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charset="utf-8" Remove unnecessary blank lines between comment sections to improve readability. Signed-off-by: Tomas Borquez --- drivers/staging/iio/frequency/ad9832.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/f= requency/ad9832.c index e2ad3e5a7a..00813dab7c 100644 --- a/drivers/staging/iio/frequency/ad9832.c +++ b/drivers/staging/iio/frequency/ad9832.c @@ -26,7 +26,6 @@ #include "dds.h" =20 /* Registers */ - #define AD9832_FREQ0LL 0x0 #define AD9832_FREQ0HL 0x1 #define AD9832_FREQ0LM 0x2 @@ -50,7 +49,6 @@ #define AD9832_OUTPUT_EN 0x13 =20 /* Command Control Bits */ - #define AD9832_CMD_PHA8BITSW 0x1 #define AD9832_CMD_PHA16BITSW 0x0 #define AD9832_CMD_FRE8BITSW 0x3 @@ -90,7 +88,6 @@ * @phase_data: tuning word spi transmit buffer * @freq_data: tuning word spi transmit buffer */ - struct ad9832_state { struct spi_device *spi; struct clk *mclk; @@ -327,7 +324,6 @@ static int ad9832_probe(struct spi_device *spi) indio_dev->modes =3D INDIO_DIRECT_MODE; =20 /* Setup default messages */ - st->xfer.tx_buf =3D &st->data; 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charset="utf-8" Use guard(mutex) for cleaner lock handling and simpler error paths. Signed-off-by: Tomas Borquez --- drivers/staging/iio/frequency/ad9832.c | 28 +++++++++++--------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/f= requency/ad9832.c index 00813dab7c..f9ef3aede4 100644 --- a/drivers/staging/iio/frequency/ad9832.c +++ b/drivers/staging/iio/frequency/ad9832.c @@ -9,6 +9,7 @@ =20 #include #include +#include #include #include #include @@ -180,9 +182,9 @@ static ssize_t ad9832_write(struct device *dev, struct = device_attribute *attr, =20 ret =3D kstrtoul(buf, 10, &val); if (ret) - goto error_ret; + return ret; =20 - mutex_lock(&st->lock); + guard(mutex)(&st->lock); switch ((u32)this_attr->address) { case AD9832_FREQ0HM: case AD9832_FREQ1HM: @@ -203,22 +205,18 @@ static ssize_t ad9832_write(struct device *dev, struc= t device_attribute *attr, ret =3D spi_sync(st->spi, &st->msg); break; case AD9832_FREQ_SYM: - if (val =3D=3D 1 || val =3D=3D 0) { - st->ctrl_fp &=3D ~AD9832_FREQ; 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charset="utf-8" Cleanup dev_err_probe() by keeping messages consistent and adding error message for clock acquisition failure. Signed-off-by: Tomas Borquez --- drivers/staging/iio/frequency/ad9832.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/f= requency/ad9832.c index f9ef3aede4..8d04f1b44f 100644 --- a/drivers/staging/iio/frequency/ad9832.c +++ b/drivers/staging/iio/frequency/ad9832.c @@ -302,15 +302,15 @@ static int ad9832_probe(struct spi_device *spi) =20 ret =3D devm_regulator_get_enable(&spi->dev, "avdd"); if (ret) - return dev_err_probe(&spi->dev, ret, "failed to enable specified AVDD vo= ltage\n"); + return dev_err_probe(&spi->dev, ret, "failed to enable AVDD supply\n"); =20 ret =3D devm_regulator_get_enable(&spi->dev, "dvdd"); if (ret) - return dev_err_probe(&spi->dev, ret, "Failed to enable specified DVDD su= pply\n"); + return dev_err_probe(&spi->dev, ret, "failed to enable DVDD supply\n"); =20 st->mclk =3D devm_clk_get_enabled(&spi->dev, "mclk"); if (IS_ERR(st->mclk)) - return PTR_ERR(st->mclk); + return dev_err_probe(&spi->dev, PTR_ERR(st->mclk), "failed to enable MCL= K\n"); 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Mon, 15 Dec 2025 11:08:32 -0800 (PST) Received: from Lewboski.localdomain ([181.191.143.42]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34abe2948d1sm9958875a91.9.2025.12.15.11.08.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Dec 2025 11:08:31 -0800 (PST) From: Tomas Borquez To: Jonathan Cameron , Greg Kroah-Hartman , Lars-Peter Clausen , Michael Hennerich Cc: David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-staging@lists.linux.dev, Tomas Borquez Subject: [PATCH 4/5] staging: iio: ad9832: convert to iio channels and ext_info attrs Date: Mon, 15 Dec 2025 16:08:05 -0300 Message-ID: <20251215190806.11003-5-tomasborquez13@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251215190806.11003-1-tomasborquez13@gmail.com> References: <20251215190806.11003-1-tomasborquez13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert ad9832 from custom sysfs attributes to standard channel interface using a single IIO_ALTCURRENT channel with ext_info attributes, as this device is a current source DAC with one output, as well as removing the dds.h header. Changes: - Add single iio_chan_spec with ext_info for frequency0/1 and phase0-3 - Phase attributes accept radians directly, driver converts internally - Frequency attributes accept Hz (unchanged) - Cache frequency and phase values in driver state for readback - Remove dependency on dds.h macros - Rename symbol attributes to frequency_symbol and phase_symbol The pincontrol_en attribute is kept temporarily with a TODO noting it should become a DT property during staging graduation. NOTE: This changes the ABI from out_altvoltage0_* to out_altcurrent0_* with different attribute organization. Signed-off-by: Tomas Borquez --- drivers/staging/iio/frequency/ad9832.c | 279 +++++++++++++++++++------ 1 file changed, 215 insertions(+), 64 deletions(-) diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/f= requency/ad9832.c index 8d04f1b44f..454a317732 100644 --- a/drivers/staging/iio/frequency/ad9832.c +++ b/drivers/staging/iio/frequency/ad9832.c @@ -24,8 +24,6 @@ #include #include =20 -#include "dds.h" - /* Registers */ #define AD9832_FREQ0LL 0x0 #define AD9832_FREQ0HL 0x1 @@ -67,6 +65,7 @@ #define AD9832_CLR BIT(11) #define AD9832_FREQ_BITS 32 #define AD9832_PHASE_BITS 12 +#define AD9832_2PI_URAD 6283185UL #define AD9832_CMD_MSK GENMASK(15, 12) #define AD9832_ADD_MSK GENMASK(11, 8) #define AD9832_DAT_MSK GENMASK(7, 0) @@ -78,6 +77,12 @@ * @ctrl_fp: cached frequency/phase control word * @ctrl_ss: cached sync/selsrc control word * @ctrl_src: cached sleep/reset/clr word + * @freq: cached frequencies + * @freq_sym: cached frequency symbol selection + * @phase: cached phases + * @phase_sym: cached phase symbol selection + * @output_en: cached output enable state + * @pinctrl_en: cached pinctrl enable state * @xfer: default spi transfer * @msg: default spi message * @freq_xfer: tuning word spi transfer @@ -95,6 +100,12 @@ struct ad9832_state { unsigned short ctrl_fp; unsigned short ctrl_ss; unsigned short ctrl_src; + u32 freq[2]; + bool freq_sym; + u32 phase[4]; + u32 phase_sym; + bool output_en; + bool pinctrl_en; struct spi_transfer xfer; struct spi_message msg; struct spi_transfer freq_xfer[4]; @@ -113,7 +124,7 @@ struct ad9832_state { } __aligned(IIO_DMA_MINALIGN); }; =20 -static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long= fout) +static unsigned long ad9832_calc_freqreg(unsigned long mclk, u32 fout) { unsigned long long freqreg =3D (u64)fout * (u64)((u64)1L << AD9832_FREQ_BITS); @@ -121,19 +132,33 @@ static unsigned long ad9832_calc_freqreg(unsigned lon= g mclk, unsigned long fout) return freqreg; } =20 -static int ad9832_write_frequency(struct ad9832_state *st, - unsigned int addr, unsigned long fout) +static ssize_t ad9832_write_frequency(struct iio_dev *indio_dev, + uintptr_t private, + struct iio_chan_spec const *chan, + const char *buf, size_t len) { + struct ad9832_state *st =3D iio_priv(indio_dev); unsigned long clk_freq; unsigned long regval; u8 regval_bytes[4]; u16 freq_cmd; + u32 fout, addr; + int ret; =20 - clk_freq =3D clk_get_rate(st->mclk); + if (private > 1) + return -EINVAL; + + addr =3D (private =3D=3D 0) ? AD9832_FREQ0HM : AD9832_FREQ1HM; =20 + ret =3D kstrtou32(buf, 10, &fout); + if (ret) + return ret; + + clk_freq =3D clk_get_rate(st->mclk); if (!clk_freq || fout > (clk_freq / 2)) return -EINVAL; =20 + guard(mutex)(&st->lock); regval =3D ad9832_calc_freqreg(clk_freq, fout); put_unaligned_be32(regval, regval_bytes); =20 @@ -145,18 +170,64 @@ static int ad9832_write_frequency(struct ad9832_state= *st, FIELD_PREP(AD9832_DAT_MSK, regval_bytes[i])); } =20 - return spi_sync(st->spi, &st->freq_msg); + ret =3D spi_sync(st->spi, &st->freq_msg); + if (ret) + return ret; + + st->freq[private] =3D fout; + + return len; } =20 -static int ad9832_write_phase(struct ad9832_state *st, - unsigned long addr, unsigned long phase) +static ssize_t ad9832_read_frequency(struct iio_dev *indio_dev, + uintptr_t private, + struct iio_chan_spec const *chan, + char *buf) +{ + struct ad9832_state *st =3D iio_priv(indio_dev); + u32 val; + + if (private > 1) + return -EINVAL; + + guard(mutex)(&st->lock); + val =3D st->freq[private]; + + return sysfs_emit(buf, "%u\n", val); +} + +static const u32 ad9832_phase_addr[] =3D { + AD9832_PHASE0H, AD9832_PHASE1H, AD9832_PHASE2H, AD9832_PHASE3H +}; + +static ssize_t ad9832_write_phase(struct iio_dev *indio_dev, + uintptr_t private, + struct iio_chan_spec const *chan, + const char *buf, size_t len) { + struct ad9832_state *st =3D iio_priv(indio_dev); u8 phase_bytes[2]; u16 phase_cmd; + u32 phase_urad, phase; + int val, val2, ret; =20 - if (phase >=3D BIT(AD9832_PHASE_BITS)) + if (private >=3D ARRAY_SIZE(ad9832_phase_addr)) return -EINVAL; =20 + ret =3D iio_str_to_fixpoint(buf, 100000, &val, &val2); + if (ret) + return ret; + + if (val < 0 || val2 < 0) + return -EINVAL; + + phase_urad =3D val * 1000000 + val2; + if (phase_urad >=3D AD9832_2PI_URAD) + return -EINVAL; + + /* Convert microradians to 12-bit phase register value (0 to 4095) */ + phase =3D ((u64)phase_urad << AD9832_PHASE_BITS) / AD9832_2PI_URAD; + + guard(mutex)(&st->lock); put_unaligned_be16(phase, phase_bytes); =20 @@ -164,14 +235,38 @@ static int ad9832_write_phase(struct ad9832_state *st, phase_cmd =3D (i % 2 =3D=3D 0) ? AD9832_CMD_PHA8BITSW : AD9832_CMD_PHA16= BITSW; =20 st->phase_data[i] =3D cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, phase_cmd) | - FIELD_PREP(AD9832_ADD_MSK, addr - i) | + FIELD_PREP(AD9832_ADD_MSK, ad9832_phase_addr[private] - i) | FIELD_PREP(AD9832_DAT_MSK, phase_bytes[i])); } =20 - return spi_sync(st->spi, &st->phase_msg); + ret =3D spi_sync(st->spi, &st->phase_msg); + if (ret) + return ret; + + st->phase[private] =3D phase; + + return len; +} + +static ssize_t ad9832_read_phase(struct iio_dev *indio_dev, + uintptr_t private, + struct iio_chan_spec const *chan, + char *buf) +{ + struct ad9832_state *st =3D iio_priv(indio_dev); + u32 phase_urad; + + if (private >=3D ARRAY_SIZE(ad9832_phase_addr)) + return -EINVAL; + + guard(mutex)(&st->lock); + phase_urad =3D ((u64)st->phase[private] * AD9832_2PI_URAD) >> AD9832_PHAS= E_BITS; + + return sysfs_emit(buf, "%u.%06u\n", phase_urad / 1000000, phase_urad % 10= 00000); } =20 -static ssize_t ad9832_write(struct device *dev, struct device_attribute *a= ttr, +static ssize_t ad9832_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t len) { struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); @@ -185,34 +280,20 @@ static ssize_t ad9832_write(struct device *dev, struc= t device_attribute *attr, return ret; =20 guard(mutex)(&st->lock); - switch ((u32)this_attr->address) { - case AD9832_FREQ0HM: - case AD9832_FREQ1HM: - ret =3D ad9832_write_frequency(st, this_attr->address, val); - break; - case AD9832_PHASE0H: - case AD9832_PHASE1H: - case AD9832_PHASE2H: - case AD9832_PHASE3H: - ret =3D ad9832_write_phase(st, this_attr->address, val); - break; - case AD9832_PINCTRL_EN: - st->ctrl_ss &=3D ~AD9832_SELSRC; - st->ctrl_ss |=3D FIELD_PREP(AD9832_SELSRC, val ? 0 : 1); - - st->data =3D cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SYNCSELSR= C) | - st->ctrl_ss); - ret =3D spi_sync(st->spi, &st->msg); - break; + switch (this_attr->address) { case AD9832_FREQ_SYM: if (val !=3D 1 && val !=3D 0) return -EINVAL; =20 st->ctrl_fp &=3D ~AD9832_FREQ; - st->ctrl_fp |=3D FIELD_PREP(AD9832_FREQ, val ? 1 : 0); + st->ctrl_fp |=3D FIELD_PREP(AD9832_FREQ, val); st->data =3D cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_FPSELECT)= | st->ctrl_fp); ret =3D spi_sync(st->spi, &st->msg); + if (ret) + return ret; + + st->freq_sym =3D val; break; case AD9832_PHASE_SYM: if (val > 3) @@ -224,8 +305,15 @@ static ssize_t ad9832_write(struct device *dev, struct= device_attribute *attr, st->data =3D cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_FPSELECT)= | st->ctrl_fp); ret =3D spi_sync(st->spi, &st->msg); + if (ret) + return ret; + + st->phase_sym =3D val; break; case AD9832_OUTPUT_EN: + if (val !=3D 1 && val !=3D 0) + return -EINVAL; + if (val) st->ctrl_src &=3D ~(AD9832_RESET | AD9832_SLEEP | AD9832_CLR); else @@ -234,49 +322,110 @@ static ssize_t ad9832_write(struct device *dev, stru= ct device_attribute *attr, st->data =3D cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SLEEPRESC= LR) | st->ctrl_src); ret =3D spi_sync(st->spi, &st->msg); + if (ret) + return ret; + + st->output_en =3D val; + break; + case AD9832_PINCTRL_EN: + if (val !=3D 1 && val !=3D 0) + return -EINVAL; + + st->ctrl_ss &=3D ~AD9832_SELSRC; + st->ctrl_ss |=3D FIELD_PREP(AD9832_SELSRC, val ? 0 : 1); + + st->data =3D cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SYNCSELSR= C) | + st->ctrl_ss); + ret =3D spi_sync(st->spi, &st->msg); + if (ret) + return ret; + + st->pinctrl_en =3D val; break; default: return -ENODEV; } =20 - return ret ? ret : len; + return len; } =20 -/* - * see dds.h for further information - */ +static ssize_t ad9832_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct ad9832_state *st =3D iio_priv(indio_dev); + struct iio_dev_attr *this_attr =3D to_iio_dev_attr(attr); =20 -static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9832_write, AD9832_FREQ0HM); -static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9832_write, AD9832_FREQ1HM); -static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9832_write, AD9832_FREQ_SY= M); -static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */ + guard(mutex)(&st->lock); + switch (this_attr->address) { + case AD9832_FREQ_SYM: + return sysfs_emit(buf, "%u\n", st->freq_sym); + case AD9832_PHASE_SYM: + return sysfs_emit(buf, "%u\n", st->phase_sym); + case AD9832_OUTPUT_EN: + return sysfs_emit(buf, "%u\n", st->output_en); + case AD9832_PINCTRL_EN: + return sysfs_emit(buf, "%u\n", st->pinctrl_en); + default: + return -ENODEV; + } +} + +#define AD9832_CHAN_FREQ(_name, _channel) { \ + .name =3D _name, \ + .write =3D ad9832_write_frequency, \ + .read =3D ad9832_read_frequency, \ + .private =3D _channel, \ + .shared =3D IIO_SEPARATE, \ +} + +#define AD9832_CHAN_PHASE(_name, _channel) { \ + .name =3D _name, \ + .write =3D ad9832_write_phase, \ + .read =3D ad9832_read_phase, \ + .private =3D _channel, \ + .shared =3D IIO_SEPARATE, \ +} + +static const struct iio_chan_spec_ext_info ad9832_ext_info[] =3D { + AD9832_CHAN_FREQ("frequency0", 0), + AD9832_CHAN_FREQ("frequency1", 1), + AD9832_CHAN_PHASE("phase0", 0), + AD9832_CHAN_PHASE("phase1", 1), + AD9832_CHAN_PHASE("phase2", 2), + AD9832_CHAN_PHASE("phase3", 3), + { } +}; =20 -static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9832_write, AD9832_PHASE0H); -static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9832_write, AD9832_PHASE1H); -static IIO_DEV_ATTR_PHASE(0, 2, 0200, NULL, ad9832_write, AD9832_PHASE2H); -static IIO_DEV_ATTR_PHASE(0, 3, 0200, NULL, ad9832_write, AD9832_PHASE3H); -static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL, - ad9832_write, AD9832_PHASE_SYM); -static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/ +static const struct iio_chan_spec ad9832_channels[] =3D { + { + .type =3D IIO_ALTCURRENT, + .output =3D 1, + .indexed =3D 1, + .channel =3D 0, + .ext_info =3D ad9832_ext_info, + }, +}; =20 -static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL, - ad9832_write, AD9832_PINCTRL_EN); -static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL, - ad9832_write, AD9832_OUTPUT_EN); +static IIO_DEVICE_ATTR(out_altcurrent0_frequency_symbol, 0644, + ad9832_show, ad9832_store, AD9832_FREQ_SYM); +static IIO_DEVICE_ATTR(out_altcurrent0_phase_symbol, 0644, + ad9832_show, ad9832_store, AD9832_PHASE_SYM); +static IIO_DEVICE_ATTR(out_altcurrent0_enable, 0644, + ad9832_show, ad9832_store, AD9832_OUTPUT_EN); +/* + * TODO: Convert to DT property when graduating from staging. + * Pin control configuration depends on hardware wiring. + */ +static IIO_DEVICE_ATTR(out_altcurrent0_pincontrol_en, 0644, + ad9832_show, ad9832_store, AD9832_PINCTRL_EN); =20 static struct attribute *ad9832_attributes[] =3D { - &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr, - &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phase2.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phase3.dev_attr.attr, - &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr, + &iio_dev_attr_out_altcurrent0_frequency_symbol.dev_attr.attr, + &iio_dev_attr_out_altcurrent0_phase_symbol.dev_attr.attr, + &iio_dev_attr_out_altcurrent0_enable.dev_attr.attr, + &iio_dev_attr_out_altcurrent0_pincontrol_en.dev_attr.attr, NULL, }; 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Mon, 15 Dec 2025 11:08:35 -0800 (PST) Received: from Lewboski.localdomain ([181.191.143.42]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34abe2948d1sm9958875a91.9.2025.12.15.11.08.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Dec 2025 11:08:35 -0800 (PST) From: Tomas Borquez To: Jonathan Cameron , Greg Kroah-Hartman , Lars-Peter Clausen , Michael Hennerich Cc: David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-staging@lists.linux.dev, Tomas Borquez Subject: [PATCH 5/5] staging: iio: ad9832: add sysfs documentation Date: Mon, 15 Dec 2025 16:08:06 -0300 Message-ID: <20251215190806.11003-6-tomasborquez13@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251215190806.11003-1-tomasborquez13@gmail.com> References: <20251215190806.11003-1-tomasborquez13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add sysfs ABI documentation for the AD9832/AD9835 Direct Digital Synthesizer chips, documenting frequency, phase, output control, and pin control attributes. Signed-off-by: Tomas Borquez --- .../Documentation/sysfs-bus-iio-dds-ad9832 | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 drivers/staging/iio/Documentation/sysfs-bus-iio-dds-ad9= 832 diff --git a/drivers/staging/iio/Documentation/sysfs-bus-iio-dds-ad9832 b/d= rivers/staging/iio/Documentation/sysfs-bus-iio-dds-ad9832 new file mode 100644 index 0000000000..5ceea57917 --- /dev/null +++ b/drivers/staging/iio/Documentation/sysfs-bus-iio-dds-ad9832 @@ -0,0 +1,41 @@ +What: /sys/bus/iio/devices/iio:deviceX/out_altcurrent0_frequencyY +KernelVersion: 6.19 +Contact: linux-iio@vger.kernel.org +Description: + Frequency in Hz for frequency register Y (0-1). The active + frequency register is selected via out_altcurrent0_frequency_symbol. + +What: /sys/bus/iio/devices/iio:deviceX/out_altcurrent0_phaseY +KernelVersion: 6.19 +Contact: linux-iio@vger.kernel.org +Description: + Phase offset in radians for phase register Y (0-3). Valid + range is 0 to 2*PI (exclusive) with 12-bit hardware resolution. The + active phase register is selected via out_altcurrent0_phase_symbol. + +What: /sys/bus/iio/devices/iio:deviceX/out_altcurrent0_frequency_symbol +KernelVersion: 6.19 +Contact: linux-iio@vger.kernel.org +Description: + Selects which frequency register (0 or 1) is active for output. + +What: /sys/bus/iio/devices/iio:deviceX/out_altcurrent0_phase_symbol +KernelVersion: 6.19 +Contact: linux-iio@vger.kernel.org +Description: + Selects which phase register (0-3) is active for output. + +What: /sys/bus/iio/devices/iio:deviceX/out_altcurrent0_enable +KernelVersion: 6.19 +Contact: linux-iio@vger.kernel.org +Description: + Enables (1) or disables (0) the output. When disabled, the + device is held in reset state. + +What: /sys/bus/iio/devices/iio:deviceX/out_altcurrent0_pincontrol_en +KernelVersion: 6.19 +Contact: linux-iio@vger.kernel.org +Description: + Enables (1) or disables (0) hardware pin control for frequency + and phase selection. When enabled, external pins control + register selection instead of software. --=20 2.43.0