From nobody Tue Dec 16 06:36:31 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F9C7342CA7; Mon, 15 Dec 2025 14:29:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765808961; cv=none; b=Kiro+lVDYp1yQuH6T/YnGLYcZ1YTCEfP1PKz0JAsKC0oV/T7RaE5HPzN8Zmm14AHsWbdopJ/fKn5U51/r4q2wQHOoQNj8vqrUHZ/dEU5MHZgyb/JFeZAnqkVYRCDDrppKa9iqPb9UFAG+V1PNpZL9OS62TcEITxj4It5YQIoDJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765808961; c=relaxed/simple; bh=4GZ4PC1exa4cMbAQRAqppA0POrS8E+SfOXMDunXF9Ps=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Wzu2mRpcYprewAEQ3a3eyYhaBpv7WU0zWWKnX5zfzkyjf3xDKurOi3g84/72FH6Ntr/10o6nfO1RE0/ddj/hLVtnWhIv3GS2JOiklmvMJoChqGdsBZ92+9Sy5E5Flvyzxlg8T7vu1Lu0r95aA/X/A33AzKf81zoHf8582OZlZy8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=AfCoPD02; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="AfCoPD02" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 807D8C19D20; Mon, 15 Dec 2025 14:28:53 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id DADD460664; Mon, 15 Dec 2025 14:29:17 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 215BB1194242B; Mon, 15 Dec 2025 15:29:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1765808956; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Ud8IKjpsg+ngLvEK4RxM9S54xPs2+N6xUI86CqmgS9o=; b=AfCoPD02/kkEkA/2hFnhtx2HZEuX6CYmEx98oh9SE7HQXV6o7qj0g5f7BLeXWWe2m76j/z JZtkNsdeOLYogjvSc0PPX9dVHgWipVeeQtsZ2FouOWXxWPLUagfWi7PtX59VFWaIYLvjgE lWIKWMIfZEgU6EysExU725sLIiuPsRAIQbDPc4v1S6esg/1PDlIKAEtyPg/SI5B+/F72cX jl7sh6RmSgoAArN5xQc9If01jLeWBvyoVzPEmshAUD4nDWvpgh/klxRQPnqH/LB2LZ2iVx kSFYUoy40E4t6PLxcANa0nAuq8IaBqkUiM4eTmnaIqo4mrziKg2jS00TW26pgA== From: "Herve Codina (Schneider Electric)" To: Thomas Gleixner , Wolfram Sang , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Saravana Kannan , Herve Codina Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni , Bartosz Golaszewski Subject: [PATCH v7 8/8] ARM: dts: r9a06g032: Add support for GPIO interrupts Date: Mon, 15 Dec 2025 15:28:30 +0100 Message-ID: <20251215142836.167101-9-herve.codina@bootlin.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251215142836.167101-1-herve.codina@bootlin.com> References: <20251215142836.167101-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" In the RZ/N1 SoC, the GPIO interrupts are multiplexed using the GPIO Interrupt Multiplexer. Add the multiplexer node and connect GPIO interrupt lines to the multiplexer. The interrupt-map available in the multiplexer node has to be updated in dts files depending on the GPIO usage. Indeed, the usage of an interrupt for a GPIO is board dependent. Up to 8 GPIOs can be used as an interrupt line (one per multiplexer output interrupt). Signed-off-by: Herve Codina (Schneider Electric) Reviewed-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Reviewed-by: Wolfram Sang --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index 06d35a83f6e1..b8e03c529007 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -543,6 +543,14 @@ gpio0a: gpio-port@0 { gpio-controller; #gpio-cells =3D <2>; snps,nr-gpios =3D <32>; + + interrupt-controller; + interrupt-parent =3D <&gpioirqmux>; + interrupts =3D <0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31>; + #interrupt-cells =3D <2>; }; =20 /* GPIO0b[0..1] connected to pins GPIO1..2 */ @@ -584,6 +592,14 @@ gpio1a: gpio-port@0 { gpio-controller; #gpio-cells =3D <2>; snps,nr-gpios =3D <32>; + + interrupt-controller; + interrupt-parent =3D <&gpioirqmux>; + interrupts =3D <32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63>; + #interrupt-cells =3D <2>; }; =20 /* GPIO1b[0..1] connected to pins GPIO55..56 */ @@ -615,6 +631,14 @@ gpio2a: gpio-port@0 { gpio-controller; #gpio-cells =3D <2>; snps,nr-gpios =3D <32>; + + interrupt-controller; + interrupt-parent =3D <&gpioirqmux>; + interrupts =3D <64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95>; + #interrupt-cells =3D <2>; }; =20 /* GPIO2b[0..9] connected to pins GPIO160..169 */ @@ -627,6 +651,23 @@ gpio2b: gpio-port@1 { }; }; =20 + gpioirqmux: interrupt-controller@51000480 { + compatible =3D "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux= "; + reg =3D <0x51000480 0x20>; + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + interrupt-map-mask =3D <0x7f>; + + /* + * Example mapping entry. Board DTs need to overwrite + * 'interrupt-map' with their specific mapping. Check + * the irqmux binding documentation for details. + */ + interrupt-map =3D <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + can0: can@52104000 { compatible =3D "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; reg =3D <0x52104000 0x800>; --=20 2.52.0