From nobody Tue Dec 16 06:35:50 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56022342514 for ; Mon, 15 Dec 2025 14:29:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765808957; cv=none; b=NgqUxB/kiZa81Kh+8fAYGtVweBukLNFLxWhtdmXttIJEQJFgujMn7z6NsVNPOZPHJF555borpTUIkJky2wytFTRLDudBGvRG4U0dUUF+4xAH9SFpgktVXBjYwSBGRgAeBNl8ec2aay2YxSpTs/aaSOiUtflLFSCxmVQgPrws6dE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765808957; c=relaxed/simple; bh=cPYz7Rl3IGZjYUip8LQYzhHjmVpG6HFaUtmNGOzanJw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VYg0eJBuDwgQGg/SNz0zVUxe7fijhcS1DpTrncp1r5QeRqMUjXIDD/J1uc1Nyk33vmfiaM1ckuU7SO2WVjMQkjP8Fh+uXSwqhzj1pSeRiijMnyrl0IFMccc3AtDwRjrLrs3+uua7B048MZumwtOhS2EbLS5Gwq4OW+p6FmHRDs0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=rU90B1nY; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="rU90B1nY" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 2E87D1A21DA; Mon, 15 Dec 2025 14:29:14 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id F1B0D60664; Mon, 15 Dec 2025 14:29:13 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id AF70511942426; Mon, 15 Dec 2025 15:29:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1765808952; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=C57NZV6yvzIJfDxz/lCn6sc57mHd2EX6xsrZ1yoZq3Q=; b=rU90B1nYRrdEP+GREE97o2Bw4N0UinNDMXfa+CeI8UK1AN3/+IIvwUETgqrDLCiE5UBRRH a6sYv/g9FDj903huAMEQlM8EMyZHtb3djbPV2Z6qfdz1AmymQidLKe2yfNCYp03LEbF/L1 hbxA6xx/3EAUhGDxrdPAia0kwmV7q3+Xvade1tLf1+09vsZwD5qOVw6RTRq3PAGz/raD6p RArNH9ud1heNbGTNH7eiTKI+1K6t9Qxuw/TJ8zNa+3iDNGbIetEZaCIVex3dbksnL3I0Sj 5op4DZlb1QnboUbeoYf96tZmqIfHF5JzuH4M62ifO+VK0Uy/T6pv5OWIkMo8hw== From: "Herve Codina (Schneider Electric)" To: Thomas Gleixner , Wolfram Sang , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Saravana Kannan , Herve Codina Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni Subject: [PATCH v7 6/8] dt-bindings: soc: renesas: Add the Renesas RZ/N1 GPIO Interrupt Multiplexer Date: Mon, 15 Dec 2025 15:28:28 +0100 Message-ID: <20251215142836.167101-7-herve.codina@bootlin.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251215142836.167101-1-herve.codina@bootlin.com> References: <20251215142836.167101-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines. The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines. Signed-off-by: Herve Codina (Schneider Electric) Reviewed-by: Wolfram Sang Reviewed-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Reviewed-by: Geert Uytterhoeven --- .../soc/renesas/renesas,rzn1-gpioirqmux.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r= zn1-gpioirqmux.yaml diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpi= oirqmux.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-g= pioirqmux.yaml new file mode 100644 index 000000000000..1a31c11bc3b4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux= .yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,rzn1-gpioirqmux.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 SoCs GPIO Interrupt Multiplexer + +description: | + The Renesas RZ/N1 GPIO Interrupt Multiplexer multiplexes GPIO interrupt + lines to the interrupt controller available in the SoC. + + It selects up to 8 of the 96 GPIO interrupt lines available and connect= them + to 8 output interrupt lines. + +maintainers: + - Herve Codina + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-gpioirqmux + - const: renesas,rzn1-gpioirqmux + + reg: + maxItems: 1 + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: + items: + - const: 0x7f + + interrupt-map: + description: | + Specifies the mapping from external GPIO interrupt lines to the outp= ut + interrupts. The array has up to 8 items defining the mapping related= to + the output line 0 (GIC 103) up to the output line 7 (GIC 110). + + The child interrupt number set in arrays items is computed using the + following formula: + gpio_bank * 32 + gpio_number + with: + - gpio_bank: The GPIO bank number + - 0 for GPIO0A, + - 1 for GPIO1A, + - 2 for GPIO2A + - gpio_number: Number of the gpio in the bank (0..31) + minItems: 1 + maxItems: 8 + +required: + - compatible + - reg + - "#address-cells" + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +additionalProperties: false + +examples: + - | + #include + + gic: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <3>; + }; + + interrupt-controller@51000480 { + compatible =3D "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioi= rqmux"; + reg =3D <0x51000480 0x20>; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0x7f>; + interrupt-map =3D + <32 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* line 0, GPIO1A.0= */ + <89 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* line 1, GPIO2A.2= 5 */ + <9 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; /* line 3, GPIO0A.9 = */ + }; --=20 2.52.0