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Mon, 15 Dec 2025 06:16:40 -0800 (PST) From: Anand Moon To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon , Mikko Perttunen Subject: [PATCH v2 3/4] PCI: tegra: Use readl_poll_timeout() for link status polling Date: Mon, 15 Dec 2025 19:45:36 +0530 Message-ID: <20251215141603.6749-4-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251215141603.6749-1-linux.amoon@gmail.com> References: <20251215141603.6749-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the manual `do-while` polling loops with the readl_poll_timeout() helper when checking the link DL_UP and DL_LINK_ACTIVE status bits during link bring-up. This simplifies the code by removing the open-coded timeout logic in favor of the standard, more robust iopoll framework. The change improves readability and reduces code duplication. Cc: Thierry Reding Signed-off-by: Anand Moon --- v2: None v1: dropped the include header file. --- drivers/pci/controller/pci-tegra.c | 37 +++++++++++------------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pc= i-tegra.c index 275d9295789a..336d2cf4d828 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -2156,37 +2156,28 @@ static bool tegra_pcie_port_check_link(struct tegra= _pcie_port *port) value |=3D RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; writel(value, port->base + RP_PRIV_MISC); =20 - do { - unsigned int timeout =3D TEGRA_PCIE_LINKUP_TIMEOUT; + while (retries--) { + int err; =20 - do { - value =3D readl(port->base + RP_VEND_XP); - - if (value & RP_VEND_XP_DL_UP) - break; - - usleep_range(1000, 2000); - } while (--timeout); - - if (!timeout) { + err =3D readl_poll_timeout(port->base + RP_VEND_XP, value, + value & RP_VEND_XP_DL_UP, + 1000, + TEGRA_PCIE_LINKUP_TIMEOUT * 1000); + if (err) { dev_dbg(dev, "link %u down, retrying\n", port->index); goto retry; } =20 - timeout =3D TEGRA_PCIE_LINKUP_TIMEOUT; - - do { - value =3D readl(port->base + RP_LINK_CONTROL_STATUS); - - if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) - return true; - - usleep_range(1000, 2000); - } while (--timeout); + err =3D readl_poll_timeout(port->base + RP_LINK_CONTROL_STATUS, + value, + value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE, + 1000, TEGRA_PCIE_LINKUP_TIMEOUT * 1000); + if (!err) + return true; =20 retry: tegra_pcie_port_reset(port); - } while (--retries); + } =20 return false; } --=20 2.50.1