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charset="utf-8" From: Sachin Gupta With the current DLL sequence stability issues for data transfer seen in HS400 and HS200 modes. "mmc0: cqhci: error IRQ status: 0x00000000 cmd error -84 data error 0" Rectify the DLL programming sequence as per latest hardware programming guide Signed-off-by: Sachin Gupta Signed-off-by: Ram Prakash Gupta --- drivers/mmc/host/sdhci-msm.c | 277 ++++++++++++++++++++++++++++++++--- 1 file changed, 260 insertions(+), 17 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 1fcd92158bee..f459b40db41c 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -28,6 +28,7 @@ #define CORE_VERSION_MAJOR_SHIFT 28 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT) #define CORE_VERSION_MINOR_MASK 0xff +#define SDHCI_MSM_MIN_V_7FF 0x6e =20 #define CORE_MCI_GENERICS 0x70 #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29) @@ -119,7 +120,8 @@ #define CORE_PWRSAVE_DLL BIT(3) =20 #define DDR_CONFIG_POR_VAL 0x80040873 - +#define DLL_CONFIG_3_POR_VAL 0x10 +#define TCXO_FREQ 19200000 =20 #define INVALID_TUNING_PHASE -1 #define SDHCI_MSM_MIN_CLOCK 400000 @@ -319,6 +321,15 @@ struct sdhci_msm_host { bool artanis_dll; }; =20 +enum dll_init_context { + DLL_INIT_NORMAL, +}; + +enum mode { + HS400, // equivalent to SDR104 mode for DLL. + HS200, // equivalent to SDR50 mode for DLL. +}; + static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_h= ost *host) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); @@ -805,6 +816,207 @@ static int msm_init_cm_dll(struct sdhci_host *host) return 0; } =20 +static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) +{ + return SDHCI_MSM_MIN_CLOCK; +} + +static unsigned int sdhci_msm_get_clk_rate(struct sdhci_host *host, u32 re= q_clk) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + struct clk *core_clk =3D msm_host->bulk_clks[0].clk; + struct mmc_ios ios =3D host->mmc->ios; + unsigned int sup_clk; + + if (req_clk < sdhci_msm_get_min_clock(host)) + return sdhci_msm_get_min_clock(host); + + sup_clk =3D clk_get_rate(core_clk); + + if (ios.timing =3D=3D MMC_TIMING_MMC_HS400 || + host->flags & SDHCI_HS400_TUNING) + sup_clk =3D sup_clk / 2; + + return sup_clk; +} + +/* Initialize the DLL (Programmable Delay Line) */ +static int sdhci_msm_configure_dll(struct sdhci_host *host, enum dll_init_= context + init_context, enum mode index) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + const struct sdhci_msm_offset *msm_offset =3D msm_host->offset; + struct mmc_host *mmc =3D host->mmc; + u32 ddr_cfg_offset, core_vendor_spec, config; + void __iomem *ioaddr =3D host->ioaddr; + unsigned long flags, dll_clock; + int rc =3D 0; + u32 dll_lock; + + dll_clock =3D sdhci_msm_get_clk_rate(host, host->clock); + spin_lock_irqsave(&host->lock, flags); + + core_vendor_spec =3D readl_relaxed(ioaddr + msm_offset->core_vendor_spec); + + /* + * Always disable PWRSAVE during the DLL power + * up regardless of its current setting. + */ + core_vendor_spec &=3D ~CORE_CLK_PWRSAVE; + writel_relaxed(core_vendor_spec, ioaddr + msm_offset->core_vendor_spec); + + if (msm_host->use_14lpp_dll_reset) { + /* Disable CK_OUT */ + config =3D readl_relaxed(ioaddr + msm_offset->core_dll_config); + config &=3D ~CORE_CK_OUT_EN; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* Disable the DLL clock */ + config =3D readl_relaxed(ioaddr + msm_offset->core_dll_config_2); + config |=3D CORE_DLL_CLOCK_DISABLE; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config_2); + } + + /* + * Write 1 to DLL_RST bit of DLL_CONFIG register + * and Write 1 to DLL_PDN bit of DLL_CONFIG register. + */ + config =3D readl_relaxed(ioaddr + msm_offset->core_dll_config); + config |=3D (CORE_DLL_RST | CORE_DLL_PDN); + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* + * Configure DLL_CONFIG_3 and USER_CTRL + * (Only applicable for 7FF projects). + */ + if (msm_host->core_minor >=3D SDHCI_MSM_MIN_V_7FF) { + writel_relaxed(msm_host->dll[index].dll_config_3, + ioaddr + msm_offset->core_dll_config_3); + writel_relaxed(msm_host->dll[index].dll_usr_ctl, + ioaddr + msm_offset->core_dll_usr_ctl); + } + + /* + * Set DDR_CONFIG since step 7 is setting TEST_CTRL that can be skipped. + */ + ddr_cfg_offset =3D msm_host->updated_ddr_cfg ? msm_offset->core_ddr_config + : msm_offset->core_ddr_config_old; + + config =3D msm_host->dll[index].ddr_config; + writel_relaxed(config, ioaddr + ddr_cfg_offset); + + /* Set DLL_CONFIG_2 */ + if (msm_host->use_14lpp_dll_reset) { + u32 mclk_freq; + int cycle_cnt; + + /* + * Only configure the mclk_freq in normal DLL init + * context. If the DLL init is coming from + * CX Collapse Exit context, the host->clock may be zero. + * The DLL_CONFIG_2 register has already been restored to + * proper value prior to getting here. + */ + if (init_context =3D=3D DLL_INIT_NORMAL) { + cycle_cnt =3D readl_relaxed(ioaddr + + msm_offset->core_dll_config_2) + & CORE_FLL_CYCLE_CNT ? 8 : 4; + + mclk_freq =3D DIV_ROUND_CLOSEST_ULL(dll_clock * cycle_cnt, TCXO_FREQ); + + if (dll_clock < 100000000) { + pr_err("%s: %s: Non standard clk freq =3D%u\n", + mmc_hostname(mmc), __func__, dll_clock); + rc =3D -EINVAL; + goto out; + } + + config =3D readl_relaxed(ioaddr + msm_offset->core_dll_config_2); + config =3D (config & ~GENMASK(17, 10)) | + FIELD_PREP(GENMASK(17, 10), mclk_freq); + writel_relaxed(config, ioaddr + msm_offset->core_dll_config_2); + } + /* wait for 5us before enabling DLL clock */ + udelay(5); + } + + config =3D msm_host->dll[index].dll_config; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* Wait for 52us */ + spin_unlock_irqrestore(&host->lock, flags); + usleep_range(60, 70); + spin_lock_irqsave(&host->lock, flags); + + /* + * Write 0 to DLL_RST bit of DLL_CONFIG register + * and Write 0 to DLL_PDN bit of DLL_CONFIG register. + */ + config &=3D ~CORE_DLL_RST; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + config &=3D ~CORE_DLL_PDN; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + /* Write 1 to DLL_RST bit of DLL_CONFIG register */ + config |=3D CORE_DLL_RST; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* Write 0 to DLL_RST bit of DLL_CONFIG register */ + config &=3D ~CORE_DLL_RST; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* Set CORE_DLL_CLOCK_DISABLE to 0 */ + if (msm_host->use_14lpp_dll_reset) { + config =3D readl_relaxed(ioaddr + msm_offset->core_dll_config_2); + config &=3D ~CORE_DLL_CLOCK_DISABLE; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config_2); + } + + /* Set DLL_EN bit to 1. */ + config =3D readl_relaxed(ioaddr + msm_offset->core_dll_config); + config |=3D CORE_DLL_EN; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* + * Wait for 8000 input clock. Here we calculate the + * delay from fixed clock freq 192MHz, which turns out 42us. + */ + spin_unlock_irqrestore(&host->lock, flags); + usleep_range(50, 60); + spin_lock_irqsave(&host->lock, flags); + + /* Set CK_OUT_EN bit to 1. */ + config |=3D CORE_CK_OUT_EN; + writel_relaxed(config, ioaddr + msm_offset->core_dll_config); + + /* + * Wait until DLL_LOCK bit of DLL_STATUS register + * becomes '1'. + */ + rc =3D readl_relaxed_poll_timeout(ioaddr + + msm_offset->core_dll_status, + dll_lock, + dll_lock & CORE_DLL_LOCK, + 10, + 100); + if (rc =3D=3D -ETIMEDOUT) + pr_err("%s: Unable to get DLL_LOCK, dll_status: 0x%08x\n", + mmc_hostname(host->mmc), dll_lock); + +out: + if (core_vendor_spec & CORE_CLK_PWRSAVE) { + /* Reenable PWRSAVE as needed */ + config =3D readl_relaxed(ioaddr + msm_offset->core_vendor_spec); + config |=3D CORE_CLK_PWRSAVE; + writel_relaxed(config, ioaddr + msm_offset->core_vendor_spec); + } + + spin_unlock_irqrestore(&host->lock, flags); + return rc; +} + static void msm_hc_select_default(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); @@ -927,6 +1139,24 @@ static void sdhci_msm_hc_select_mode(struct sdhci_hos= t *host) msm_hc_select_default(host); } =20 +static int sdhci_msm_init_dll(struct sdhci_host *host, enum dll_init_conte= xt init_context) +{ + if (host->mmc->ios.timing =3D=3D MMC_TIMING_UHS_SDR104 || + host->mmc->ios.timing =3D=3D MMC_TIMING_MMC_HS400) + return sdhci_msm_configure_dll(host, init_context, HS400); + + return sdhci_msm_configure_dll(host, init_context, HS200); +} + +static int sdhci_msm_dll_config(struct sdhci_host *host, enum dll_init_con= text init_context) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + + return msm_host->artanis_dll ? sdhci_msm_init_dll(host, init_context) : + msm_init_cm_dll(host); +} + static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); @@ -942,7 +1172,7 @@ static int sdhci_msm_cdclp533_calibration(struct sdhci= _host *host) * Retuning in HS400 (DDR mode) will fail, just reset the * tuning block and restore the saved tuning phase. */ - ret =3D msm_init_cm_dll(host); + ret =3D sdhci_msm_dll_config(host, DLL_INIT_NORMAL); if (ret) goto out; =20 @@ -1030,7 +1260,7 @@ static int sdhci_msm_cdclp533_calibration(struct sdhc= i_host *host) return ret; } =20 -static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) +static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host, enum= mode index) { struct mmc_host *mmc =3D host->mmc; u32 dll_status, config, ddr_cfg_offset; @@ -1053,7 +1283,11 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct = sdhci_host *host) ddr_cfg_offset =3D msm_offset->core_ddr_config; else ddr_cfg_offset =3D msm_offset->core_ddr_config_old; - writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset); + + if (msm_host->artanis_dll) + writel_relaxed(msm_host->dll[index].ddr_config, host->ioaddr + ddr_cfg_o= ffset); + else + writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset); =20 if (mmc->ios.enhanced_strobe) { config =3D readl_relaxed(host->ioaddr + @@ -1122,7 +1356,8 @@ static int sdhci_msm_hs400_dll_calibration(struct sdh= ci_host *host) * Retuning in HS400 (DDR mode) will fail, just reset the * tuning block and restore the saved tuning phase. */ - ret =3D msm_init_cm_dll(host); + ret =3D sdhci_msm_dll_config(host, DLL_INIT_NORMAL); + if (ret) goto out; =20 @@ -1142,7 +1377,7 @@ static int sdhci_msm_hs400_dll_calibration(struct sdh= ci_host *host) if (msm_host->use_cdclp533) ret =3D sdhci_msm_cdclp533_calibration(host); else - ret =3D sdhci_msm_cm_dll_sdc4_calibration(host); + ret =3D sdhci_msm_cm_dll_sdc4_calibration(host, HS400); out: pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), __func__, ret); @@ -1185,7 +1420,8 @@ static int sdhci_msm_restore_sdr_dll_config(struct sd= hci_host *host) return 0; =20 /* Reset the tuning block */ - ret =3D msm_init_cm_dll(host); + ret =3D sdhci_msm_dll_config(host, DLL_INIT_NORMAL); + if (ret) return ret; =20 @@ -1227,6 +1463,7 @@ static int sdhci_msm_execute_tuning(struct mmc_host *= mmc, u32 opcode) struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); const struct sdhci_msm_offset *msm_offset =3D msm_host->offset; u32 config; + bool hs400_tuning; =20 if (!sdhci_msm_is_tuning_needed(host)) { msm_host->use_cdr =3D false; @@ -1256,17 +1493,23 @@ static int sdhci_msm_execute_tuning(struct mmc_host= *mmc, u32 opcode) * - select MCLK/2 in VENDOR_SPEC * - program MCLK to 400MHz (or nearest supported) in GCC */ - if (host->flags & SDHCI_HS400_TUNING) { + hs400_tuning =3D !!(host->flags & SDHCI_HS400_TUNING); + if (hs400_tuning) { sdhci_msm_hc_select_mode(host); msm_set_clock_rate_for_bus_mode(host, ios.clock, ios.timing); - host->flags &=3D ~SDHCI_HS400_TUNING; } =20 retry: /* First of all reset the tuning block */ - rc =3D msm_init_cm_dll(host); - if (rc) + rc =3D sdhci_msm_dll_config(host, DLL_INIT_NORMAL); + if (rc) { + if (hs400_tuning) + host->flags &=3D ~SDHCI_HS400_TUNING; return rc; + } + + if (hs400_tuning) + host->flags &=3D ~SDHCI_HS400_TUNING; =20 phase =3D 0; do { @@ -1297,6 +1540,8 @@ static int sdhci_msm_execute_tuning(struct mmc_host *= mmc, u32 opcode) mmc_hostname(mmc)); if (--tuning_seq_cnt) { tuned_phase_cnt =3D 0; + if (hs400_tuning) + host->flags |=3D SDHCI_HS400_TUNING; goto retry; } } @@ -1319,8 +1564,11 @@ static int sdhci_msm_execute_tuning(struct mmc_host = *mmc, u32 opcode) dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n", mmc_hostname(mmc), phase); } else { - if (--tuning_seq_cnt) + if (--tuning_seq_cnt) { + if (hs400_tuning) + host->flags |=3D SDHCI_HS400_TUNING; goto retry; + } /* Tuning failed */ dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n", mmc_hostname(mmc)); @@ -1847,11 +2095,6 @@ static unsigned int sdhci_msm_get_max_clock(struct s= dhci_host *host) return clk_round_rate(core_clk, ULONG_MAX); } =20 -static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) -{ - return SDHCI_MSM_MIN_CLOCK; -} - /* * __sdhci_msm_set_clock - sdhci_msm clock control. * --=20 2.34.1