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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f1bd6b50afsm90557971cf.21.2025.12.15.00.40.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Dec 2025 00:40:36 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, yongxing.mou@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, Dmitry Baryshkov Subject: [PATCH v3 06/11] drm/msm/dsi/phy: Add support for Kaanapali Date: Mon, 15 Dec 2025 16:38:49 +0800 Message-Id: <20251215083854.577-7-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251215083854.577-1-yuanjie.yang@oss.qualcomm.com> References: <20251215083854.577-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE1MDA3MiBTYWx0ZWRfX5pxtSliiQtLX /QTG26cFdBMJD2XQD0RBqGdMWLDGK9PoJrYwCqXZtazdrR1Mh/NLN7YIOmRsgz/LsPAfchixtty BjvBTPW7SosMkCzLSKX/khFhckwB51+3dTfImCYqn/J8oWN5g4uVMlO1dawdOG8jl9SDPw2lW4O 170yVqxpje7ba8U5jGAtuoTMt77mR38okeoH0az9IHN1m5ps9QDThUrzGT1x306CTorxD6kAKIJ zURA4GAnmJWzJEZGa7VH/gasNbOS9Gxk+UEeiMKbVsHTZbJJ7bCFqi5urqrH75rCcXSiCH3nqXj jHdP8FJO85ioE2AVqGP8JWexycG6sFKFioMzRQvXpmdaI+XtCX9xRC7/c5pFRK4lyx/BieQ049/ 1biUKbe/shnMXB35hfqz0F52AU73AA== X-Proofpoint-GUID: KU91PDHEZrVjCwuD1xmkIVyMQqsdldMY X-Authority-Analysis: v=2.4 cv=PJQCOPqC c=1 sm=1 tr=0 ts=693fc985 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ab5uJhi7KCXt4xzmVoQA:9 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-ORIG-GUID: KU91PDHEZrVjCwuD1xmkIVyMQqsdldMY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-15_01,2025-12-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 suspectscore=0 adultscore=0 priorityscore=1501 bulkscore=0 spamscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512150072 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add DSI PHY support for the Kaanapali platform, kaanapali introduce addition of DSI2/DSI2_phy compared to SM8650, However, based on the HPG diagram, only DSI0_phy and DSI1_phy works. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov Signed-off-by: Yuanjie Yang --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +++++++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index 4ea681130dba..7937266de1d2 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -577,6 +577,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_4nm_8650_cfgs }, { .compatible =3D "qcom,sm8750-dsi-phy-3nm", .data =3D &dsi_phy_3nm_8750_cfgs }, + { .compatible =3D "qcom,kaanapali-dsi-phy-3nm", + .data =3D &dsi_phy_3nm_kaanapali_cfgs }, #endif {} }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index 3cbf08231492..c01784ca38ed 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -64,6 +64,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_= cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs; =20 struct msm_dsi_dphy_timing { u32 clk_zero; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index c5e1d2016bcc..8cb0db3a9880 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -1504,3 +1504,26 @@ const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs = =3D { .num_dsi_phy =3D 2, .quirks =3D DSI_PHY_7NM_QUIRK_V7_0, }; + +const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_7nm_98000uA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops =3D { + .enable =3D dsi_7nm_phy_enable, + .disable =3D dsi_7nm_phy_disable, + .pll_init =3D dsi_pll_7nm_init, + .save_pll_state =3D dsi_7nm_pll_save_state, + .restore_pll_state =3D dsi_7nm_pll_restore_state, + .set_continuous_clock =3D dsi_7nm_set_continuous_clock, + }, + .min_pll_rate =3D 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate =3D 5000000000UL, +#else + .max_pll_rate =3D ULONG_MAX, +#endif + .io_start =3D { 0x9ac1000, 0x9ac4000 }, + .num_dsi_phy =3D 2, + .quirks =3D DSI_PHY_7NM_QUIRK_V7_0, +}; --=20 2.34.1