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Sun, 14 Dec 2025 22:48:25 -0800 From: Ashish Mhetre To: , , , , , , CC: , , , , , , , , , Ashish Mhetre Subject: [PATCH V7 3/4] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support Date: Mon, 15 Dec 2025 06:48:18 +0000 Message-ID: <20251215064819.3345361-4-amhetre@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251215064819.3345361-1-amhetre@nvidia.com> References: <20251215064819.3345361-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B3:EE_|CH2PR12MB4199:EE_ X-MS-Office365-Filtering-Correlation-Id: 8d314d04-cb85-4187-0522-08de3ba5fc06 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700013|13003099007; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2025 06:48:41.5579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8d314d04-cb85-4187-0522-08de3ba5fc06 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4199 Content-Type: text/plain; charset="utf-8" The Command Queue Virtualization (CMDQV) hardware is part of the SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in virtualizing the command queue for the SMMU. Add a new device tree binding document for nvidia,tegra264-cmdqv. Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv property. This property is a phandle to the CMDQV device node, allowing the SMMU driver to associate with its corresponding CMDQV instance. Restrict this property usage to Nvidia Tegra264 only. Reviewed-by: Rob Herring (Arm) Signed-off-by: Ashish Mhetre Acked-by: Nicolin Chen --- .../bindings/iommu/arm,smmu-v3.yaml | 30 ++++++++++++- .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 42 +++++++++++++++++++ 2 files changed, 70 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra264= -cmdqv.yaml diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Doc= umentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 75fcf4cb52d9..1c03482e4c61 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -20,7 +20,12 @@ properties: $nodename: pattern: "^iommu@[0-9a-f]*" compatible: - const: arm,smmu-v3 + oneOf: + - const: arm,smmu-v3 + - items: + - enum: + - nvidia,tegra264-smmu + - const: arm,smmu-v3 =20 reg: maxItems: 1 @@ -58,6 +63,15 @@ properties: =20 msi-parent: true =20 + nvidia,cmdqv: + description: | + A phandle to its pairing CMDQV extension for an implementation on NV= IDIA + Tegra SoC. + + If this property is absent, CMDQ-Virtualization won't be used and SM= MU + will only use its own CMDQ. + $ref: /schemas/types.yaml#/definitions/phandle + hisilicon,broken-prefetch-cmd: type: boolean description: Avoid sending CMD_PREFETCH_* commands to the SMMU. @@ -69,6 +83,17 @@ properties: register access with page 0 offsets. Set for Cavium ThunderX2 silico= n that doesn't support SMMU page1 register space. =20 +allOf: + - if: + not: + properties: + compatible: + contains: + const: nvidia,tegra264-smmu + then: + properties: + nvidia,cmdqv: false + required: - compatible - reg @@ -82,7 +107,7 @@ examples: #include =20 iommu@2b400000 { - compatible =3D "arm,smmu-v3"; + compatible =3D "nvidia,tegra264-smmu", "arm,smmu-v3"; reg =3D <0x2b400000 0x20000>; interrupts =3D , , @@ -92,4 +117,5 @@ examples: dma-coherent; #iommu-cells =3D <1>; msi-parent =3D <&its 0xff0000>; + nvidia,cmdqv =3D <&cmdqv>; }; diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.= yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml new file mode 100644 index 000000000000..3f5006a59805 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/nvidia,tegra264-cmdqv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 CMDQV + +description: + The CMDQ-Virtualization hardware block is part of the SMMUv3 implementat= ion + on Tegra264 SoCs. It assists in virtualizing the command queue for the S= MMU. + +maintainers: + - Nicolin Chen + +properties: + compatible: + const: nvidia,tegra264-cmdqv + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + cmdqv@5200000 { + compatible =3D "nvidia,tegra264-cmdqv"; + reg =3D <0x5200000 0x830000>; + interrupts =3D ; + }; --=20 2.25.1