From nobody Thu Dec 18 08:16:31 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CDEB31AA85; Mon, 15 Dec 2025 03:50:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765770616; cv=none; b=ibqJmoYAE+OIQj+8dOYTIkJq2lCIh3x1sRrd7AT90N4oe/fOhWYzYWsFn2LVToPn7xUUM3JDaSe9/ffDY60dOYEhIMr364BA5C6HttndC8mKnu2oLe+bTk0EVCyZLj4A6Q25xmGTvuyFbPmep7i8NKQP9YS8oMqjmxu2hfWOIaY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765770616; c=relaxed/simple; bh=n+XcFsq0fXIFI09blNJRe186pzfGjTuYHtrjZz1CHhU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mIxeST4gx1MNXA5Xb2r61xmfyuYfGEnt+n7L5AobRhpbESniwonRUguIb3qW4ILZipZrPt0KY9GEk0qRhpLb3WY1zcdu2z0KVsUgBdaeKZKylyuhsltTaj9AwLfKDHkMr2SpG1pDHT4x1b+MpE6bWcprDdq6NfFldG4iczsgvlA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=tmCbsDKT; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="tmCbsDKT" X-UUID: 1d117248d96911f0b2bf0b349165d6e0-20251215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=uqdpu67IUC+r8CLx+XFjqa8UJ5wYTydLu0WRgTZ8wmE=; b=tmCbsDKTaIXxjmcroctPyplTD/X2OiVTm3zz4bpXAZ0/MPH8m4ON+xEWiKVg/5hyTCKQxgV0vUNoQq287kryj5yLppOUN4n7NuQpapsEj1UO4SJec4tKWQpp/kZ1TwO94ECL9hdM8gqAo4b2h6LB4x8GDDxO0r67UW4pBbs3xhE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:da11c18f-185d-4ab3-99e3-c185e23f69da,IP:0,UR L:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:-5 X-CID-META: VersionHash:a9d874c,CLOUDID:3dd0c402-1fa9-44eb-b231-4afc61466396,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 1d117248d96911f0b2bf0b349165d6e0-20251215 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1062340307; Mon, 15 Dec 2025 11:49:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Mon, 15 Dec 2025 11:49:51 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Mon, 15 Dec 2025 11:49:51 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran CC: Qiqi Wang , , , , , , , , , , , , Subject: [PATCH v4 04/21] clk: mediatek: Add MT8189 apmixedsys clock support Date: Mon, 15 Dec 2025 11:49:13 +0800 Message-ID: <20251215034944.2973003-5-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251215034944.2973003-1-irving-ch.lin@mediatek.com> References: <20251215034944.2973003-1-irving-ch.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Irving-CH Lin Add support for the MT8189 apmixedsys clock controller, which provides PLLs generated from SoC 26m. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 13 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-apmixedsys.c | 192 +++++++++++++++++++ 3 files changed, 206 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-apmixedsys.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 0e8dd82aa84e..2c898fd8a34c 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -815,6 +815,19 @@ config COMMON_CLK_MT8188_WPESYS help This driver supports MediaTek MT8188 Warp Engine clocks. =20 +config COMMON_CLK_MT8189 + bool "Clock driver for MediaTek MT8189" + depends on ARM64 || COMPILE_TEST + select COMMON_CLK_MEDIATEK + select COMMON_CLK_MEDIATEK_FHCTL + default ARCH_MEDIATEK + help + Enable this option to support the clock management for MediaTek MT8189 = SoC. This + includes handling of all primary clock functions and features specific = to the MT8189 + platform. Enabling this driver ensures that the system's clock function= ality aligns + with the MediaTek MT8189 hardware capabilities, providing efficient man= agement of + clock speeds and power consumption. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index d8736a060dbd..66577ccb9b93 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -123,6 +123,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) +=3D clk-mt8188-= vdo0.o clk-mt8188-vdo1.o obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) +=3D clk-mt8188-venc.o obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) +=3D clk-mt8188-vpp0.o clk-mt8188-v= pp1.o obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) +=3D clk-mt8188-wpe.o +obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixedsys.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8189-apmixedsys.c new file mode 100644 index 000000000000..1299765e4f14 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-apmixedsys.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-fhctl.h" +#include "clk-mtk.h" +#include "clk-pll.h" + +#include + +#define MT8189_PLL_FMAX (3800UL * MHZ) +#define MT8189_PLL_FMIN (1500UL * MHZ) +#define MT8189_PLLEN_OFS 0x70 +#define MT8189_INTEGER_BITS 8 + +#define PLL_SETCLR(_id, _name, _reg, _en_setclr_bit, \ + _rstb_setclr_bit, _flags, _pd_reg, \ + _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, \ + _pcwbits) { \ + .id =3D _id, \ + .name =3D _name, \ + .en_reg =3D MT8189_PLLEN_OFS, \ + .reg =3D _reg, \ + .pll_en_bit =3D _en_setclr_bit, \ + .rst_bar_mask =3D BIT(_rstb_setclr_bit), \ + .flags =3D _flags, \ + .fmax =3D MT8189_PLL_FMAX, \ + .fmin =3D MT8189_PLL_FMIN, \ + .pd_reg =3D _pd_reg, \ + .pd_shift =3D _pd_shift, \ + .tuner_reg =3D _tuner_reg, \ + .tuner_en_reg =3D _tuner_en_reg, \ + .tuner_en_bit =3D _tuner_en_bit, \ + .pcw_reg =3D _pcw_reg, \ + .pcw_shift =3D _pcw_shift, \ + .pcwbits =3D _pcwbits, \ + .pcwibits =3D MT8189_INTEGER_BITS, \ + } + +static const struct mtk_pll_data apmixed_plls[] =3D { + PLL_SETCLR(CLK_APMIXED_ARMPLL_LL, "armpll-ll", 0x204, 18, + 0, PLL_AO, 0x208, 24, 0, 0, 0, 0x208, 0, 22), + PLL_SETCLR(CLK_APMIXED_ARMPLL_BL, "armpll-bl", 0x214, 17, + 0, PLL_AO, 0x218, 24, 0, 0, 0, 0x218, 0, 22), + PLL_SETCLR(CLK_APMIXED_CCIPLL, "ccipll", 0x224, 16, + 0, PLL_AO, 0x228, 24, 0, 0, 0, 0x228, 0, 22), + PLL_SETCLR(CLK_APMIXED_MAINPLL, "mainpll", 0x304, 15, + 23, HAVE_RST_BAR | PLL_AO, + 0x308, 24, 0, 0, 0, 0x308, 0, 22), + PLL_SETCLR(CLK_APMIXED_UNIVPLL, "univpll", 0x314, 14, + 23, HAVE_RST_BAR, 0x318, 24, 0, 0, 0, 0x318, 0, 22), + PLL_SETCLR(CLK_APMIXED_MMPLL, "mmpll", 0x324, 13, + 23, HAVE_RST_BAR, 0x328, 24, 0, 0, 0, 0x328, 0, 22), + PLL_SETCLR(CLK_APMIXED_MFGPLL, "mfgpll", 0x504, 7, + 0, 0, 0x508, 24, 0, 0, 0, 0x508, 0, 22), + PLL_SETCLR(CLK_APMIXED_APLL1, "apll1", 0x404, 11, + 0, 0, 0x408, 24, 0x040, 0x00c, 0, 0x40c, 0, 32), + PLL_SETCLR(CLK_APMIXED_APLL2, "apll2", 0x418, 10, + 0, 0, 0x41c, 24, 0x044, 0x00c, 1, 0x420, 0, 32), + PLL_SETCLR(CLK_APMIXED_EMIPLL, "emipll", 0x334, 12, + 0, PLL_AO, 0x338, 24, 0, 0, 0, 0x338, 0, 22), + PLL_SETCLR(CLK_APMIXED_APUPLL2, "apupll2", 0x614, 2, + 0, 0, 0x618, 24, 0, 0, 0, 0x618, 0, 22), + PLL_SETCLR(CLK_APMIXED_APUPLL, "apupll", 0x604, 3, + 0, 0, 0x608, 24, 0, 0, 0, 0x608, 0, 22), + PLL_SETCLR(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x42c, 9, + 0, 0, 0x430, 24, 0, 0, 0, 0x430, 0, 22), + PLL_SETCLR(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x43c, 8, + 0, 0, 0x440, 24, 0, 0, 0, 0x440, 0, 22), + PLL_SETCLR(CLK_APMIXED_ETHPLL, "ethpll", 0x514, 6, + 0, 0, 0x518, 24, 0, 0, 0, 0x518, 0, 22), + PLL_SETCLR(CLK_APMIXED_MSDCPLL, "msdcpll", 0x524, 5, + 0, 0, 0x528, 24, 0, 0, 0, 0x528, 0, 22), + PLL_SETCLR(CLK_APMIXED_UFSPLL, "ufspll", 0x534, 4, + 0, 0, 0x538, 24, 0, 0, 0, 0x538, 0, 22), +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data =3D { \ + .pll_id =3D _pllid, \ + .fh_id =3D _fhid, \ + .fh_ver =3D FHCTL_PLLFH_V2, \ + .fhx_offset =3D _offset, \ + .dds_mask =3D GENMASK(21, 0), \ + .slope0_value =3D 0x6003c97, \ + .slope1_value =3D 0x6003c97, \ + .sfstrx_en =3D BIT(2), \ + .frddsx_en =3D BIT(1), \ + .fhctlx_en =3D BIT(0), \ + .tgl_org =3D BIT(31), \ + .dvfs_tri =3D BIT(31), \ + .pcwchg =3D BIT(31), \ + .dt_val =3D 0x0, \ + .df_val =3D 0x9, \ + .updnlmt_shft =3D 16, \ + .msk_frddsx_dys =3D GENMASK(23, 20), \ + .msk_frddsx_dts =3D GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] =3D { + FH(CLK_APMIXED_ARMPLL_LL, 0, 0x003C), + FH(CLK_APMIXED_ARMPLL_BL, 1, 0x0050), + FH(CLK_APMIXED_CCIPLL, 2, 0x0064), + FH(CLK_APMIXED_MAINPLL, 3, 0x0078), + FH(CLK_APMIXED_MMPLL, 4, 0x008C), + FH(CLK_APMIXED_MFGPLL, 5, 0x00A0), + FH(CLK_APMIXED_EMIPLL, 6, 0x00B4), + FH(CLK_APMIXED_TVDPLL1, 7, 0x00C8), + FH(CLK_APMIXED_TVDPLL2, 8, 0x00DC), + FH(CLK_APMIXED_MSDCPLL, 9, 0x00F0), + FH(CLK_APMIXED_UFSPLL, 10, 0x0104), + FH(CLK_APMIXED_APUPLL, 11, 0x0118), + FH(CLK_APMIXED_APUPLL2, 12, 0x012c), +}; + +static const struct of_device_id of_match_clk_mt8189_apmixed[] =3D { + { .compatible =3D "mediatek,mt8189-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_apmixed); + +static int clk_mt8189_apmixed_probe(struct platform_device *pdev) +{ + int r; + struct clk_hw_onecell_data *clk_data; + struct device_node *node =3D pdev->dev.of_node; + const u8 *fhctl_node =3D "mediatek,mt8189-fhctl"; + + clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls)); + if (!clk_data) + return -ENOMEM; + + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + + r =3D mtk_clk_register_pllfhs(node, apmixed_plls, ARRAY_SIZE(apmixed_plls= ), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); + if (r) + goto free_apmixed_data; + + r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + goto unregister_plls; + + platform_set_drvdata(pdev, clk_data); + + return 0; + +unregister_plls: + mtk_clk_unregister_plls(apmixed_plls, ARRAY_SIZE(apmixed_plls), + clk_data); +free_apmixed_data: + mtk_free_clk_data(clk_data); + return r; +} + +static void clk_mt8189_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_pllfhs(apmixed_plls, ARRAY_SIZE(apmixed_plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); + mtk_free_clk_data(clk_data); +} + +static struct platform_driver clk_mt8189_apmixed_drv =3D { + .probe =3D clk_mt8189_apmixed_probe, + .remove =3D clk_mt8189_apmixed_remove, + .driver =3D { + .name =3D "clk-mt8189-apmixed", + .of_match_table =3D of_match_clk_mt8189_apmixed, + }, +}; + +module_platform_driver(clk_mt8189_apmixed_drv); +MODULE_DESCRIPTION("MediaTek MT8189 apmixed clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2