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Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 10 ++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-scp.c | 73 +++++++++++++++++++++++++++ 3 files changed, 84 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-scp.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 8b1f358457d8..2cc1a28436f1 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -929,6 +929,16 @@ config COMMON_CLK_MT8189_MMSYS ensure that these components receive the correct clock frequencies for proper operation. =20 +config COMMON_CLK_MT8189_SCP + tristate "Clock driver for MediaTek MT8189 scp" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock framework for the System Control + Processor (SCP) in the MediaTek MT8189 SoC. This includes clock + management for SCP-related features, ensuring proper clock + distribution and gating for power efficiency and functionality. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 21a9e6264b84..819c67395e1b 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -134,6 +134,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_IMG) +=3D clk-mt8189-img= .o obj-$(CONFIG_COMMON_CLK_MT8189_MDPSYS) +=3D clk-mt8189-mdpsys.o obj-$(CONFIG_COMMON_CLK_MT8189_MFG) +=3D clk-mt8189-mfg.o obj-$(CONFIG_COMMON_CLK_MT8189_MMSYS) +=3D clk-mt8189-dispsys.o +obj-$(CONFIG_COMMON_CLK_MT8189_SCP) +=3D clk-mt8189-scp.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-scp.c b/drivers/clk/mediatek/c= lk-mt8189-scp.c new file mode 100644 index 000000000000..efa00de90215 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-scp.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs scp_cg_regs =3D { + .set_ofs =3D 0x4, + .clr_ofs =3D 0x8, + .sta_ofs =3D 0x4, +}; + +#define GATE_SCP(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &scp_cg_regs, _shift, &mtk_clk_gate_ops_set= clr_inv) + +static const struct mtk_gate scp_clks[] =3D { + GATE_SCP(CLK_SCP_SET_SPI0, "scp_set_spi0", "clk26m", 0), + GATE_SCP(CLK_SCP_SET_SPI1, "scp_set_spi1", "clk26m", 1), +}; + +static const struct mtk_clk_desc scp_mcd =3D { + .clks =3D scp_clks, + .num_clks =3D ARRAY_SIZE(scp_clks), +}; + +static const struct mtk_gate_regs scp_iic_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_SCP_IIC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &scp_iic_cg_regs, _shift, &mtk_clk_gate_ops= _setclr_inv) + +static const struct mtk_gate scp_iic_clks[] =3D { + GATE_SCP_IIC(CLK_SCP_IIC_I2C0_W1S, "scp_iic_i2c0_w1s", "vlp_scp_iic_sel",= 0), + GATE_SCP_IIC(CLK_SCP_IIC_I2C1_W1S, "scp_iic_i2c1_w1s", "vlp_scp_iic_sel",= 1), +}; + +static const struct mtk_clk_desc scp_iic_mcd =3D { + .clks =3D scp_iic_clks, + .num_clks =3D ARRAY_SIZE(scp_iic_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_scp[] =3D { + { .compatible =3D "mediatek,mt8189-scp-clk", .data =3D &scp_mcd }, + { .compatible =3D "mediatek,mt8189-scp-i2c-clk", .data =3D &scp_iic_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_scp); + +static struct platform_driver clk_mt8189_scp_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-scp", + .of_match_table =3D of_match_clk_mt8189_scp, + }, +}; + +module_platform_driver(clk_mt8189_scp_drv); +MODULE_DESCRIPTION("MediaTek MT8189 scp clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2