From nobody Thu Dec 18 08:12:28 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BFDF316905; Mon, 15 Dec 2025 03:50:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765770611; cv=none; b=p1ZwvxM2UWoMI6HnbWW4dXkVab3fMzp8O2NPDzfxOloEQYNi3EvNPXSfhJO1eF6JB2fH6SZltoNTZci96RYu6Ow6iPayoe889ObbIySufGmNEWhcKCjM/LB3S2cH+czRtgZVC5DFjYoyFvsQ6Pen1Ojc0Thp64Y1LIv4TzbDl2U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765770611; c=relaxed/simple; bh=D7RL3Um63Zw/7tKAOk++fVQaBhpsk8wHta0wTq4lj6k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ApUj5S6XVTY0ECgS4KPWPTdTO7DXu+z6uCLD+LbtKLbDdImJoxegippOhZK47vNBMaBHANGFrlkYhZ9SUoXt5kgOXmTjx5XJbkKw4aZUsNLUdipAsnq0F1SE4uZmuAevdgT2jX1Ho9GbV1oV8L11AL07Z5HXWP/7loWpNBkbLBw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=i7tPDlBW; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="i7tPDlBW" X-UUID: 1dc7488ed96911f0b33aeb1e7f16c2b6-20251215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=QxXOMKoHwGVrbpel5rPQL1p+ya5cMq6oSyfUu18oLBQ=; b=i7tPDlBW9nI07cIJHomxH51509kcUkma/Y7BOn7jk/rtutHt6LK3HDKVJNi/JkPFPKwnA3zFhK1kZzBy8JbkOxJMP6FAqEjs+HPgYtrsL0/J9FA79bSm+wKvw8LY8HZ/qWNvSO9GjYer2h5rSS7S0i1DYj1Jr1asKX5Rm49PXeg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:8f89a665-be49-4425-9de8-3f3efd33c248,IP:0,UR L:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-25 X-CID-META: VersionHash:a9d874c,CLOUDID:a86970c6-8a73-4871-aac2-7b886d064f36,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 1dc7488ed96911f0b33aeb1e7f16c2b6-20251215 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 303324362; Mon, 15 Dec 2025 11:49:54 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Mon, 15 Dec 2025 11:49:53 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Mon, 15 Dec 2025 11:49:53 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran CC: Qiqi Wang , , , , , , , , , , , , Subject: [PATCH v4 16/21] clk: mediatek: Add MT8189 dispsys clock support Date: Mon, 15 Dec 2025 11:49:25 +0800 Message-ID: <20251215034944.2973003-17-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251215034944.2973003-1-irving-ch.lin@mediatek.com> References: <20251215034944.2973003-1-irving-ch.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Irving-CH Lin Add support for the MT8189 dispsys clock controller, which provides clock gate control for display system. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 12 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-dispsys.c | 172 ++++++++++++++++++++++ 3 files changed, 185 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-dispsys.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 316d010b503a..8b1f358457d8 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -917,6 +917,18 @@ config COMMON_CLK_MT8189_MFG the MT8189 chipset. Enabling this will allow the manufacturing mode of the chipset to function correctly with the appropriate clock settings. =20 +config COMMON_CLK_MT8189_MMSYS + tristate "Clock driver for MediaTek MT8189 mmsys" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock framework for MediaTek MT8189 + multimedia systems (mmsys). This driver is responsible for managing + the clocks for various multimedia components within the SoC, such as + video, audio, and image processing units. Enabling this option will + ensure that these components receive the correct clock frequencies + for proper operation. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 07f11760cf68..21a9e6264b84 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -133,6 +133,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_IIC) +=3D clk-mt8189-iic= .o obj-$(CONFIG_COMMON_CLK_MT8189_IMG) +=3D clk-mt8189-img.o obj-$(CONFIG_COMMON_CLK_MT8189_MDPSYS) +=3D clk-mt8189-mdpsys.o obj-$(CONFIG_COMMON_CLK_MT8189_MFG) +=3D clk-mt8189-mfg.o +obj-$(CONFIG_COMMON_CLK_MT8189_MMSYS) +=3D clk-mt8189-dispsys.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-dispsys.c b/drivers/clk/mediat= ek/clk-mt8189-dispsys.c new file mode 100644 index 000000000000..4c101cf66f91 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-dispsys.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs mm0_cg_regs =3D { + .set_ofs =3D 0x04, + .clr_ofs =3D 0x08, + .sta_ofs =3D 0x00, +}; + +static const struct mtk_gate_regs mm1_cg_regs =3D { + .set_ofs =3D 0x14, + .clr_ofs =3D 0x18, + .sta_ofs =3D 0x10, +}; + +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) + +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) + +static const struct mtk_gate mm_clks[] =3D { + /* MM0 */ + GATE_MM0(CLK_MM_DISP_OVL0_4L, "mm_disp_ovl0_4l", "disp0_sel", 0), + GATE_MM0(CLK_MM_DISP_OVL1_4L, "mm_disp_ovl1_4l", "disp0_sel", 1), + GATE_MM0(CLK_MM_VPP_RSZ0, "mm_vpp_rsz0", "disp0_sel", 2), + GATE_MM0(CLK_MM_VPP_RSZ1, "mm_vpp_rsz1", "disp0_sel", 3), + GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp0_sel", 4), + GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "disp0_sel", 5), + GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp0_sel", 6), + GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "disp0_sel", 7), + GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp0_sel", 8), + GATE_MM0(CLK_MM_DISP_CCORR1, "mm_disp_ccorr1", "disp0_sel", 9), + GATE_MM0(CLK_MM_DISP_CCORR2, "mm_disp_ccorr2", "disp0_sel", 10), + GATE_MM0(CLK_MM_DISP_CCORR3, "mm_disp_ccorr3", "disp0_sel", 11), + GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp0_sel", 12), + GATE_MM0(CLK_MM_DISP_AAL1, "mm_disp_aal1", "disp0_sel", 13), + GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp0_sel", 14), + GATE_MM0(CLK_MM_DISP_GAMMA1, "mm_disp_gamma1", "disp0_sel", 15), + GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp0_sel", 16), + GATE_MM0(CLK_MM_DISP_DITHER1, "mm_disp_dither1", "disp0_sel", 17), + GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "disp0_sel", 18), + GATE_MM0(CLK_MM_VPP_MERGE0, "mm_vpp_merge0", "disp0_sel", 19), + GATE_MM0(CLK_MMSYS_0_DISP_DVO, "mmsys_0_disp_dvo", "disp0_sel", 20), + GATE_MM0(CLK_MMSYS_0_DISP_DSI0, "mmsys_0_CLK0", "disp0_sel", 21), + GATE_MM0(CLK_MM_DP_INTF0, "mm_dp_intf0", "disp0_sel", 22), + GATE_MM0(CLK_MM_DPI0, "mm_dpi0", "disp0_sel", 23), + GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp0_sel", 24), + GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "disp0_sel", 25), + GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp0_sel", 26), + GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "disp0_sel", 27), + GATE_MM0(CLK_MM_SMI_LARB, "mm_smi_larb", "disp0_sel", 28), + GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp0_sel", 29), + GATE_MM0(CLK_MM_DIPSYS_CONFIG, "mm_dipsys_config", "disp0_sel", 30), + GATE_MM0(CLK_MM_DUMMY, "mm_dummy", "disp0_sel", 31), + /* MM1 */ + GATE_MM1(CLK_MMSYS_1_DISP_DSI0, "mmsys_1_CLK0", "dsi_occ_sel", 0), + GATE_MM1(CLK_MMSYS_1_LVDS_ENCODER, "mmsys_1_lvds_encoder", "pll_dpix_sel"= , 1), + GATE_MM1(CLK_MMSYS_1_DPI0, "mmsys_1_dpi0", "pll_dpix_sel", 2), + GATE_MM1(CLK_MMSYS_1_DISP_DVO, "mmsys_1_disp_dvo", "edp_sel", 3), + GATE_MM1(CLK_MM_DP_INTF, "mm_dp_intf", "dp_sel", 4), + GATE_MM1(CLK_MMSYS_1_LVDS_ENCODER_CTS, "mmsys_1_lvds_encoder_cts", "vdstx= _dg_cts_sel", 5), + GATE_MM1(CLK_MMSYS_1_DISP_DVO_AVT, "mmsys_1_disp_dvo_avt", "edp_favt_sel"= , 6), +}; + +static const struct mtk_clk_desc mm_mcd =3D { + .clks =3D mm_clks, + .num_clks =3D ARRAY_SIZE(mm_clks), +}; + +static const struct mtk_gate_regs gce_d_cg_regs =3D { + .set_ofs =3D 0x0, + .clr_ofs =3D 0x0, + .sta_ofs =3D 0x0, +}; + +#define GATE_GCE_D(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &gce_d_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr) + +static const struct mtk_gate gce_d_clks[] =3D { + GATE_GCE_D(CLK_GCE_D_TOP, "gce_d_top", "mminfra_gce_d", 16), +}; + +static const struct mtk_clk_desc gce_d_mcd =3D { + .clks =3D gce_d_clks, + .num_clks =3D ARRAY_SIZE(gce_d_clks), +}; + +static const struct mtk_gate_regs gce_m_cg_regs =3D { + .set_ofs =3D 0x0, + .clr_ofs =3D 0x0, + .sta_ofs =3D 0x0, +}; + +#define GATE_GCE_M(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &gce_m_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr) + +static const struct mtk_gate gce_m_clks[] =3D { + GATE_GCE_M(CLK_GCE_M_TOP, "gce_m_top", "mminfra_gce_m", 16), +}; + +static const struct mtk_clk_desc gce_m_mcd =3D { + .clks =3D gce_m_clks, + .num_clks =3D ARRAY_SIZE(gce_m_clks), +}; + +static const struct mtk_gate_regs mminfra_config0_cg_regs =3D { + .set_ofs =3D 0x104, + .clr_ofs =3D 0x108, + .sta_ofs =3D 0x100, +}; + +static const struct mtk_gate_regs mminfra_config1_cg_regs =3D { + .set_ofs =3D 0x114, + .clr_ofs =3D 0x118, + .sta_ofs =3D 0x110, +}; + +#define GATE_MMINFRA_CONFIG0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mminfra_config0_cg_regs, _shift, &mtk_clk_= gate_ops_setclr) + +#define GATE_MMINFRA_CONFIG1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mminfra_config1_cg_regs, _shift, &mtk_clk_= gate_ops_setclr) + +static const struct mtk_gate mminfra_config_clks[] =3D { + /* MMINFRA_CONFIG0 */ + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_D, "mminfra_gce_d", "mminfra_sel", 0= ), + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_M, "mminfra_gce_m", "mminfra_sel", 1= ), + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_SMI, "mminfra_smi", "mminfra_sel", 2), + /* MMINFRA_CONFIG1 */ + GATE_MMINFRA_CONFIG1(CLK_MMINFRA_GCE_26M, "mminfra_gce_26m", "mminfra_sel= ", 17), +}; + +static const struct mtk_clk_desc mminfra_config_mcd =3D { + .clks =3D mminfra_config_clks, + .num_clks =3D ARRAY_SIZE(mminfra_config_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_dispsys[] =3D { + { .compatible =3D "mediatek,mt8189-dispsys", .data =3D &mm_mcd }, + { .compatible =3D "mediatek,mt8189-gce-d", .data =3D &gce_d_mcd }, + { .compatible =3D "mediatek,mt8189-gce-m", .data =3D &gce_m_mcd }, + { .compatible =3D "mediatek,mt8189-mm-infra", .data =3D &mminfra_config_m= cd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_dispsys); + +static struct platform_driver clk_mt8189_dispsys_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-dispsys", + .of_match_table =3D of_match_clk_mt8189_dispsys, + }, +}; + +module_platform_driver(clk_mt8189_dispsys_drv); +MODULE_DESCRIPTION("MediaTek MT8189 display clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2