From nobody Thu Dec 18 08:12:23 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CFB0317706; Mon, 15 Dec 2025 03:50:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765770612; cv=none; b=UH6OEbsfKlsQGl9zB+0kNB7e7KNh58BpCIWQN0KQ3p4cQ1hOOAaABizyAGdUtkG1IofAye35E1AkKfhcbMnLNzTR8Zft2rDTkblooyCjFc4j74QrXk4s9okYRhLWMdWwEwxvqz5dZJq+0u1sGVMselfwwQw07db68/GmbexrgqA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765770612; c=relaxed/simple; bh=j4PeH3VvdDceENg13Ql0e5mBtrLJ1NdiEmH6js9boas=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=llIiqj5dFbxAUhz7v+YEXHBfOxzBiM1+tiBbgn6jibwIbMGLT/1lFX/Wm/N3m7+cJqWDDo0qWWtJ8ppG4VaBwmksogVta06wsvS67JldEdCXEsWy5ZVu1NWM2eCVMXaEpU2qvMnNAsKeS5id7fYJk0JVedZIblaAu2bzuq/jqD8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=SHVNSIgH; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="SHVNSIgH" X-UUID: 1d68151cd96911f0b2bf0b349165d6e0-20251215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=LaV8DwZmBEHEtEB75FWL49lVDqkVLABEDZwia7MXrhw=; b=SHVNSIgHk4l+zrKpD6Q9+CmWXR/jvrhiZ4CqaMJttO9tzOYOnD9uugly9T5Std2mqbxKE86t56N7WvewnSl/CKve6nF5CHvQx4+BG9OJBACalv0YK4WZaZkkHoNAyQGeEREH7Quo0fbw2RFPRlItgtJNWrmvbjVni5/wZCm0UOY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:8e165a07-236a-424e-957c-66aee5054d25,IP:0,UR L:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-25 X-CID-META: VersionHash:a9d874c,CLOUDID:e8f430aa-6421-45b1-b8b8-e73e3dc9a90f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 1d68151cd96911f0b2bf0b349165d6e0-20251215 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1514044215; Mon, 15 Dec 2025 11:49:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Mon, 15 Dec 2025 11:49:53 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Mon, 15 Dec 2025 11:49:53 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran CC: Qiqi Wang , , , , , , , , , , , , Subject: [PATCH v4 13/21] clk: mediatek: Add MT8189 img clock support Date: Mon, 15 Dec 2025 11:49:22 +0800 Message-ID: <20251215034944.2973003-14-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251215034944.2973003-1-irving-ch.lin@mediatek.com> References: <20251215034944.2973003-1-irving-ch.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Irving-CH Lin Add support for the MT8189 img clock controller, which provides clock gate control for image processing module. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 11 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-img.c | 107 ++++++++++++++++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-img.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 71603fba2ea8..c0fe1aa49993 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -883,6 +883,17 @@ config COMMON_CLK_MT8189_IIC the MT8189 chipset, improving the overall performance and power efficiency of the device. =20 +config COMMON_CLK_MT8189_IMG + tristate "Clock driver for MediaTek MT8189 img" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock framework for MediaTek MT8189 SoC's + image processing units. This includes clocks necessary for the operation + of image-related hardware blocks such as ISP, VENC, and VDEC. If you + are building a kernel for a device that uses the MT8189 SoC and requires + image processing capabilities, say Y or M to include this driver. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 0eed1edf7c63..a1eaf123f2f0 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -130,6 +130,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_CAM) +=3D clk-mt8189-cam= .o obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) +=3D clk-mt8189-dbgao.o obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) +=3D clk-mt8189-dvfsrc.o obj-$(CONFIG_COMMON_CLK_MT8189_IIC) +=3D clk-mt8189-iic.o +obj-$(CONFIG_COMMON_CLK_MT8189_IMG) +=3D clk-mt8189-img.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-img.c b/drivers/clk/mediatek/c= lk-mt8189-img.c new file mode 100644 index 000000000000..d79f48dbe3e1 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-img.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs imgsys1_cg_regs =3D { + .set_ofs =3D 0x4, + .clr_ofs =3D 0x8, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMGSYS1(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &imgsys1_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED) + +static const struct mtk_gate imgsys1_clks[] =3D { + GATE_IMGSYS1(CLK_IMGSYS1_LARB9, "imgsys1_larb9", "img1_sel", 0), + GATE_IMGSYS1(CLK_IMGSYS1_LARB11, "imgsys1_larb11", "img1_sel", 1), + GATE_IMGSYS1(CLK_IMGSYS1_DIP, "imgsys1_dip", "img1_sel", 2), + GATE_IMGSYS1(CLK_IMGSYS1_GALS, "imgsys1_gals", "img1_sel", 12), +}; + +static const struct mtk_clk_desc imgsys1_mcd =3D { + .clks =3D imgsys1_clks, + .num_clks =3D ARRAY_SIZE(imgsys1_clks), +}; + +static const struct mtk_gate_regs imgsys2_cg_regs =3D { + .set_ofs =3D 0x4, + .clr_ofs =3D 0x8, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMGSYS2(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &imgsys2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED) + +static const struct mtk_gate imgsys2_clks[] =3D { + GATE_IMGSYS2(CLK_IMGSYS2_LARB9, "imgsys2_larb9", "img1_sel", 0), + GATE_IMGSYS2(CLK_IMGSYS2_LARB11, "imgsys2_larb11", "img1_sel", 1), + GATE_IMGSYS2(CLK_IMGSYS2_MFB, "imgsys2_mfb", "img1_sel", 6), + GATE_IMGSYS2(CLK_IMGSYS2_WPE, "imgsys2_wpe", "img1_sel", 7), + GATE_IMGSYS2(CLK_IMGSYS2_MSS, "imgsys2_mss", "img1_sel", 8), + GATE_IMGSYS2(CLK_IMGSYS2_GALS, "imgsys2_gals", "img1_sel", 12), +}; + +static const struct mtk_clk_desc imgsys2_mcd =3D { + .clks =3D imgsys2_clks, + .num_clks =3D ARRAY_SIZE(imgsys2_clks), +}; + +static const struct mtk_gate_regs ipe_cg_regs =3D { + .set_ofs =3D 0x4, + .clr_ofs =3D 0x8, + .sta_ofs =3D 0x0, +}; + +#define GATE_IPE(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &ipe_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED) + +static const struct mtk_gate ipe_clks[] =3D { + GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "ipe_sel", 0), + GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "ipe_sel", 1), + GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2), + GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3), + GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4), + GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5), + GATE_IPE(CLK_IPESYS_GALS, "ipesys_gals", "ipe_sel", 8), +}; + +static const struct mtk_clk_desc ipe_mcd =3D { + .clks =3D ipe_clks, + .num_clks =3D ARRAY_SIZE(ipe_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_img[] =3D { + { .compatible =3D "mediatek,mt8189-imgsys1", .data =3D &imgsys1_mcd }, + { .compatible =3D "mediatek,mt8189-imgsys2", .data =3D &imgsys2_mcd }, + { .compatible =3D "mediatek,mt8189-ipesys", .data =3D &ipe_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_img); + +static struct platform_driver clk_mt8189_img_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-img", + .of_match_table =3D of_match_clk_mt8189_img, + }, +}; + +module_platform_driver(clk_mt8189_img_drv); +MODULE_DESCRIPTION("MediaTek MT8189 img clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2