From nobody Thu Dec 18 08:16:31 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D046317710; Mon, 15 Dec 2025 03:50:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765770612; cv=none; b=QFGACz7ZVVrGxs6oYJzfU7GkR4mqLoBnNN5g4XtOjREDiTD0f+eYqSWqnsrzlia2s/UCEPgrPu9akycgu9YCJB8uIjjYfzWRrdeU3tBC2gSFQZxJW74K57ZOYzF1VcO0My3GA6Da0NzxZ9YZq2IJjOFIbYXeOsYaoA87NZ2E1FY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765770612; c=relaxed/simple; bh=yP2G0xnCndXvKgA9ufCBU51ZKHHPhhM8DXezyhV0zhQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=a6aAnvLOfJ4DZWCmeU85IhFTwAR4ul3rN0IClm1xtkzyVJ3R+D68Dk8uErgHE8tI5h2mMGuM81I4sQVxsqyqooFFvecm0zcD8J2+sZVJUhFhxO9bttElIsYDIz89uyWBCQU3pVDLh4Y2/7S8fnFIvpQFefDpN88A1FdvW1ixuE8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=LuGwljyi; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="LuGwljyi" X-UUID: 1dbcb248d96911f0b33aeb1e7f16c2b6-20251215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=P9/XVFCCgvctonRjRNcM4hdI/6vw9v9rD0qwnUdztW4=; b=LuGwljyiMJtil4OhUQg7R8H+UwU/gd9io5Mienh1+KYrpVBCZSwxL0yoRiEP6RRf4H/zMy7KV7IZGMvIuZwxjGrVNzHEcibjOktV9gNhVvw3YnfLjwxviZhj6RQzubrrbM+8LmEv1t/it9RZalwa80nACGCHUCuRoznx0qbw60U=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:14462ce5-3af7-422d-885c-b5fd0c45a863,IP:0,UR L:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-25 X-CID-META: VersionHash:a9d874c,CLOUDID:ba078528-e3a2-4f78-a442-8c73c4eb9e9d,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 1dbcb248d96911f0b33aeb1e7f16c2b6-20251215 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1480380138; Mon, 15 Dec 2025 11:49:54 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Mon, 15 Dec 2025 11:49:52 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Mon, 15 Dec 2025 11:49:52 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Richard Cochran CC: Qiqi Wang , , , , , , , , , , , , Subject: [PATCH v4 12/21] clk: mediatek: Add MT8189 i2c clock support Date: Mon, 15 Dec 2025 11:49:21 +0800 Message-ID: <20251215034944.2973003-13-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251215034944.2973003-1-irving-ch.lin@mediatek.com> References: <20251215034944.2973003-1-irving-ch.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Irving-CH Lin Add support for the MT8189 i2c clock controller, which provides clock gate control for i2c. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 13 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-iic.c | 118 ++++++++++++++++++++++++++ 3 files changed, 132 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-iic.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 76c9391bee69..71603fba2ea8 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -870,6 +870,19 @@ config COMMON_CLK_MT8189_DVFSRC vcore dvfs clocks. If you want to control its clocks, say Y or M to include this driver in your kernel build. =20 +config COMMON_CLK_MT8189_IIC + tristate "Clock driver for MediaTek MT8189 iic" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this option to support the clock framework for MediaTek MT8189 + integrated circuits (iic). This driver is responsible for managing + clock sources, dividers, and gates specifically designed for MT8189 + SoCs. Enabling this driver ensures that the system can correctly + manage clock frequencies and power for various components within + the MT8189 chipset, improving the overall performance and power + efficiency of the device. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 3a8dad865c97..0eed1edf7c63 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -129,6 +129,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_BUS) +=3D clk-mt8189-bus= .o obj-$(CONFIG_COMMON_CLK_MT8189_CAM) +=3D clk-mt8189-cam.o obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) +=3D clk-mt8189-dbgao.o obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) +=3D clk-mt8189-dvfsrc.o +obj-$(CONFIG_COMMON_CLK_MT8189_IIC) +=3D clk-mt8189-iic.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-iic.c b/drivers/clk/mediatek/c= lk-mt8189-iic.c new file mode 100644 index 000000000000..5feeb6cd83cf --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-iic.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs impe_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMPE(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &impe_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE) + +static const struct mtk_gate impe_clks[] =3D { + GATE_IMPE(CLK_IMPE_I2C0, "impe_i2c0", "i2c_sel", 0), + GATE_IMPE(CLK_IMPE_I2C1, "impe_i2c1", "i2c_sel", 1), +}; + +static const struct mtk_clk_desc impe_mcd =3D { + .clks =3D impe_clks, + .num_clks =3D ARRAY_SIZE(impe_clks), +}; + +static const struct mtk_gate_regs impen_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMPEN(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &impen_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE) + +static const struct mtk_gate impen_clks[] =3D { + GATE_IMPEN(CLK_IMPEN_I2C7, "impen_i2c7", "i2c_sel", 0), + GATE_IMPEN(CLK_IMPEN_I2C8, "impen_i2c8", "i2c_sel", 1), +}; + +static const struct mtk_clk_desc impen_mcd =3D { + .clks =3D impen_clks, + .num_clks =3D ARRAY_SIZE(impen_clks), +}; + +static const struct mtk_gate_regs imps_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMPS(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &imps_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE) + +static const struct mtk_gate imps_clks[] =3D { + GATE_IMPS(CLK_IMPS_I2C3, "imps_i2c3", "i2c_sel", 0), + GATE_IMPS(CLK_IMPS_I2C4, "imps_i2c4", "i2c_sel", 1), + GATE_IMPS(CLK_IMPS_I2C5, "imps_i2c5", "i2c_sel", 2), + GATE_IMPS(CLK_IMPS_I2C6, "imps_i2c6", "i2c_sel", 3), +}; + +static const struct mtk_clk_desc imps_mcd =3D { + .clks =3D imps_clks, + .num_clks =3D ARRAY_SIZE(imps_clks), +}; + +static const struct mtk_gate_regs impws_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x4, + .sta_ofs =3D 0x0, +}; + +#define GATE_IMPWS(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &impws_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE) + +static const struct mtk_gate impws_clks[] =3D { + GATE_IMPWS(CLK_IMPWS_I2C2, "impws_i2c2", "i2c_sel", 0), +}; + +static const struct mtk_clk_desc impws_mcd =3D { + .clks =3D impws_clks, + .num_clks =3D ARRAY_SIZE(impws_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_iic[] =3D { + { .compatible =3D "mediatek,mt8189-iic-wrap-e", .data =3D &impe_mcd }, + { .compatible =3D "mediatek,mt8189-iic-wrap-en", .data =3D &impen_mcd }, + { .compatible =3D "mediatek,mt8189-iic-wrap-s", .data =3D &imps_mcd }, + { .compatible =3D "mediatek,mt8189-iic-wrap-ws", .data =3D &impws_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_iic); + +static struct platform_driver clk_mt8189_iic_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-iic", + .of_match_table =3D of_match_clk_mt8189_iic, + }, +}; + +module_platform_driver(clk_mt8189_iic_drv); +MODULE_DESCRIPTION("MediaTek MT8189 iic clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2