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The serial engine must be properly setup before kernel reach "init", so UART driver and its dependencies needs to be built in, enable its dependency GCC, interconnect and pinctrl as built-in meanwhile enable TCSRCC as module. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Jingyi Wang --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index cdb7d69e3b24..5aac8878f676 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -642,6 +642,7 @@ CONFIG_PINCTRL_IPQ5424=3Dy CONFIG_PINCTRL_IPQ8074=3Dy CONFIG_PINCTRL_IPQ6018=3Dy CONFIG_PINCTRL_IPQ9574=3Dy +CONFIG_PINCTRL_KAANAPALI=3Dy CONFIG_PINCTRL_MSM8916=3Dy CONFIG_PINCTRL_MSM8953=3Dy CONFIG_PINCTRL_MSM8976=3Dy @@ -1425,6 +1426,8 @@ CONFIG_COMMON_CLK_MT8192_SCP_ADSP=3Dy CONFIG_COMMON_CLK_MT8192_VDECSYS=3Dy CONFIG_COMMON_CLK_MT8192_VENCSYS=3Dy CONFIG_COMMON_CLK_QCOM=3Dy +CONFIG_CLK_KAANAPALI_GCC=3Dy +CONFIG_CLK_KAANAPALI_TCSRCC=3Dm CONFIG_CLK_X1E80100_CAMCC=3Dm CONFIG_CLK_X1E80100_DISPCC=3Dm CONFIG_CLK_X1E80100_GCC=3Dy @@ -1801,6 +1804,7 @@ CONFIG_INTERCONNECT_IMX8MN=3Dm CONFIG_INTERCONNECT_IMX8MQ=3Dm CONFIG_INTERCONNECT_IMX8MP=3Dy CONFIG_INTERCONNECT_QCOM=3Dy +CONFIG_INTERCONNECT_QCOM_KAANAPALI=3Dy CONFIG_INTERCONNECT_QCOM_MSM8916=3Dm CONFIG_INTERCONNECT_QCOM_MSM8953=3Dy CONFIG_INTERCONNECT_QCOM_MSM8996=3Dy --=20 2.25.1 From nobody Mon Dec 15 23:31:19 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 280B832C33B for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ac3c13d60bsm15439671eec.0.2025.12.15.01.07.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Dec 2025 01:07:36 -0800 (PST) From: Jingyi Wang Date: Mon, 15 Dec 2025 01:07:23 -0800 Subject: [PATCH v4 3/5] arm64: dts: qcom: Introduce Kaanapali SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251215-knp-dts-v4-3-1541bebeb89f@oss.qualcomm.com> References: <20251215-knp-dts-v4-0-1541bebeb89f@oss.qualcomm.com> In-Reply-To: <20251215-knp-dts-v4-0-1541bebeb89f@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Jingyi Wang , Tengfei Fan X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765789652; l=43645; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=DcvOaFpkQQkzDYW4EUZMRF63T6PkEkrqZZd5aDoFRDo=; b=D2sq8BAa+eJL8PSM8nvCWIFudYcMeS7y0Y6dULG5Rgfvk1miSi++/cBXzaMGNEc+PGPb/DK7M pGGFjsHPTlHA6gwgRj8lgxTI+zHI7/0XRwIkBeW+Q6e8xA7hbASaYvv X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Authority-Analysis: v=2.4 cv=ftPRpV4f c=1 sm=1 tr=0 ts=693fcfdb cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=P7TurCwWt9EVGe50nVwA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE1MDA3NiBTYWx0ZWRfX8+yBsIWCWmk3 v3KqFeW4zj2A3ENdVPX/dV94a6viXH5oV3AWFddewoOUx3kV5yZQ27ykS+Joy2ixNWA0dgM6uXk 5IXaIMWZ8kh4AfnrsSbQtxDVa9id0QE0D8Ko8mgM/mqwrUBUXI7XOt1NxUkWLwC5E3Z8Q/x248A D+3gEKE8NTDHoEYTJgWwC+Y6K3ZsIzlLRtiiiTbLKzmX3LeDs6M1y/I//EA5XDzdjH5x8FgSami aw7XGLmKvCq4s2Pjhztw9E0GqUfN9j2XU+mwZENUFCyxSWlsj69p1i+NErbuJ+mefqqp0wI4HW7 B1jw1w6TJsH00FhfWT4ajqO/+h6R5vo0SJ+Wv+9PleYqr5UvWNPpRRnPdN6R4sP8wT8121XBv/0 Q9P9JBf8aelh6iXMeopUIEd1qbboPA== X-Proofpoint-ORIG-GUID: x7GQMfo70HR2CuvtwGIjT7e_ujEvn5lk X-Proofpoint-GUID: x7GQMfo70HR2CuvtwGIjT7e_ujEvn5lk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-15_01,2025-12-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 spamscore=0 suspectscore=0 phishscore=0 clxscore=1015 bulkscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512150076 Kaanapali is Snapdragon SoC from Qualcomm. Features added in this patch: - CPUs with PSCI idle states and cpufreq - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - GCC and RPMHCC - TLMM - Interconnect with CPU BWMONs - QuP with UART - SMMU - RPMhPD - UFS with Inline Crypto Engine - LLCC - Watchdog - SD Card - PCIe Written with help from Raviteja Laggyshetty (added interconnect nodes), Taniya Das (added Clock Controllers and cpufreq), Jishnu Prakash (added RPMhPD), Nitin Rawat (added UFS), Gaurav Kashyap (added ICE), Manish Pandey (added SD Card) and Qiang Yu (added PCIe). Co-developed-by: Tengfei Fan Signed-off-by: Tengfei Fan Signed-off-by: Jingyi Wang Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1606 +++++++++++++++++++++++++++= ++++ 1 file changed, 1606 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi new file mode 100644 index 000000000000..51f8b3e0749c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -0,0 +1,1606 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "kaanapali-ipcc.h" + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 0>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 0>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 0>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 0>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd4>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 0>; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd5>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 0>; + }; + + cpu6: cpu@10000 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x10000>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_1>; + power-domains =3D <&cpu_pd6>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 1>; + + l2_1: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu7: cpu@10100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x10100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_1>; + power-domains =3D <&cpu_pd7>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu6>; + }; + + core1 { + cpu =3D <&cpu7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cluster0_c4: cpu-sleep-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "retention"; + arm,psci-suspend-param =3D <0x00000004>; + entry-latency-us =3D <93>; + exit-latency-us =3D <129>; + min-residency-us =3D <560>; + }; + + cluster1_c4: cpu-sleep-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "retention"; + arm,psci-suspend-param =3D <0x00000004>; + entry-latency-us =3D <172>; + exit-latency-us =3D <130>; + min-residency-us =3D <686>; + }; + }; + + domain-idle-states { + cluster_cl5: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x01000054>; + entry-latency-us =3D <2150>; + exit-latency-us =3D <1983>; + min-residency-us =3D <9144>; + }; + + domain_ss3: domain-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x0200c354>; + entry-latency-us =3D <2800>; + exit-latency-us =3D <4400>; + min-residency-us =3D <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-kaanapali", "qcom,scm"; + qcom,dload-mode =3D <&tcsr 0x19000>; + interconnects =3D <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + }; + + scmi: scmi { + compatible =3D "arm,scmi"; + mboxes =3D <&pdp0_mbox 0>, <&pdp0_mbox 1>; + mbox-names =3D "tx", "rx"; + shmem =3D <&pdp_tx>, <&pdp_rx>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + pdp_scmi_perf: protocol@13 { + reg =3D <0x13>; + #clock-cells =3D <1>; + }; + }; + }; + + clk_virt: interconnect-0 { + compatible =3D "qcom,kaanapali-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible =3D "qcom,kaanapali-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + memory@a0000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster1_c4>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster1_c4>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_cl5>; + power-domains =3D <&system_pd>; + }; + + system_pd: power-domain-system { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&domain_ss3>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + pdp_mem: pdp@81300000 { + reg =3D <0x0 0x81300000 0x0 0x100000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@81c60000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + smem_mem: smem@81d00000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x81d00000 0x0 0x200000>; + hwlocks =3D <&tcsr_mutex 3>; + no-map; + }; + + pdp_ns_shared_mem: pdp-ns-shared@81f00000 { + reg =3D <0x0 0x81f00000 0x0 0x100000>; + no-map; + }; + + dsm_partition_1_mem: dsm-partition-1@84a00000 { + reg =3D <0x0 0x84a00000 0x0 0x5500000>; + no-map; + }; + + dsm_partition_2_mem: dsm-partition-2@89f00000 { + reg =3D <0x0 0x89f00000 0x0 0xa80000>; + no-map; + }; + + mpss_mem: mpss@8aa00000 { + reg =3D <0x0 0x8aa00000 0x0 0xeb00000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@99500000 { + reg =3D <0x0 0x99500000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@99580000 { + reg =3D <0x0 0x99580000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@99590000 { + reg =3D <0x0 0x99590000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@9959a000 { + reg =3D <0x0 0x9959a000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera@99600000 { + reg =3D <0x0 0x99600000 0x0 0x800000>; + no-map; + }; + + camera_2_mem: camera-2@99e00000 { + reg =3D <0x0 0x99e00000 0x0 0x800000>; + no-map; + }; + + video_mem: video@9a600000 { + reg =3D <0x0 0x9a600000 0x0 0x800000>; + no-map; + }; + + cvp_mem: cvp@9ae00000 { + reg =3D <0x0 0x9ae00000 0x0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp@9b500000 { + reg =3D <0x0 0x9b500000 0x0 0x1900000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb@9ce00000 { + reg =3D <0x0 0x9ce00000 0x0 0x80000>; + no-map; + }; + + soccp_mem: soccp@a03d0000 { + reg =3D <0x0 0xa03d0000 0x0 0x500000>; + no-map; + }; + + soccp_dtb_mem: soccp-dtb@a08d0000 { + reg =3D <0x0 0xa08d0000 0x0 0x40000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb@a1380000 { + reg =3D <0x0 0xa1380000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi@a1400000 { + reg =3D <0x0 0xa1400000 0x0 0x4c00000>; + no-map; + }; + + rmtfs_mem: rmtfs@d7c00000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0xd7c00000 0x0 0x400000>; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D ; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; + ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,kaanapali-gcc"; + reg =3D <0x0 0x00100000 0x0 0x1f4200>; + + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>, + <&pcie0_phy>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <0>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + qupv3_1: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AXI_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + iommus =3D <&apps_smmu 0xa3 0x0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + uart7: serial@a9c000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x00a9c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart7_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + ipcc: mailbox@1106000 { + compatible =3D "qcom,kaanapali-ipcc", "qcom,ipcc"; + reg =3D <0x0 0x01106000 0x0 0x1000>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + + #mbox-cells =3D <2>; + }; + + cnoc_main: interconnect@1500000 { + compatible =3D "qcom,kaanapali-cnoc-main"; + reg =3D <0x0 0x01500000 0x0 0x1a080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + config_noc: interconnect@1600000 { + compatible =3D "qcom,kaanapali-cnoc-cfg"; + reg =3D <0x0 0x01600000 0x0 0x6200>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,kaanapali-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x1f080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + pcie_noc: interconnect@16c0000 { + compatible =3D "qcom,kaanapali-pcie-anoc"; + reg =3D <0x0 0x016c0000 0x0 0x11400>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + }; + + aggre_noc: interconnect@16e0000 { + compatible =3D "qcom,kaanapali-aggre-noc"; + reg =3D <0x0 0x016e0000 0x0 0x42400>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; + + mmss_noc: interconnect@1780000 { + compatible =3D "qcom,kaanapali-mmss-noc"; + reg =3D <0x0 0x01780000 0x0 0x5b800>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + pcie0: pcie@1c00000 { + device_type =3D "pci"; + compatible =3D "qcom,kaanapali-pcie", "qcom,pcie-sm8550"; + reg =3D <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr", + "cnoc_sf_axi"; + + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + interconnects =3D <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + power-domains =3D <&gcc GCC_PCIE_0_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + + operating-points-v2 =3D <&pcie0_opp_table>; + + iommu-map =3D <0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 0x7>; + #interrupt-cells =3D <1>; + + msi-map =3D <0x0 &gic_its 0x1400 0x1>, + <0x100 &gic_its 0x1401 0x1>; + msi-map-mask =3D <0xff00>; + max-link-speed =3D <3>; + linux,pci-domain =3D <0>; + num-lanes =3D <2>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + status =3D "disabled"; + + pcie0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <984500 1>; + }; + + /* GEN 3 x2 */ + opp-16000000 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <1969000 1>; + }; + }; + + pcie_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + phys =3D <&pcie0_phy>; + }; + }; + + pcie0_phy: phy@1c06000 { + compatible =3D "qcom,kaanapali-qmp-gen3x2-pcie-phy"; + reg =3D <0x0 0x01c06000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>, + <&gcc GCC_PCIE_0_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr"; + + power-domains =3D <&gcc GCC_PCIE_0_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie0_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + ufs_mem_phy: phy@1d80000 { + compatible =3D "qcom,kaanapali-qmp-ufs-phy", "qcom,sm8750-qmp-ufs-phy"; + reg =3D <0x0 0x01d80000 0x0 0x2000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; + + clock-names =3D "ref", + "ref_aux", + "qref"; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + + power-domains =3D <&gcc GCC_UFS_MEM_PHY_GDSC>; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible =3D "qcom,kaanapali-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg =3D <0x0 0x01d84000 0x0 0x3000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + operating-points-v2 =3D <&ufs_opp_table>; + + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + interconnects =3D <&aggre_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "ufs-ddr", + "cpu-ufs"; + + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0x60 0x0>; + dma-coherent; + + lanes-per-direction =3D <2>; + qcom,ice =3D <&ice>; + + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + + #reset-cells =3D <1>; + + status =3D "disabled"; + + ufs_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-403000000 { + opp-hz =3D /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + ice: crypto@1d88000 { + compatible =3D "qcom,kaanapali-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg =3D <0x0 0x01d88000 0x0 0x18000>; + + clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible =3D "qcom,kaanapali-tcsr", "syscon"; + reg =3D <0x0 0x01fc0000 0x0 0x30000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible =3D "qcom,kaanapali-lpass-lpiaon-noc"; + reg =3D <0x0 0x07400000 0x0 0x19080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible =3D "qcom,kaanapali-lpass-lpicx-noc"; + reg =3D <0x0 0x07420000 0x0 0x44080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + lpass_ag_noc: interconnect@7f40000 { + compatible =3D "qcom,kaanapali-lpass-ag-noc"; + reg =3D <0x0 0x07f40000 0x0 0xe080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + sdhc_2: mmc@8804000 { + compatible =3D "qcom,kaanapali-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x08804000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "core", "xo"; + + interconnects =3D <&aggre_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&sdhc2_opp_table>; + + qcom,dll-config =3D <0x0007442c>; + qcom,ddr-config =3D <0x80040868>; + + iommus =3D <&apps_smmu 0x540 0x0>; + dma-coherent; + + resets =3D <&gcc GCC_SDCC2_BCR>; + status =3D "disabled"; + + sdhc2_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + opp-peak-kBps =3D <160000 100000>; + opp-avg-kBps =3D <50000 0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + opp-peak-kBps =3D <200000 120000>; + opp-avg-kBps =3D <104000 0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,kaanapali-pdc", "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x10000>, + <0x0 0x179600f0 0x0 0xf4>; + + qcom,pdc-ranges =3D <0 745 38>, + <40 785 11>, + <51 527 4>, + <58 534 2>, + <61 537 20>, + <84 559 14>, + <98 609 32>, + <130 717 12>, + <142 251 5>, + <147 796 16>, + <163 783 2>, + <165 531 2>, + <167 536 1>, + <168 557 2>, + <170 415 1>, + <171 438 1>, + <172 579 1>, + <173 703 1>, + <174 708 1>, + <175 714 1>, + <176 68 1>, + <177 86 1>, + <178 96 1>, + <179 249 1>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + aoss_qmp: power-management@c300000 { + compatible =3D "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0x0 0x0c300000 0x0 0x400>; + + interrupts-extended =3D <&ipcc IPCC_MPROC_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells =3D <0>; + }; + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,kaanapali-tlmm"; + reg =3D <0x0 0x0f100000 0x0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 218>; + interrupt-controller; + #interrupt-cells =3D <2>; + wakeup-parent =3D <&pdc>; + + qup_uart7_default: qup-uart7-state { + /* TX, RX */ + pins =3D "gpio62", "gpio63"; + function =3D "qup1_se7"; + drive-strength =3D <2>; + bias-disable; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + + card-detect-pins { + pins =3D "gpio55"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + + card-detect-pins { + pins =3D "gpio55"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + }; + + sram@14680000 { + compatible =3D "qcom,kaanapali-imem", "mmio-sram"; + reg =3D <0x0 0x14680000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x14680000 0x1000>; + + no-memory-wc; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + pil-sram@94c { + compatible =3D "qcom,pil-reloc-info"; + reg =3D <0x94c 0xc8>; + }; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,kaanapali-smmu-500", "qcom,smmu-500", "arm,mmu-500= "; + reg =3D <0x0 0x15000000 0x0 0x100000>; + + interrupts =3D, + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + + dma-coherent; + }; + + intc: interrupt-controller@17000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x200000>; + + interrupts =3D ; + + #interrupt-cells =3D <3>; + interrupt-controller; + + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x40000>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic_its: msi-controller@17040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x17040000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + }; + + watchdog@17600000 { + compatible =3D "qcom,apss-wdt-kaanapali", "qcom,kpss-wdt"; + reg =3D <0x0 0x17600000 0x0 0x1000>; + clocks =3D <&sleep_clk>; + interrupts =3D ; + }; + + pdp0_mbox: mailbox@17610000 { + compatible =3D "qcom,kaanapali-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg =3D <0x0 0x17610000 0x0 0x8000>, <0x0 0x19980000 0x0 0x8000>; + interrupts =3D ; + #mbox-cells =3D <1>; + }; + + timer@17810000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17810000 0x0 0x1000>; + + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x0 0x0 0x20000000>; + + frame@17811000 { + reg =3D <0x0 0x17811000 0x1000>, + <0x0 0x17812000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + + frame@17813000 { + reg =3D <0x0 0x17813000 0x1000>; + frame-number =3D <1>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17815000 { + reg =3D <0x0 0x17815000 0x1000>; + frame-number =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17817000 { + reg =3D <0x0 0x17817000 0x1000>; + frame-number =3D <3>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17819000 { + reg =3D <0x0 0x17819000 0x1000>; + frame-number =3D <4>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@1781b000 { + reg =3D <0x0 0x1781b000 0x1000>; + frame-number =3D <5>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@1781d000 { + reg =3D <0x0 0x1781d000 0x1000>; + frame-number =3D <6>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@18900000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18900000 0x0 0x10000>, + <0x0 0x18910000 0x0 0x10000>, + <0x0 0x18920000 0x0 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + interrupts =3D , + , + ; + + power-domains =3D <&system_pd>; + label =3D "apps_rsc"; + + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,kaanapali-rpmh-clk"; + #clock-cells =3D <1>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,kaanapali-rpmhpd"; + + operating-points-v2 =3D <&rpmhpd_opp_table>; + + #power-domain-cells =3D <1>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d3: opp-50 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d2_1: opp-51 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d1_1: opp-54 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_l0: opp-76 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_l2: opp-96 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l2: opp-224 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l0: opp-400 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l2: opp-432 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l3: opp-448 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l4: opp-452 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l5: opp-456 { + opp-level =3D ; + }; + + rpmhpd_opp_super_turbo_no_cpr: opp-480 { + opp-level =3D ; + }; + }; + }; + }; + + nsp_noc: interconnect@260c0000 { + compatible =3D "qcom,kaanapali-nsp-noc"; + reg =3D <0x0 0x260c0000 0x0 0x21280>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + /* Cluster 0 */ + pmu@310b3400 { + compatible =3D "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; + reg =3D <0x0 0x310b3400 0x0 0x600>; + + interrupts =3D ; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 =3D <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-0 { + opp-peak-kBps =3D <2188000>; + }; + + opp-1 { + opp-peak-kBps =3D <5412000>; + }; + + opp-2 { + opp-peak-kBps =3D <6220000>; + }; + + opp-3 { + opp-peak-kBps =3D <6832000>; + }; + + opp-4 { + opp-peak-kBps =3D <8368000>; + }; + + opp-5 { + opp-peak-kBps =3D <10944000>; + }; + + opp-6 { + opp-peak-kBps =3D <12748000>; + }; + + opp-7 { + opp-peak-kBps =3D <14744000>; + }; + + opp-8 { + opp-peak-kBps =3D <16896000>; + }; + + opp-9 { + opp-peak-kBps =3D <19120000>; + }; + + opp-10 { + opp-peak-kBps =3D <21332000>; + }; + }; + }; + + /* Cluster 1 */ + pmu@310b7400 { + compatible =3D "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; + reg =3D <0x0 0x310b7400 0x0 0x600>; + + interrupts =3D ; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 =3D <&cpu_bwmon_opp_table>; + }; + + gem_noc: interconnect@31100000 { + compatible =3D "qcom,kaanapali-gem-noc"; + reg =3D <0x0 0x31100000 0x0 0x153080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + system-cache-controller@31800000 { + compatible =3D "qcom,kaanapali-llcc"; + reg =3D <0x0 0x31800000 0x0 0x200000>, + <0x0 0x32800000 0x0 0x200000>, + <0x0 0x31c00000 0x0 0x200000>, + <0x0 0x32c00000 0x0 0x200000>, + <0x0 0x34800000 0x0 0x200000>, + <0x0 0x34c00000 0x0 0x200000>; + reg-names =3D "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ac3c13d60bsm15439671eec.0.2025.12.15.01.07.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Dec 2025 01:07:37 -0800 (PST) From: Jingyi Wang Date: Mon, 15 Dec 2025 01:07:24 -0800 Subject: [PATCH v4 4/5] arm64: dts: qcom: kaanapali: Add base MTP board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251215-knp-dts-v4-4-1541bebeb89f@oss.qualcomm.com> References: <20251215-knp-dts-v4-0-1541bebeb89f@oss.qualcomm.com> In-Reply-To: <20251215-knp-dts-v4-0-1541bebeb89f@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Jingyi Wang , Dmitry Baryshkov X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765789652; l=23816; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=4Efl78C8pyw+hoEtIJfsPs/QdgTQ3zjDSBiSKuJLGVQ=; b=/vpJY24yq9l1l51Ird6e78ptRqKUJtrYXv3SHYm4YY6ZEyfub1/mAG30XuucsvDR7NI/b3ZD4 1QMab5KpBHhBl/Hq+WXH9NWBN6MO/T/kflM207pFpBjscv0HHKjJSrl X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE1MDA3NiBTYWx0ZWRfX7GESPRqMlPp8 OjWFRVfJdxRms7JyJnJrjbKzTBiBh7/2y5M1NyLC6Xx1vXGRuYLj4VpNUG9Lgxy7o7citPHoB8G DUjhekb7Rgfi6ueZ/FmFCVZsSxDex7zntsQAdHX+p5+QtAQBHNBy0UefMUQFbDvvM+Lp5ZHjx+m u+G/EH8Oa1HYIOl+i5JFw6+OBwOrP/ZXCXVgDMZmO0OyzvvynYZiSVZLcjd1dH6wfIQOQM+UlvD m6VOeft6hrLATHz7mLahUy2hiVvQ92Nd7voUkWCqsdXMMHpJCrlx8iGiMhrC5qp6NYqy9xn3/SW FHfr0tAABYNbBglxWQ0h6pk6kljQag7bH/C6RuzaWliQKHekMcnnw0a/C9+76MAmiPupTCPWnMQ 5anZ9DPf11L/HAqaD0dIDACMeFewjw== X-Proofpoint-GUID: VB1c__EvD49__0cXRdnvUNP50cSqHG_W X-Authority-Analysis: v=2.4 cv=E6nAZKdl c=1 sm=1 tr=0 ts=693fcfdd cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=tb9M4NetvsSJUPytCegA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-ORIG-GUID: VB1c__EvD49__0cXRdnvUNP50cSqHG_W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-15_01,2025-12-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 adultscore=0 clxscore=1015 spamscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512150076 Add initial support for Qualcomm Kaanapali MTP board which enables PCIe, SD Card, UFS and booting to shell with UART console. Written with help from Jishnu Prakash (added RPMhPD nodes), Nitin Rawat (added UFS), Manish Pandey (added SD Card) and Qiang Yu (added PCIe). Reviewed-by: Dmitry Baryshkov Signed-off-by: Jingyi Wang Reviewed-by: Abel Vesa --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 754 +++++++++++++++++++++++++= ++++ 2 files changed, 755 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 6f34d5ed331c..ac6c0178aae4 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp454.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D kaanapali-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk.dtb =20 lemans-evk-camera-csi1-imx577-dtbs :=3D lemans-evk.dtb lemans-evk-camera-c= si1-imx577.dtbo diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/d= ts/qcom/kaanapali-mtp.dts new file mode 100644 index 000000000000..32a082598434 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -0,0 +1,754 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include "kaanapali.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. Kaanapali MTP"; + compatible =3D "qcom,kaanapali-mtp", "qcom,kaanapali"; + chassis-type =3D "handset"; + + aliases { + serial0 =3D &uart7; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <76800000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32764>; + #clock-cells =3D <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id =3D "B_E0"; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <4000000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2704000>; + regulator-max-microvolt =3D <3552000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name =3D "vreg_l1b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3048000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name =3D "vreg_l4b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <3100000>; + regulator-max-microvolt =3D <3148000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name =3D "vreg_l7b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name =3D "vreg_l8b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name =3D "vreg_l10b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11b_1p0: ldo11 { + regulator-name =3D "vreg_l11b_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1292000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name =3D "vreg_l12b_1p8"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name =3D "vreg_l14b_3p2"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l18b_1p2: ldo18 { + regulator-name =3D "vreg_l18b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "D_E0"; + + vreg_s10d_1p0: smps10 { + regulator-name =3D "vreg_s10d_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_l1d_1p2: ldo1 { + regulator-name =3D "vreg_l1d_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1256000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name =3D "vreg_l2d_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <958000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3d_0p8: ldo3 { + regulator-name =3D "vreg_l3d_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4d_1p2: ldo4 { + regulator-name =3D "vreg_l4d_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "F_E0"; + + vreg_s6f_0p5: smps6 { + regulator-name =3D "vreg_s6f_0p5"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <570000>; + regulator-initial-mode =3D ; + }; + + vreg_s7f_1p2: smps7 { + regulator-name =3D "vreg_s7f_1p2"; + regulator-min-microvolt =3D <1224000>; + regulator-max-microvolt =3D <1372000>; + regulator-initial-mode =3D ; + }; + + vreg_s8f_1p8: smps8 { + regulator-name =3D "vreg_s8f_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_1p2: ldo1 { + regulator-name =3D "vreg_l1f_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2f_1p2: ldo2 { + regulator-name =3D "vreg_l2f_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3f_0p8: ldo3 { + regulator-name =3D "vreg_l3f_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <936000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4f_0p8: ldo4 { + regulator-name =3D "vreg_l4f_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "G_E0"; + + vreg_s7g_0p9: smps7 { + regulator-name =3D "vreg_s7g_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_s9g_1p0: smps9 { + regulator-name =3D "vreg_s9g_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name =3D "vreg_l1g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2g_1p8: ldo2 { + regulator-name =3D "vreg_l2g_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name =3D "vreg_l3g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4g_0p9: ldo4 { + regulator-name =3D "vreg_l4g_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "I_E0"; + + vreg_s7i_0p9: smps7 { + regulator-name =3D "vreg_s7i_0p9"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <972000>; + regulator-initial-mode =3D ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name =3D "vreg_l2i_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name =3D "vreg_l3i_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-5 { + compatible =3D "qcom,pmh0104-rpmh-regulators"; + qcom,pmic-id =3D "J_E1"; + + vreg_s1j_0p8: smps1 { + regulator-name =3D "vreg_s1j_0p8"; + regulator-min-microvolt =3D <400000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + }; + + vreg_s2j_0p8: smps2 { + regulator-name =3D "vreg_s2j_0p8"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_s3j_1p2: smps3 { + regulator-name =3D "vreg_s3j_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + }; + + vreg_s4j_0p7: smps4 { + regulator-name =3D "vreg_s4j_0p7"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-6 { + compatible =3D "qcom,pmr735d-rpmh-regulators"; + qcom,pmic-id =3D "K_E1"; + + vreg_l1k_0p8: ldo1 { + regulator-name =3D "vreg_l1k_0p8"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2k_0p7: ldo2 { + regulator-name =3D "vreg_l2k_0p7"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3k_1p2: ldo3 { + regulator-name =3D "vreg_l3k_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4k_1p0: ldo4 { + regulator-name =3D "vreg_l4k_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5k_0p7: ldo5 { + regulator-name =3D "vreg_l5k_0p7"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6k_1p7: ldo6 { + regulator-name =3D "vreg_l6k_1p7"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7k_0p7: ldo7 { + regulator-name =3D "vreg_l7k_0p7"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <848000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-7 { + compatible =3D "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id =3D "M_E1"; + + vreg_l1m_1p0: ldo1 { + regulator-name =3D "vreg_l1m_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2m_1p0: ldo2 { + regulator-name =3D "vreg_l2m_1p0"; + regulator-min-microvolt =3D <1096000>; + regulator-max-microvolt =3D <1104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name =3D "vreg_l3m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2900000>; + regulator-initial-mode =3D ; + }; + + vreg_l4m_2p2: ldo4 { + regulator-name =3D "vreg_l4m_2p2"; + regulator-min-microvolt =3D <2200000>; + regulator-max-microvolt =3D <2200000>; + regulator-initial-mode =3D ; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name =3D "vreg_l6m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l7m_2p8: ldo7 { + regulator-name =3D "vreg_l7m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-8 { + compatible =3D "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id =3D "N_E1"; + + vreg_l1n_1p1: ldo1 { + regulator-name =3D "vreg_l1n_1p1"; + regulator-min-microvolt =3D <1096000>; + regulator-max-microvolt =3D <1104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2n_1p2: ldo2 { + regulator-name =3D "vreg_l2n_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name =3D "vreg_l3n_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name =3D "vreg_l4n_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name =3D "vreg_l5n_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name =3D "vreg_l6n_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name =3D "vreg_l7n_3p3"; + regulator-min-microvolt =3D <3304000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&pcie0 { + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l3i_0p8>; + vdda-pll-supply =3D <&vreg_l1d_1p2>; + + status =3D "okay"; +}; + +&pcie_port0 { + wake-gpios =3D <&tlmm 104 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&tlmm 102 GPIO_ACTIVE_LOW>; +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 55 GPIO_ACTIVE_LOW>; + + vmmc-supply =3D <&vreg_l9b_2p9>; + vqmmc-supply =3D <&vreg_l8b_1p8>; + + bus-width =3D <4>; + no-sdio; + no-mmc; + + pinctrl-0 =3D <&sdc2_default>; + pinctrl-1 =3D <&sdc2_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; +}; + +&tlmm { + gpio-reserved-ranges =3D <36 4>, /* NFC eSE SPI */ + <74 1>, /* eSE */ + <119 2>, /* SoCCP */ + <144 4>; /* CXM UART */ + + pcie0_default_state: pcie0-default-state { + perst-n-pins { + pins =3D "gpio102"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + clkreq-n-pins { + pins =3D "gpio103"; + function =3D "pcie0_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake-n-pins { + pins =3D "gpio104"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; +}; + +&uart7 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 217 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l17b_2p5>; + vcc-max-microamp =3D <1200000>; + vccq-supply =3D <&vreg_l4d_1p2>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l4g_0p9>; + vdda-pll-supply =3D <&vreg_l1d_1p2>; + + status =3D "okay"; +}; --=20 2.25.1 From nobody Mon Dec 15 23:31:19 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E10732F744 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ac3c13d60bsm15439671eec.0.2025.12.15.01.07.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Dec 2025 01:07:38 -0800 (PST) From: Jingyi Wang Date: Mon, 15 Dec 2025 01:07:25 -0800 Subject: [PATCH v4 5/5] arm64: dts: qcom: kaanapali: Add base QRD board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251215-knp-dts-v4-5-1541bebeb89f@oss.qualcomm.com> References: <20251215-knp-dts-v4-0-1541bebeb89f@oss.qualcomm.com> In-Reply-To: <20251215-knp-dts-v4-0-1541bebeb89f@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Jingyi Wang , Dmitry Baryshkov X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765789652; l=23008; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=mdANDSNEIC5lQ5TbLF7yScpuPNZGHRntBOP09/3K8o8=; b=etglql6JdVsd39Uog6FGqNEUlFYtysw+mBJNldOei2Bkdy8JoQTQknhRtcbbfMd51B5Mkcgbe geAmlxNn8DwDKjV3/OX/B2H7ggxjk7YV0rrRtD7UXp3IlW+DFF1D3I8 X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Authority-Analysis: v=2.4 cv=TtDrRTXh c=1 sm=1 tr=0 ts=693fcfdd cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=HxS99sl-kXwyYRSu5lYA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE1MDA3NiBTYWx0ZWRfXyGptatogbumx YLKb7AcGx0rwDtv3Xlc8EFwozf+qekzV+wOPkZrtSoJL6U+A6Ghkj88bxuv+FCaIW1fHUuuSrv2 /0OwypcxQz+wk+EDnd+CBQ6b37974Wy0aJx9vrCr6jkFLlpH8eEI9y+j+sDjwo71BlYxYgRUS5i 3pKqwwkU8mza8NQykWB21V9mNa95R/7EnBcNLt2n9fsnmcchlMVfmkkhXlpXsa/PfV/wNwNMsEL vc/j3UsScfzsouiZVod8mHyFBmslx1314qsYNVII/PJ4kRah4otQhnbQHXRwya7TE5rkOvQSlww p32FFsE/V6rAS0xspdyB1sAAqJo9vPlkVsx+Fyhbx/hFCMQRrjM2N/BlRgeNQi7uxgSgBba1Ach JxhVFxbFeWCQjtwS3da3SGJ4JhCKMg== X-Proofpoint-GUID: HNNXapGOh9iqqlrNCfoioH_dgKyJ-4uH X-Proofpoint-ORIG-GUID: HNNXapGOh9iqqlrNCfoioH_dgKyJ-4uH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-15_01,2025-12-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512150076 Add initial support for Qualcomm Kaanapali QRD board which enables SD Card, UFS and booting to shell with UART console. Written with help from Jishnu Prakash (added RPMhPD nodes), Nitin Rawat (added ufs) and Manish Pandey (added SD Card). Reviewed-by: Dmitry Baryshkov Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 712 +++++++++++++++++++++++++= ++++ 2 files changed, 713 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index ac6c0178aae4..699d61d30280 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D kaanapali-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D kaanapali-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk.dtb =20 lemans-evk-camera-csi1-imx577-dtbs :=3D lemans-evk.dtb lemans-evk-camera-c= si1-imx577.dtbo diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/d= ts/qcom/kaanapali-qrd.dts new file mode 100644 index 000000000000..66b423a497b3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -0,0 +1,712 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include "kaanapali.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. Kaanapali QRD"; + compatible =3D "qcom,kaanapali-qrd", "qcom,kaanapali"; + chassis-type =3D "handset"; + + aliases { + serial0 =3D &uart7; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <76800000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32764>; + #clock-cells =3D <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id =3D "B_E0"; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <4000000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2704000>; + regulator-max-microvolt =3D <3552000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name =3D "vreg_l1b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3048000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name =3D "vreg_l4b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <3100000>; + regulator-max-microvolt =3D <3148000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name =3D "vreg_l7b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name =3D "vreg_l8b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name =3D "vreg_l10b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11b_1p0: ldo11 { + regulator-name =3D "vreg_l11b_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1292000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name =3D "vreg_l12b_1p8"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name =3D "vreg_l14b_3p2"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l18b_1p2: ldo18 { + regulator-name =3D "vreg_l18b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "D_E0"; + + vreg_s10d_1p0: smps10 { + regulator-name =3D "vreg_s10d_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_l1d_1p2: ldo1 { + regulator-name =3D "vreg_l1d_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1256000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name =3D "vreg_l2d_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <958000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3d_0p8: ldo3 { + regulator-name =3D "vreg_l3d_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4d_1p2: ldo4 { + regulator-name =3D "vreg_l4d_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "F_E0"; + + vreg_s6f_0p5: smps6 { + regulator-name =3D "vreg_s6f_0p5"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <570000>; + regulator-initial-mode =3D ; + }; + + vreg_s7f_1p2: smps7 { + regulator-name =3D "vreg_s7f_1p2"; + regulator-min-microvolt =3D <1224000>; + regulator-max-microvolt =3D <1372000>; + regulator-initial-mode =3D ; + }; + + vreg_s8f_1p8: smps8 { + regulator-name =3D "vreg_s8f_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_1p2: ldo1 { + regulator-name =3D "vreg_l1f_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2f_1p2: ldo2 { + regulator-name =3D "vreg_l2f_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3f_0p8: ldo3 { + regulator-name =3D "vreg_l3f_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <936000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4f_0p8: ldo4 { + regulator-name =3D "vreg_l4f_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "G_E0"; + + vreg_s7g_0p9: smps7 { + regulator-name =3D "vreg_s7g_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_s9g_1p0: smps9 { + regulator-name =3D "vreg_s9g_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name =3D "vreg_l1g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2g_1p8: ldo2 { + regulator-name =3D "vreg_l2g_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name =3D "vreg_l3g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4g_0p9: ldo4 { + regulator-name =3D "vreg_l4g_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "I_E0"; + + vreg_s7i_0p9: smps7 { + regulator-name =3D "vreg_s7i_0p9"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <972000>; + regulator-initial-mode =3D ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name =3D "vreg_l2i_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name =3D "vreg_l3i_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-5 { + compatible =3D "qcom,pmh0104-rpmh-regulators"; + qcom,pmic-id =3D "J_E1"; + + vreg_s1j_0p8: smps1 { + regulator-name =3D "vreg_s1j_0p8"; + regulator-min-microvolt =3D <400000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + }; + + vreg_s2j_0p8: smps2 { + regulator-name =3D "vreg_s2j_0p8"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_s3j_1p2: smps3 { + regulator-name =3D "vreg_s3j_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + }; + + vreg_s4j_0p7: smps4 { + regulator-name =3D "vreg_s4j_0p7"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-6 { + compatible =3D "qcom,pmr735d-rpmh-regulators"; + qcom,pmic-id =3D "K_E1"; + + vreg_l1k_0p8: ldo1 { + regulator-name =3D "vreg_l1k_0p8"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2k_0p7: ldo2 { + regulator-name =3D "vreg_l2k_0p7"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3k_1p2: ldo3 { + regulator-name =3D "vreg_l3k_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4k_1p0: ldo4 { + regulator-name =3D "vreg_l4k_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5k_0p7: ldo5 { + regulator-name =3D "vreg_l5k_0p7"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6k_1p7: ldo6 { + regulator-name =3D "vreg_l6k_1p7"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7k_0p7: ldo7 { + regulator-name =3D "vreg_l7k_0p7"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <848000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-7 { + compatible =3D "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id =3D "M_E1"; + + vreg_l1m_1p0: ldo1 { + regulator-name =3D "vreg_l1m_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2m_1p0: ldo2 { + regulator-name =3D "vreg_l2m_1p0"; + regulator-min-microvolt =3D <1096000>; + regulator-max-microvolt =3D <1104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name =3D "vreg_l3m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2900000>; + regulator-initial-mode =3D ; + }; + + vreg_l4m_2p2: ldo4 { + regulator-name =3D "vreg_l4m_2p2"; + regulator-min-microvolt =3D <2200000>; + regulator-max-microvolt =3D <2200000>; + regulator-initial-mode =3D ; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name =3D "vreg_l6m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l7m_2p8: ldo7 { + regulator-name =3D "vreg_l7m_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-8 { + compatible =3D "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id =3D "N_E1"; + + vreg_l1n_1p1: ldo1 { + regulator-name =3D "vreg_l1n_1p1"; + regulator-min-microvolt =3D <1096000>; + regulator-max-microvolt =3D <1104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2n_1p2: ldo2 { + regulator-name =3D "vreg_l2n_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name =3D "vreg_l3n_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name =3D "vreg_l4n_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name =3D "vreg_l5n_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name =3D "vreg_l6n_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name =3D "vreg_l7n_3p3"; + regulator-min-microvolt =3D <3304000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 55 GPIO_ACTIVE_LOW>; + + vmmc-supply =3D <&vreg_l9b_2p9>; + vqmmc-supply =3D <&vreg_l8b_1p8>; + + bus-width =3D <4>; + no-sdio; + no-mmc; + + pinctrl-0 =3D <&sdc2_default>; + pinctrl-1 =3D <&sdc2_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; +}; + +&tlmm { + gpio-reserved-ranges =3D <36 4>, /* NFC eSE SPI */ + <74 1>, /* eSE */ + <119 2>, /* SoCCP */ + <144 4>; /* CXM UART */ +}; + +&uart7 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 217 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l17b_2p5>; + vcc-max-microamp =3D <1200000>; + vccq-supply =3D <&vreg_l4d_1p2>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l4g_0p9>; + vdda-pll-supply =3D <&vreg_l1d_1p2>; + + status =3D "okay"; +}; --=20 2.25.1