From nobody Tue Dec 16 08:52:25 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAE862D0625; Mon, 15 Dec 2025 12:42:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765802545; cv=none; b=Re5/6t/dr6IJuy5vNFoGJ2YC02069xVloalairBRu+b8+BPHULBkGLJgm3PlHKUreSYNdWEMF/Tb/m+eM4Q2D19VC7W4YEhEx7iaR1mnEra6kceOXz5BcBWBGxAqZTECREava7o4e9U73XHju0cvacCM+e9i4X4XwPaqEugcAzo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765802545; c=relaxed/simple; bh=oZPi5EyJ/MJZ1+Rxh/gbO6jBHriV28sNnHkCk71/260=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PoSnUOmOisKoc3M0Ox22L6/wqEfmF+K1HqdVSnZ4kFCDeJ+ERct2/AQh6CBGsjcTb8AOdlgps5DTyLl/rtMDkbxqStu60bvB2FEAtS3EsUs5LxNDJSkqm5xd+c66J3pcoRsyLV7Hz9esNinixw2Z0uekLiWF/afB1AFjRwQjmaA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HsJ/6soP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HsJ/6soP" Received: by smtp.kernel.org (Postfix) with ESMTPS id 69271C16AAE; Mon, 15 Dec 2025 12:42:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1765802545; bh=oZPi5EyJ/MJZ1+Rxh/gbO6jBHriV28sNnHkCk71/260=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HsJ/6soPArN4lHsDwv44a64WxUONrCzBBkbediexAYlXlr/LaQdEFHFRSA1On11H8 T0D/yMEl20FcrBDafRjKurp+ednls3S5ljNVM1/ULgomdjQYYK6QU0prL0uOiowF47 TzC6EuD9S7mZ1weNCQQy+of1tLbMtmaXYQCyUdpD9/SLsP0rQh7C0skzPsmoo8F7uU /f/G+g1jELEbKYUnFLEnjtslQfBAPwhTsv9cA/g66ZNFWGpL+LfD5NMaesG40O5rY5 /3IwwrSGmvRsZldb/E6QwSG0qNLArDc3peviOQOwcqTmuEVaUxu7SpSSlIl5AepW6a ECBuExaHtfwWw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48349D59D99; Mon, 15 Dec 2025 12:42:25 +0000 (UTC) From: Xiangxu Yin via B4 Relay Date: Mon, 15 Dec 2025 20:41:57 +0800 Subject: [PATCH v8 01/12] dt-bindings: phy: Add QMP USB3+DP PHY for QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251215-add-displayport-support-for-qcs615-platform-v8-1-cbc72c88a44e@oss.qualcomm.com> References: <20251215-add-displayport-support-for-qcs615-platform-v8-0-cbc72c88a44e@oss.qualcomm.com> In-Reply-To: <20251215-add-displayport-support-for-qcs615-platform-v8-0-cbc72c88a44e@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Dmitry Baryshkov , Bjorn Andersson , Konrad Dybcio , Xiangxu Yin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765802541; l=3524; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=c37lHyKAfNqHHZwzu6h0ZBVIk4rQzgE8GLOefpC2o5U=; b=fC7NDEuFJp9TUUUQNoadX34giD5b1dvGKL1/asqCe6PljFG9NfXZnnP61RI84R0+FWCm+02FM KqIKij0QfdfAj2faLp84xDR6KN/YgR+MXACq20uOHNNd6Oc+2ml9u9r X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Endpoint-Received: by B4 Relay for xiangxu.yin@oss.qualcomm.com/20241125 with auth_id=542 X-Original-From: Xiangxu Yin Reply-To: xiangxu.yin@oss.qualcomm.com From: Xiangxu Yin Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY on QCS615 Platform. This PHY supports both USB3 and DP functionality over USB-C, with PHY mode switching capability. It does not support combo mode. Reviewed-by: Rob Herring (Arm) Signed-off-by: Xiangxu Yin --- .../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml | 111 +++++++++++++++++= ++++ 1 file changed, 111 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.= yaml new file mode 100644 index 000000000000..efb465c71c1b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615) + +maintainers: + - Xiangxu Yin + +description: + The QMP PHY controller supports physical layer functionality for both US= B3 + and DisplayPort over USB-C. While it enables mode switching between USB3= and + DisplayPort, but does not support combo mode. + +properties: + compatible: + enum: + - qcom,qcs615-qmp-usb3-dp-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: aux + - const: ref + - const: cfg_ahb + - const: pipe + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy_phy + - const: dp_phy + + vdda-phy-supply: true + + vdda-pll-supply: true + + "#clock-cells": + const: 1 + description: + See include/dt-bindings/phy/phy-qcom-qmp.h + + "#phy-cells": + const: 1 + description: + See include/dt-bindings/phy/phy-qcom-qmp.h + + qcom,tcsr-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the VLS CLAMP register + - description: offset of the PHY mode register + description: Clamp and PHY mode register present in the TCSR + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - "#clock-cells" + - "#phy-cells" + - qcom,tcsr-reg + +additionalProperties: false + +examples: + - | + #include + #include + + phy@88e8000 { + compatible =3D "qcom,qcs615-qmp-usb3-dp-phy"; + reg =3D <0x88e8000 0x2000>; + + clocks =3D <&gcc GCC_USB2_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>, + <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets =3D <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_DP_PHY_SEC_BCR>; + reset-names =3D "phy_phy", + "dp_phy"; + + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + qcom,tcsr-reg =3D <&tcsr 0xbff0 0xb24c>; + }; --=20 2.34.1