From nobody Mon Dec 15 23:31:48 2025 Received: from out-179.mta1.migadu.com (out-179.mta1.migadu.com [95.215.58.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B981624BBEE for ; Mon, 15 Dec 2025 08:22:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765786960; cv=none; b=E72ncK87MD+YtD6jppTu5155JACF7HksccolLGz9hgZwtuluXhNoPz4WDj/WVf43K9O/akN1F9dnG7Ndw3f7l8d5xeL25GkpNWoLOTLKvQ9Gf/g8UpFsBGzuC4wDGw7+Tyz2fylNILD7QUcw1TuDhFMaQszorGrnaPNu4GfXJGs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765786960; c=relaxed/simple; bh=3XZ0kMOkmhXJkUgXZqo3ZjEbGyvsIUXKZG61LlH0dTU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KymNMx/tvI4dOoU1oYDRiLuN25R5ySFBeC0lUdR4BtxMgKqofdqwxw13yklLqsljhLfIGqa/gn2URgctbmQev0G2BQ8dUF2UfJSS+GcCMDW4p13P5x+NRnrKc1cYK09wM9vjo+uQ/3iVLXGwYxNKYKlrph1Ov5qyJXCENVOQvpY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=ayWeislS; arc=none smtp.client-ip=95.215.58.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="ayWeislS" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1765786956; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oLJdLwQTD/0wHQRSqI/Lqi0DxQEzBBtNavs5xmL24Kw=; b=ayWeislSn7/ZmidHHP3gcOyrfJ/n2g4DzRUKwm7oUNbiZMOsyVWcBbHLMXPdJKg531gW7f 6xy9aBRO/8zaQJMi6F5wxut0avt3MEEwiUBjKFPfksjGgNSv3gBxBDtb4fdVV3wWJ8Gx74 HE6DgvKziq9eBfy+CU8aNYyUUIqCMQk= From: George Guo Date: Mon, 15 Dec 2025 16:22:01 +0800 Subject: [PATCH v6 1/4] LoongArch: Add SCQ support detection Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251215-2-v6-1-09a486e8df99@linux.dev> References: <20251215-2-v6-0-09a486e8df99@linux.dev> In-Reply-To: <20251215-2-v6-0-09a486e8df99@linux.dev> To: Huacai Chen , WANG Xuerui , hengqi.chen@gmail.com Cc: r@hev.cc, xry111@xry111.site, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, George Guo , George Guo , Yangyang Lian X-Developer-Signature: v=1; a=ed25519-sha256; t=1765786949; l=3909; i=dongtai.guo@linux.dev; s=20251103; h=from:subject:message-id; bh=OKOY1aPzYkum+Trqg6DK3AnIryJ6rYAevr9PZQRiEA0=; b=qjgmEmnYqY6Ezu/QUXekCmlvLCFb9jgzhiLHAOM5v2G8vw+iF0DcWCLXQYd+aVEWzAiJbs2oM NDoAuPRR29+B7hBfbhb/ONJ6roQ/doq5zQe+JYcvfcB04FVsAErZrTQ X-Developer-Key: i=dongtai.guo@linux.dev; a=ed25519; pk=yHUJPGx/kAXutP/NSHpj7hWW0KQNlv3w9H6ju4qUoTM= X-Migadu-Flow: FLOW_OUT From: George Guo Check CPUCFG2_SCQ bit to determin if the CPU supports SCQ instrction. Co-developed-by: Yangyang Lian Signed-off-by: Yangyang Lian Signed-off-by: George Guo --- arch/loongarch/include/asm/cpu-features.h | 1 + arch/loongarch/include/asm/cpu.h | 2 ++ arch/loongarch/include/asm/loongarch.h | 1 + arch/loongarch/kernel/cpu-probe.c | 2 ++ arch/loongarch/kernel/proc.c | 1 + 5 files changed, 7 insertions(+) diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/inc= lude/asm/cpu-features.h index bd5f0457ad21d89ab902fb1971cc8b41b1d340ad..860cb58a92ba0c0316a8009d974= 41043374e7f10 100644 --- a/arch/loongarch/include/asm/cpu-features.h +++ b/arch/loongarch/include/asm/cpu-features.h @@ -70,5 +70,6 @@ #define cpu_has_msgint cpu_opt(LOONGARCH_CPU_MSGINT) #define cpu_has_avecint cpu_opt(LOONGARCH_CPU_AVECINT) #define cpu_has_redirectint cpu_opt(LOONGARCH_CPU_REDIRECTINT) +#define cpu_has_scq cpu_opt(LOONGARCH_CPU_SCQ) =20 #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/= cpu.h index f3efb00b61414a9b111ade9fe9beb410b927d937..5531039027ec763f21c7a6a8868= 5ec81fa61d3cc 100644 --- a/arch/loongarch/include/asm/cpu.h +++ b/arch/loongarch/include/asm/cpu.h @@ -125,6 +125,7 @@ static inline char *id_to_core_name(unsigned int id) #define CPU_FEATURE_MSGINT 29 /* CPU has MSG interrupt */ #define CPU_FEATURE_AVECINT 30 /* CPU has AVEC interrupt */ #define CPU_FEATURE_REDIRECTINT 31 /* CPU has interrupt remapping */ +#define CPU_FEATURE_SCQ 32 /* CPU has SC.Q instruction */ =20 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG) #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM) @@ -158,5 +159,6 @@ static inline char *id_to_core_name(unsigned int id) #define LOONGARCH_CPU_MSGINT BIT_ULL(CPU_FEATURE_MSGINT) #define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT) #define LOONGARCH_CPU_REDIRECTINT BIT_ULL(CPU_FEATURE_REDIRECTINT) +#define LOONGARCH_CPU_SCQ BIT_ULL(CPU_FEATURE_SCQ) =20 #endif /* _ASM_CPU_H */ diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/includ= e/asm/loongarch.h index 3de03cb864b248cd0fb5de9ec5a86b1436ccbdef..be04b3e6f5b0cd6c5d561efcfd9= 9502bc24e5eee 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -94,6 +94,7 @@ #define CPUCFG2_LSPW BIT(21) #define CPUCFG2_LAM BIT(22) #define CPUCFG2_PTW BIT(24) +#define CPUCFG2_SCQ BIT(30) =20 #define LOONGARCH_CPUCFG3 0x3 #define CPUCFG3_CCDMA BIT(0) diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-= probe.c index a2060a24b39fd78fa255816fa5518e0ee99b8a8e..5c5ead3eb0895c1a20abba1e19f= 02226a2657b1f 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -201,6 +201,8 @@ static void cpu_probe_common(struct cpuinfo_loongarch *= c) c->options |=3D LOONGARCH_CPU_PTW; elf_hwcap |=3D HWCAP_LOONGARCH_PTW; } + if (config & CPUCFG2_SCQ) + c->options |=3D LOONGARCH_CPU_SCQ; if (config & CPUCFG2_LSPW) { c->options |=3D LOONGARCH_CPU_LSPW; elf_hwcap |=3D HWCAP_LOONGARCH_LSPW; diff --git a/arch/loongarch/kernel/proc.c b/arch/loongarch/kernel/proc.c index 63d2b7e7e844b0647a3e0d988ec2adb6c77b9b14..f1ad1773425eba5becfd31bc730= eed0f2d19589d 100644 --- a/arch/loongarch/kernel/proc.c +++ b/arch/loongarch/kernel/proc.c @@ -75,6 +75,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) if (cpu_has_lbt_x86) seq_printf(m, " lbt_x86"); if (cpu_has_lbt_arm) seq_printf(m, " lbt_arm"); if (cpu_has_lbt_mips) seq_printf(m, " lbt_mips"); + if (cpu_has_scq) seq_printf(m, " scq"); seq_printf(m, "\n"); =20 seq_printf(m, "Hardware Watchpoint\t: %s", str_yes_no(cpu_has_watch)); --=20 2.49.0 From nobody Mon Dec 15 23:31:48 2025 Received: from out-171.mta1.migadu.com (out-171.mta1.migadu.com [95.215.58.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F24D226B74A for ; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1765786959; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6KDuNOF7zwOqq4SGBvigFpNcY4PTnIkUpXxey+/fvOw=; b=DBt9YTa9zJ+3QinVRkgpDHlgf+sITCx/uDb0D9zsZ600tsoPCq5ZfpX3iXVlhLYngHDo+v NJx8xOEfWf4hSRx+5wkanni8hGjQ0uRTy5KGbyVeeYJ9S0eDjL0T7rQG9psHQxjlUD6CdQ YbsVt8ZowEqJBo7K329NeKp7vdYZErE= From: George Guo Date: Mon, 15 Dec 2025 16:22:02 +0800 Subject: [PATCH v6 2/4] LoongArch: Add 128-bit atomic cmpxchg support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251215-2-v6-2-09a486e8df99@linux.dev> References: <20251215-2-v6-0-09a486e8df99@linux.dev> In-Reply-To: <20251215-2-v6-0-09a486e8df99@linux.dev> To: Huacai Chen , WANG Xuerui , hengqi.chen@gmail.com Cc: r@hev.cc, xry111@xry111.site, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, George Guo , George Guo X-Developer-Signature: v=1; a=ed25519-sha256; t=1765786949; l=2734; i=dongtai.guo@linux.dev; s=20251103; h=from:subject:message-id; bh=G9Rok0Fvrnc2B8Tx4x6JiuOW/GjTomdEObq8AwW7z40=; b=fw7ut4I9ZLopgq1mXsaGHLFF5PYp9hiu+0QFVBw9HMVlP63LJ+2Ry3a3OyacpQTkA/ib7c2Bp SW0OOS2FJ3/Dq4nL602n4gpkico2uzI1H5XfriAq8YGXZlDc6nd8r90 X-Developer-Key: i=dongtai.guo@linux.dev; a=ed25519; pk=yHUJPGx/kAXutP/NSHpj7hWW0KQNlv3w9H6ju4qUoTM= X-Migadu-Flow: FLOW_OUT From: George Guo Implement 128-bit atomic compare-and-exchange using LoongArch's LL.D/SC.Q instructions. At the same time, fix BPF scheduler test failures (scx_central scx_qmap) caused by kmalloc_nolock_noprof returning NULL due to missing 128-bit atomics. The NULL returns led to -ENOMEM errors during scheduler initialization, causing test cases to fail. Verified by testing with the scx_qmap scheduler (located in tools/sched_ext/). Building with `make` and running ./tools/sched_ext/build/bin/scx_qmap. Signed-off-by: George Guo --- arch/loongarch/include/asm/cmpxchg.h | 47 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 47 insertions(+) diff --git a/arch/loongarch/include/asm/cmpxchg.h b/arch/loongarch/include/= asm/cmpxchg.h index 979fde61bba8a42cb4f019f13ded2a3119d4aaf4..f7a0a9a032c513196ef186a5493= b500787e0e9b6 100644 --- a/arch/loongarch/include/asm/cmpxchg.h +++ b/arch/loongarch/include/asm/cmpxchg.h @@ -111,6 +111,44 @@ __arch_xchg(volatile void *ptr, unsigned long x, int s= ize) __ret; \ }) =20 +union __u128_halves { + u128 full; + struct { + u64 low; + u64 high; + }; +}; + +#define __cmpxchg128_asm(ptr, old, new) \ +({ \ + union __u128_halves __old, __new, __ret; \ + volatile u64 *__ptr =3D (volatile u64 *)(ptr); \ + \ + __old.full =3D (old); \ + __new.full =3D (new); \ + \ + __asm__ __volatile__( \ + "1: ll.d %0, %3 # 128-bit cmpxchg low \n" \ + __WEAK_LLSC_MB \ + " ld.d %1, %4 # 128-bit cmpxchg high \n" \ + " bne %0, %z5, 2f \n" \ + " bne %1, %z6, 2f \n" \ + " move $t0, %z7 \n" \ + " move $t1, %z8 \n" \ + " sc.q $t0, $t1, %2 \n" \ + " beqz $t0, 1b \n" \ + "2: \n" \ + __WEAK_LLSC_MB \ + : "=3D&r" (__ret.low), "=3D&r" (__ret.high) \ + : "r" (__ptr), \ + "ZC" (__ptr[0]), "m" (__ptr[1]), \ + "Jr" (__old.low), "Jr" (__old.high), \ + "Jr" (__new.low), "Jr" (__new.high) \ + : "t0", "t1", "memory"); \ + \ + __ret.full; \ +}) + static inline unsigned int __cmpxchg_small(volatile void *ptr, unsigned in= t old, unsigned int new, unsigned int size) { @@ -198,6 +236,15 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsig= ned long new, unsigned int __res; \ }) =20 +/* cmpxchg128 */ +#define system_has_cmpxchg128() 1 + +#define arch_cmpxchg128(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 16); \ + __cmpxchg128_asm(ptr, o, n); \ +}) + #ifdef CONFIG_64BIT #define arch_cmpxchg64_local(ptr, o, n) \ ({ \ --=20 2.49.0 From nobody Mon Dec 15 23:31:48 2025 Received: from out-182.mta1.migadu.com (out-182.mta1.migadu.com [95.215.58.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 130FA2DBF76 for ; Mon, 15 Dec 2025 08:22:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765786965; cv=none; b=t1Af/sU79xuPT/0N7IkQsj4hSWqh/NaPYJTQKdkwTz53/6wIcXOu6enPZ+xwM4Z13vUfihKsMJYNcu/q5uLWJ72Swj8RwzpQt/QKU2Wao2XsyWiYCo3gB/W16r7ZRodiv20vgGdQLXhQUpP79LLhrFWxyHywucy8plu5iNYuTR4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765786965; c=relaxed/simple; bh=1ydGX2ckPcbDTOaBlko8S4H7H/Su4Cxx0zFDcMsJB+g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Vohq28DiYZh11uqRMRCR6xOG+gtUUjubivYzzoPbjjMTNRc9xAK/zQXIZmqMyslZJrNQJykM/S1U0Cr+jxgvkaHfGMlFEnPi5A7Kg4YHyuw4gGFgwNZxmvhdxEZqo24rfYXfuwFPJN7zh0DiD3c67gMZ1l4oWRi1gfbUrQ9TTBc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=GHHcRbZw; arc=none smtp.client-ip=95.215.58.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="GHHcRbZw" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1765786962; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wbG/hNpFVx1z8RtgsmITOX2lkUrENsQeLW2JOQQh7ZM=; b=GHHcRbZw+d9jgizZdsPGQo+9tyHpkuyoJk3W/stLsT90YwnpanaBEGH465t9M7xx+yfGoK vxz9TQWo6F7XYyKpeBIkCORGnlbzyn0PqAo6oxx6aE0FjFy1T+YXv6CK8O4ooORjH7bX4U hmvPlpEI/g+47+4Wsg41NFeLGDlB7zw= From: George Guo Date: Mon, 15 Dec 2025 16:22:03 +0800 Subject: [PATCH v6 3/4] LoongArch: Use spinlock to emulate 128-bit cmpxchg Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251215-2-v6-3-09a486e8df99@linux.dev> References: <20251215-2-v6-0-09a486e8df99@linux.dev> In-Reply-To: <20251215-2-v6-0-09a486e8df99@linux.dev> To: Huacai Chen , WANG Xuerui , hengqi.chen@gmail.com Cc: r@hev.cc, xry111@xry111.site, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, George Guo , George Guo X-Developer-Signature: v=1; a=ed25519-sha256; t=1765786949; l=1861; i=dongtai.guo@linux.dev; s=20251103; h=from:subject:message-id; bh=PCzsPV7oGfaIDaA0cqRcyRoMNSMiHxOqDWfuZv8Lz68=; b=SBr2LlbovI73LnV5uHeY21CD3nGNBn4rnlKlI+sJpWsHzLVBQvc3oknqIzXC7P54IQvi8u4fN Lvkvnm7VTNIAgV9Iycg/TVCTxHMQH5tYLPdVl3nbR8p4t9i2eEnj2A5 X-Developer-Key: i=dongtai.guo@linux.dev; a=ed25519; pk=yHUJPGx/kAXutP/NSHpj7hWW0KQNlv3w9H6ju4qUoTM= X-Migadu-Flow: FLOW_OUT From: George Guo For LoongArch CPUs lacking 128-bit atomic instruction(e.g., the SCQ instruction on 3A5000), provide a fallback implementation of __cmpxchg128 using a spinlock to emulate the atomic operation. Signed-off-by: George Guo --- arch/loongarch/include/asm/cmpxchg.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/include/asm/cmpxchg.h b/arch/loongarch/include/= asm/cmpxchg.h index f7a0a9a032c513196ef186a5493b500787e0e9b6..814097bfc334184018747e47fb9= 0fd2d2fb27ee2 100644 --- a/arch/loongarch/include/asm/cmpxchg.h +++ b/arch/loongarch/include/asm/cmpxchg.h @@ -8,6 +8,7 @@ #include #include #include +#include =20 #define __xchg_asm(amswap_db, m, val) \ ({ \ @@ -149,6 +150,23 @@ union __u128_halves { __ret.full; \ }) =20 +#define __cmpxchg128_locked(ptr, old, new) \ +({ \ + u128 __ret; \ + static DEFINE_SPINLOCK(lock); \ + unsigned long flags; \ + \ + spin_lock_irqsave(&lock, flags); \ + \ + __ret =3D *(volatile u128 *)(ptr); \ + if (__ret =3D=3D (old)) \ + *(volatile u128 *)(ptr) =3D (new); \ + \ + spin_unlock_irqrestore(&lock, flags); \ + \ + __ret; \ +}) + static inline unsigned int __cmpxchg_small(volatile void *ptr, unsigned in= t old, unsigned int new, unsigned int size) { @@ -242,7 +260,8 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsign= ed long new, unsigned int #define arch_cmpxchg128(ptr, o, n) \ ({ \ BUILD_BUG_ON(sizeof(*(ptr)) !=3D 16); \ - __cmpxchg128_asm(ptr, o, n); \ + cpu_has_scq ? __cmpxchg128_asm(ptr, o, n) : \ + __cmpxchg128_locked(ptr, o, n); \ }) =20 #ifdef CONFIG_64BIT --=20 2.49.0 From nobody Mon Dec 15 23:31:48 2025 Received: from out-172.mta1.migadu.com (out-172.mta1.migadu.com [95.215.58.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 663C031354E for ; Mon, 15 Dec 2025 08:22:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765786970; cv=none; b=gtVa5br8jeA+nLXxVL3YPwh6UaWSwERc2cF9zfJKqn0dgEbrbIw+uqMLNhrfvRmM8B2QK5/v8r/Pbxvg42Zy6blK/xtBq+0MKXxU7g2G6dcCKCf4BwrpVLubciednNM4v8fXFV8V461d/8T/2KIcWN0UIToDooicQ2v9DNFDjUg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765786970; c=relaxed/simple; bh=jBTSf1NBjHQ0A85ubxl+1PskFCEAy3vCJ4zJY+SfPYU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nITzEA5GxEmqrn1NDWueRqURohFimAuK/L//exFzNE6FA0K+fa3TOFYi4hXp2PdgM8fEUfPupvUy8qlYR+xS5g4lRX/kPh7bBzEixvlQcI+t/aP+TyRUvJMiNhEDWF6dvRPAvl6dX2rWoe+UoLvwjw7yR8Rizvrebsv7UX4Ecsc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=tSafFRUj; arc=none smtp.client-ip=95.215.58.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="tSafFRUj" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1765786965; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XnHdPbNZY+icNHDhsU00WTTGxUuRI5fAPK2EbH7Tj7Q=; b=tSafFRUjcri0kk/LKeDUWGBY16ZYmLR1FCdTK/b1GxPfQUw60oG41n8Doo1khp6SRKSWVA HIFgk+4lH3TcVlZbfKeYvJmYr9XMVYAguxeY7O9GJq7OOKEPgt7NssDpAxblxXj3NClpU7 DVUqPt8UI/wxDpiEuNEQcnerhHjs2PY= From: George Guo Date: Mon, 15 Dec 2025 16:22:04 +0800 Subject: [PATCH v6 4/4] LoongArch: Enable 128-bit atomics cmpxchg support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251215-2-v6-4-09a486e8df99@linux.dev> References: <20251215-2-v6-0-09a486e8df99@linux.dev> In-Reply-To: <20251215-2-v6-0-09a486e8df99@linux.dev> To: Huacai Chen , WANG Xuerui , hengqi.chen@gmail.com Cc: r@hev.cc, xry111@xry111.site, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, George Guo , George Guo X-Developer-Signature: v=1; a=ed25519-sha256; t=1765786949; l=1046; i=dongtai.guo@linux.dev; s=20251103; h=from:subject:message-id; bh=ciDWXt3BQSm1RCVw/2AyrNMAA+62PK+Q6MPycedHCU8=; b=1iI1XIbB8mlkKnO/8vzxPD4K1e2TfwP2hScjG31FoCnwv+LkIDUwXDCCUx8CJlI572cq9I5aV Tix9yEfvMpbDIlHnDIem4aXkAv3w6RY6XXVBNdIfaDkRy6miVC7x6zo X-Developer-Key: i=dongtai.guo@linux.dev; a=ed25519; pk=yHUJPGx/kAXutP/NSHpj7hWW0KQNlv3w9H6ju4qUoTM= X-Migadu-Flow: FLOW_OUT From: George Guo Add select HAVE_CMPXCHG_DOUBLE and select HAVE_ALIGNED_STRUCT_PAGE in Kconf= ig to enable 128-bit atomic cmpxchg support on LoongArch. Signed-off-by: George Guo --- arch/loongarch/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 5b1116733d881bc2b1b43fb93f20367add4dbc54..6fb2c253969f9ddece547892042= 3d7326c3ec046 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -114,6 +114,7 @@ config LOONGARCH select GENERIC_TIME_VSYSCALL select GPIOLIB select HAS_IOPORT + select HAVE_ALIGNED_STRUCT_PAGE select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_JUMP_LABEL select HAVE_ARCH_JUMP_LABEL_RELATIVE @@ -140,6 +141,7 @@ config LOONGARCH select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS select HAVE_DYNAMIC_FTRACE_WITH_REGS select HAVE_EBPF_JIT + select HAVE_CMPXCHG_DOUBLE select HAVE_EFFICIENT_UNALIGNED_ACCESS if !ARCH_STRICT_ALIGN select HAVE_EXIT_THREAD select HAVE_GENERIC_TIF_BITS --=20 2.49.0