From nobody Tue Dec 16 14:51:16 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C2E930C617 for ; Sun, 14 Dec 2025 18:02:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765735347; cv=none; b=BmcgSJzoiQGrAyIySDK11B/J27Dz0t7umDKZgWaytDwD5jxFIs8i4m/NIobl+UUCR4iVkQ05tCVPEGI/AxNwshaeFHBtYLNwE1laQNDQ6cyfYRtbhvcLM57L793nm5Mgu6ASQG4Xo3jiajN7AskSTn+Orqmb7JCALE70oibEbTM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765735347; c=relaxed/simple; bh=Upo/KeJ1tydzhEX3FEnB2Lq6CdSMUiNT1LlycW0K1NM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Pm1Njrb/2gjMjCY7SLaSXxIatTzhio/tyce1fPR3xBoyj30FI/XuDq2ecX5UPGxx0XXqkQxSHu8WnzZX6Ig7rPHEXMc6oxhLbfv9mbbWy8geNi/NvoOCV37HGBM/LZ6iD4j3NPQFpQdue+7G+UvkTEmhTcfH/7pjLqN+PMNr3Q8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gynnoUqd; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gynnoUqd" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-4775ae77516so32522805e9.1 for ; Sun, 14 Dec 2025 10:02:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1765735343; x=1766340143; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VFXHMGeoomdbZOLp3ce3D0yDHo0q4hSajO4R4fHl4CQ=; b=gynnoUqdjZdfIbkWjlVgJAF+2SgoVuno9diMquCkPmC64TQ868ryTl2CfbT1CBjX+G IliwzJWE6oieFTxjhBinSRhJ+3nxX2I3NizdATLIzQDglTvmPTeY0uY9bfljMWm47+ef gUJeG8L/5VQ18DrfqoJbM/ShBI15MjVP4UkIPpnv1soFmBwQjZ9YEQCDB3sPyH2KkfgT ki0oj+ZVETNyIgvcMdy70+dFRpI5iA6jzXylTRP32w34i0fYRL70onTbkDVLZN9fTMdN JMZy7rsRaKAaESBoboF/8apeBg33BqnRmyHuV1JKeEHQ7UwhLKtzyTp8k73DNZnWrCIX qsJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765735343; x=1766340143; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=VFXHMGeoomdbZOLp3ce3D0yDHo0q4hSajO4R4fHl4CQ=; b=hcJZYfVy9Y4DHCEAebreYNs+DniFjbO10tXp2EV+H6fzeI7FaK9InKjM4qLhrg8cwm 97+5pAKID5m0lEcdict60d0snsOhiR1B6XLHZaprhfcijHi6nYS8YTtQs+ITLp2ZHAfm LtIc0coWuFScKrOr3IGhMD0u4vghSZVwkG+u8uixz784MkfiIoMA4hR+qCuQv1eyZyw1 CZBJAH/CD7DDKP5hqdypCK4JQsgPXwn6AlU9Y/Uz7mn72UnOk17cJ1rujF6HBUUZYSfQ 29mJtlgNTNylgnY5CTvam3qb6JCff2AfmHmZ4a8DmHeBXGIw4yYXUdLXbbmXlLdss++K pWtg== X-Gm-Message-State: AOJu0YzjXeojEdFrosls6+STFgyJq4rbt7q5bFLL43FTC6bPMnO2AJoQ P6S/lRSfCjaJmRze/BhlZ3XKl18sI9W6kNyAMiiKd690zH3+83/yL38zPDIIQQ== X-Gm-Gg: AY/fxX5P8wpRef/+WpcpBlcrxyHYDtKnpkSL0SBhnO4/vYI44nn1bwNHg9cxcbQkPpO P2dHDAuPhmxUmK4GvKlM56a7n12b3ujYxtj8WjUDRMBlObmCXI+HxcwQNMVVsH6Iiz5pg6fr1Wk qJ2+PAwcvqrBGWiV1gfbsUGPLsMXpIgmXkxLTf+tkXXzUA97zFsVw+f6RzsoLvz56XqOrEFPszh NLMbrqkc63bE5GWeWhzeZ8tU/jPSavgjuMmv9KVWDaByUwGVsMPy7le9ApTRDAdjcDmXnYmshDZ rbPn6kBoBOK84AnldcdvZ/VO/HDEO4ls7tZYDhZkXze72v0DZCYdcNrVFrL5a+n/GEfDNgIWxRa Np2j+gNt+Rh7rJpCooJmPtVtJdYkEm5Zdsmi9RUyKANgnv5eW5cffECBZ6SLk04ApZ7ovc9uq+G Evf+jt48zAWCXEujNFFHsTeYPUNPB6L7EUy6tQTtwPrsEjAcQ2SMhliordDfhyYJF7 X-Google-Smtp-Source: AGHT+IFBYOK1tyGfwO114byCkmi23dhpNbs6vJuHuSe5U0l9V4ENnxuM2Cf0xygYGmqZgWbSG1E/mw== X-Received: by 2002:a05:6000:240a:b0:430:f494:6a9c with SMTP id ffacd0b85a97d-430f4946d3amr3593476f8f.17.1765735342647; Sun, 14 Dec 2025 10:02:22 -0800 (PST) Received: from localhost (brnt-04-b2-v4wan-170138-cust2432.vm7.cable.virginm.net. [94.175.9.129]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-430f5f6ede8sm7167762f8f.4.2025.12.14.10.02.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Dec 2025 10:02:21 -0800 (PST) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Jonas Bonn , Stefan Kristiansson , Thomas Gleixner Subject: [PATCH 3/5] openrisc: Fix IPIs on simple multicore systems Date: Sun, 14 Dec 2025 18:01:43 +0000 Message-ID: <20251214180158.3955285-4-shorne@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251214180158.3955285-1-shorne@gmail.com> References: <20251214180158.3955285-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit c05671846451 ("openrisc: sleep instead of spin on secondary wait") fixed OpenRISC SMP Linux for QEMU. However, stability was never achieved on FPGA development boards. This is because the above patch has a step to unmask IPIs on non-boot cpu's but on hardware without power management, IPIs remain masked. This meant that IPI's were never actually working on the simple SMP systems we run on development boards. The systems booted but stability was very suspect. Add the ability to unmask IPI's on the non-boot cores. This is done by making the OMPIC IRQs proper percpu IRQs. We can then use the enabled_percpu_irq() to unmask IRQ on the non-boot cpus. Update the or1k PIC driver to use a flow handler that can switch between percpu and the configured level or edge flow handlers at runtime. This mechanism is inspired by that done in the J-Core AIC driver. Signed-off-by: Stafford Horne --- arch/openrisc/include/asm/smp.h | 3 ++- arch/openrisc/kernel/smp.c | 22 +++++++++++++++++++++- drivers/irqchip/irq-ompic.c | 15 +++++++++++---- drivers/irqchip/irq-or1k-pic.c | 27 ++++++++++++++++++++++++++- 4 files changed, 60 insertions(+), 7 deletions(-) diff --git a/arch/openrisc/include/asm/smp.h b/arch/openrisc/include/asm/sm= p.h index e21d2f12b5b6..007296f160ef 100644 --- a/arch/openrisc/include/asm/smp.h +++ b/arch/openrisc/include/asm/smp.h @@ -20,7 +20,8 @@ extern void smp_init_cpus(void); extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); =20 -extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned i= nt)); +extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned i= nt), + unsigned int irq); extern void handle_IPI(unsigned int ipi_msg); =20 #endif /* __ASM_OPENRISC_SMP_H */ diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c index 86da4bc5ee0b..040ca201b692 100644 --- a/arch/openrisc/kernel/smp.c +++ b/arch/openrisc/kernel/smp.c @@ -13,6 +13,7 @@ =20 #include #include +#include #include #include #include @@ -25,6 +26,7 @@ =20 asmlinkage __init void secondary_start_kernel(void); =20 +static unsigned int ipi_irq __ro_after_init; static void (*smp_cross_call)(const struct cpumask *, unsigned int); =20 unsigned long secondary_release =3D -1; @@ -39,6 +41,14 @@ enum ipi_msg_type { =20 static DEFINE_SPINLOCK(boot_lock); =20 +static void or1k_ipi_enable(void) +{ + if (WARN_ON_ONCE(!ipi_irq)) + return; + + enable_percpu_irq(ipi_irq, 0); +} + static void boot_secondary(unsigned int cpu, struct task_struct *idle) { /* @@ -136,6 +146,7 @@ asmlinkage __init void secondary_start_kernel(void) complete(&cpu_running); =20 synchronise_count_slave(cpu); + or1k_ipi_enable(); set_cpu_online(cpu, true); =20 local_irq_enable(); @@ -195,9 +206,18 @@ void smp_send_stop(void) smp_call_function(stop_this_cpu, NULL, 0); } =20 -void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned= int)) +void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned= int), + unsigned int irq) { + if (WARN_ON(ipi_irq)) + return; + smp_cross_call =3D fn; + + ipi_irq =3D irq; + + /* Enabled IPIs for boot CPU immediately */ + or1k_ipi_enable(); } =20 void arch_send_call_function_single_ipi(int cpu) diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c index e66ef4373b1e..f0e0b435bb1d 100644 --- a/drivers/irqchip/irq-ompic.c +++ b/drivers/irqchip/irq-ompic.c @@ -84,6 +84,8 @@ DEFINE_PER_CPU(unsigned long, ops); =20 static void __iomem *ompic_base; =20 +static DEFINE_PER_CPU_READ_MOSTLY(int, ipi_dummy_dev); + static inline u32 ompic_readreg(void __iomem *base, loff_t offset) { return ioread32be(base + offset); @@ -183,12 +185,17 @@ static int __init ompic_of_init(struct device_node *n= ode, goto out_unmap; } =20 - ret =3D request_irq(irq, ompic_ipi_handler, IRQF_PERCPU, - "ompic_ipi", NULL); - if (ret) + irq_set_percpu_devid(irq); + ret =3D request_percpu_irq(irq, ompic_ipi_handler, "ompic_ipi", + &ipi_dummy_dev); + + if (ret) { + pr_err("ompic: failed to request irq %d, error: %d", + irq, ret); goto out_irq_disp; + } =20 - set_smp_cross_call(ompic_raise_softirq); + set_smp_cross_call(ompic_raise_softirq, irq); =20 return 0; =20 diff --git a/drivers/irqchip/irq-or1k-pic.c b/drivers/irqchip/irq-or1k-pic.c index 48126067c54b..73dc99c71d40 100644 --- a/drivers/irqchip/irq-or1k-pic.c +++ b/drivers/irqchip/irq-or1k-pic.c @@ -118,11 +118,36 @@ static void or1k_pic_handle_irq(struct pt_regs *regs) generic_handle_domain_irq(root_domain, irq); } =20 +/* + * The OR1K PIC is a cpu-local interrupt controller and does not distingui= sh or + * use distinct irq number ranges for per-cpu event interrupts (IPI). Since + * information to determine whether a particular irq number should be trea= ted as + * per-cpu is not available at mapping time, we use a wrapper handler func= tion + * which chooses the right handler at runtime based on whether IRQF_PERCPU= was + * used when requesting the irq. Borrowed from J-Core AIC. + */ +static void or1k_irq_flow_handler(struct irq_desc *desc) +{ +#ifdef CONFIG_SMP + struct irq_data *data =3D irq_desc_get_irq_data(desc); + struct or1k_pic_dev *pic =3D data->domain->host_data; + + if (irqd_is_per_cpu(data)) + handle_percpu_devid_irq(desc); + else + pic->handle(desc); +#endif +} + static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_= t hw) { struct or1k_pic_dev *pic =3D d->host_data; =20 - irq_set_chip_and_handler(irq, &pic->chip, pic->handle); + if (IS_ENABLED(CONFIG_SMP)) + irq_set_chip_and_handler(irq, &pic->chip, or1k_irq_flow_handler); + else + irq_set_chip_and_handler(irq, &pic->chip, pic->handle); + irq_set_status_flags(irq, pic->flags); =20 return 0; --=20 2.51.0