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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42fb7118267sm16191030f8f.27.2025.12.14.10.02.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Dec 2025 10:02:13 -0800 (PST) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/5] dt-bindings: Add compatible string opencores,gpio to gpio-mmio Date: Sun, 14 Dec 2025 18:01:41 +0000 Message-ID: <20251214180158.3955285-2-shorne@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251214180158.3955285-1-shorne@gmail.com> References: <20251214180158.3955285-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In FPGA Development boards with GPIOs we use the opencores gpio verilog rtl. This is compatible with the gpio-mmio. Add the compatible string to allow as below. Example: gpio0: gpio@91000000 { compatible =3D "opencores,gpio", "brcm,bcm6345-gpio"; reg =3D <0x91000000 0x1>, <0x91000001 0x1>; reg-names =3D "dat", "dirout"; gpio-controller; #gpio-cells =3D <2>; status =3D "okay"; }; Link: https://opencores.org/projects/gpio Signed-off-by: Stafford Horne --- Documentation/devicetree/bindings/gpio/gpio-mmio.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Docume= ntation/devicetree/bindings/gpio/gpio-mmio.yaml index b4d55bf6a285..0490580df19e 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml @@ -23,6 +23,7 @@ properties: - ni,169445-nand-gpio - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO contr= oller - intel,ixp4xx-expansion-bus-mmio-gpio + - opencores,gpio =20 big-endian: true =20 --=20 2.51.0 From nobody Tue Dec 16 07:34:18 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15EB72192FA for ; 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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47a8f74b17bsm146120235e9.2.2025.12.14.10.02.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Dec 2025 10:02:18 -0800 (PST) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonas Bonn , Stefan Kristiansson , devicetree@vger.kernel.org Subject: [PATCH 2/5] openrisc: dts: Add de0 nano config and devicetree Date: Sun, 14 Dec 2025 18:01:42 +0000 Message-ID: <20251214180158.3955285-3-shorne@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251214180158.3955285-1-shorne@gmail.com> References: <20251214180158.3955285-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The de0 nano from Terasic is an FPGA board that we use in the OpenRISC community to test OpenRISC configurations. Add a base configuration for the board that runs an OpenRISC CPU at 50Mhz with 32MB ram, UART for console and some GPIOs for LEDs and switches. There is an older version of this floating around that defines all of the hardware on the board including SPI's, flash devices, sram, ADCs etc. Eventually it would be good to get the full version upstream but for now I think a minimal board is good to start with. Link: https://openrisc.io/tutorials/de0_nano/ Link: https://github.com/olofk/de0_nano Signed-off-by: Stafford Horne --- arch/openrisc/boot/dts/de0-nano-common.dtsi | 41 +++++++++++ arch/openrisc/boot/dts/de0-nano.dts | 54 ++++++++++++++ arch/openrisc/configs/de0_nano_defconfig | 79 +++++++++++++++++++++ 3 files changed, 174 insertions(+) create mode 100644 arch/openrisc/boot/dts/de0-nano-common.dtsi create mode 100644 arch/openrisc/boot/dts/de0-nano.dts create mode 100644 arch/openrisc/configs/de0_nano_defconfig diff --git a/arch/openrisc/boot/dts/de0-nano-common.dtsi b/arch/openrisc/bo= ot/dts/de0-nano-common.dtsi new file mode 100644 index 000000000000..421c366d120e --- /dev/null +++ b/arch/openrisc/boot/dts/de0-nano-common.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include + +/ { + memory@0 { + device_type =3D "memory"; + reg =3D <0x00000000 0x02000000>; + }; + + leds: leds { + compatible =3D "gpio-leds"; + status =3D "okay"; + led-heartbeat { + gpios =3D <&gpio0 0 GPIO_ACTIVE_HIGH>; + color =3D ; + function =3D LED_FUNCTION_HEARTBEAT; + linux,default-trigger =3D "heartbeat"; + label =3D "heartbeat"; + }; + }; + + gpio0: gpio@91000000 { + compatible =3D "opencores,gpio", "brcm,bcm6345-gpio"; + reg =3D <0x91000000 0x1>, <0x91000001 0x1>; + reg-names =3D "dat", "dirout"; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "okay"; + }; + + gpio1: gpio@92000000 { + compatible =3D "opencores,gpio", "brcm,bcm6345-gpio"; + reg =3D <0x92000000 0x1>, <0x92000001 0x1>; + reg-names =3D "dat", "dirout"; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + }; +}; diff --git a/arch/openrisc/boot/dts/de0-nano.dts b/arch/openrisc/boot/dts/d= e0-nano.dts new file mode 100644 index 000000000000..06c9b0b2406e --- /dev/null +++ b/arch/openrisc/boot/dts/de0-nano.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "de0-nano-common.dtsi" + +/ { + model =3D "Terasic DE0 Nano"; + compatible =3D "opencores,or1ksim"; + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-parent =3D <&pic>; + + aliases { + uart0 =3D &serial0; + }; + + chosen { + bootargs =3D "earlycon"; + stdout-path =3D "uart0:115200"; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu@0 { + compatible =3D "opencores,or1200-rtlsvn481"; + reg =3D <0>; + clock-frequency =3D <50000000>; + }; + }; + + /* + * OR1K PIC is built into CPU and accessed via special purpose + * registers. It is not addressable and, hence, has no 'reg' + * property. + */ + pic: pic { + compatible =3D "opencores,or1k-pic"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + + serial0: serial@90000000 { + compatible =3D "opencores,uart16550-rtlsvn105", "ns16550a"; + reg =3D <0x90000000 0x100>; + interrupts =3D <2>; + clock-frequency =3D <50000000>; + }; +}; + +&gpio1 { + status =3D "okay"; +}; diff --git a/arch/openrisc/configs/de0_nano_defconfig b/arch/openrisc/confi= gs/de0_nano_defconfig new file mode 100644 index 000000000000..bc63905f9cd8 --- /dev/null +++ b/arch/openrisc/configs/de0_nano_defconfig @@ -0,0 +1,79 @@ +CONFIG_SYSVIPC=3Dy +CONFIG_NO_HZ=3Dy +CONFIG_LOG_BUF_SHIFT=3D14 +CONFIG_BLK_DEV_INITRD=3Dy +# CONFIG_RD_GZIP is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_ZSTD is not set +CONFIG_EXPERT=3Dy +# CONFIG_EPOLL is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +CONFIG_BUILTIN_DTB_NAME=3D"de0-nano" +# CONFIG_FPU is not set +CONFIG_HZ_100=3Dy +# CONFIG_BLOCK is not set +CONFIG_SLUB_TINY=3Dy +# CONFIG_COMPAT_BRK is not set +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_NET=3Dy +CONFIG_UNIX=3Dy +CONFIG_UNIX_DIAG=3Dy +CONFIG_INET=3Dy +CONFIG_IP_MULTICAST=3Dy +CONFIG_INET_UDP_DIAG=3Dy +CONFIG_INET_RAW_DIAG=3Dy +CONFIG_INET_DIAG_DESTROY=3Dy +# CONFIG_IPV6 is not set +CONFIG_DEVTMPFS=3Dy +CONFIG_DEVTMPFS_MOUNT=3Dy +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=3Dy +CONFIG_SERIAL_8250_CONSOLE=3Dy +CONFIG_SERIAL_OF_PLATFORM=3Dy +# CONFIG_HW_RANDOM is not set +CONFIG_PPS=3Dy +CONFIG_GPIO_SYSFS=3Dy +# CONFIG_GPIO_SYSFS_LEGACY is not set +CONFIG_GPIO_GENERIC_PLATFORM=3Dy +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_NEW_LEDS=3Dy +CONFIG_LEDS_CLASS=3Dy +CONFIG_LEDS_GPIO=3Dy +CONFIG_LEDS_TRIGGERS=3Dy +CONFIG_LEDS_TRIGGER_TIMER=3Dy +CONFIG_LEDS_TRIGGER_ONESHOT=3Dy +CONFIG_LEDS_TRIGGER_HEARTBEAT=3Dy +CONFIG_LEDS_TRIGGER_CPU=3Dy +CONFIG_LEDS_TRIGGER_ACTIVITY=3Dy +CONFIG_LEDS_TRIGGER_GPIO=3Dy +CONFIG_LEDS_TRIGGER_DEFAULT_ON=3Dy +CONFIG_LEDS_TRIGGER_TRANSIENT=3Dy +CONFIG_LEDS_TRIGGER_PANIC=3Dy +CONFIG_LEDS_TRIGGER_NETDEV=3Dy +CONFIG_LEDS_TRIGGER_PATTERN=3Dy +CONFIG_LEDS_TRIGGER_TTY=3Dy +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_DNOTIFY is not set +CONFIG_TMPFS=3Dy +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_ARM64 is not set +# CONFIG_XZ_DEC_SPARC is not set +# CONFIG_XZ_DEC_RISCV is not set +CONFIG_PRINTK_TIME=3Dy +# CONFIG_DEBUG_MISC is not set +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set --=20 2.51.0 From nobody Tue Dec 16 07:34:18 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C2E930C617 for ; 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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-430f5f6ede8sm7167762f8f.4.2025.12.14.10.02.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Dec 2025 10:02:21 -0800 (PST) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Jonas Bonn , Stefan Kristiansson , Thomas Gleixner Subject: [PATCH 3/5] openrisc: Fix IPIs on simple multicore systems Date: Sun, 14 Dec 2025 18:01:43 +0000 Message-ID: <20251214180158.3955285-4-shorne@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251214180158.3955285-1-shorne@gmail.com> References: <20251214180158.3955285-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit c05671846451 ("openrisc: sleep instead of spin on secondary wait") fixed OpenRISC SMP Linux for QEMU. However, stability was never achieved on FPGA development boards. This is because the above patch has a step to unmask IPIs on non-boot cpu's but on hardware without power management, IPIs remain masked. This meant that IPI's were never actually working on the simple SMP systems we run on development boards. The systems booted but stability was very suspect. Add the ability to unmask IPI's on the non-boot cores. This is done by making the OMPIC IRQs proper percpu IRQs. We can then use the enabled_percpu_irq() to unmask IRQ on the non-boot cpus. Update the or1k PIC driver to use a flow handler that can switch between percpu and the configured level or edge flow handlers at runtime. This mechanism is inspired by that done in the J-Core AIC driver. Signed-off-by: Stafford Horne --- arch/openrisc/include/asm/smp.h | 3 ++- arch/openrisc/kernel/smp.c | 22 +++++++++++++++++++++- drivers/irqchip/irq-ompic.c | 15 +++++++++++---- drivers/irqchip/irq-or1k-pic.c | 27 ++++++++++++++++++++++++++- 4 files changed, 60 insertions(+), 7 deletions(-) diff --git a/arch/openrisc/include/asm/smp.h b/arch/openrisc/include/asm/sm= p.h index e21d2f12b5b6..007296f160ef 100644 --- a/arch/openrisc/include/asm/smp.h +++ b/arch/openrisc/include/asm/smp.h @@ -20,7 +20,8 @@ extern void smp_init_cpus(void); extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); =20 -extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned i= nt)); +extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned i= nt), + unsigned int irq); extern void handle_IPI(unsigned int ipi_msg); =20 #endif /* __ASM_OPENRISC_SMP_H */ diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c index 86da4bc5ee0b..040ca201b692 100644 --- a/arch/openrisc/kernel/smp.c +++ b/arch/openrisc/kernel/smp.c @@ -13,6 +13,7 @@ =20 #include #include +#include #include #include #include @@ -25,6 +26,7 @@ =20 asmlinkage __init void secondary_start_kernel(void); =20 +static unsigned int ipi_irq __ro_after_init; static void (*smp_cross_call)(const struct cpumask *, unsigned int); =20 unsigned long secondary_release =3D -1; @@ -39,6 +41,14 @@ enum ipi_msg_type { =20 static DEFINE_SPINLOCK(boot_lock); =20 +static void or1k_ipi_enable(void) +{ + if (WARN_ON_ONCE(!ipi_irq)) + return; + + enable_percpu_irq(ipi_irq, 0); +} + static void boot_secondary(unsigned int cpu, struct task_struct *idle) { /* @@ -136,6 +146,7 @@ asmlinkage __init void secondary_start_kernel(void) complete(&cpu_running); =20 synchronise_count_slave(cpu); + or1k_ipi_enable(); set_cpu_online(cpu, true); =20 local_irq_enable(); @@ -195,9 +206,18 @@ void smp_send_stop(void) smp_call_function(stop_this_cpu, NULL, 0); } =20 -void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned= int)) +void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned= int), + unsigned int irq) { + if (WARN_ON(ipi_irq)) + return; + smp_cross_call =3D fn; + + ipi_irq =3D irq; + + /* Enabled IPIs for boot CPU immediately */ + or1k_ipi_enable(); } =20 void arch_send_call_function_single_ipi(int cpu) diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c index e66ef4373b1e..f0e0b435bb1d 100644 --- a/drivers/irqchip/irq-ompic.c +++ b/drivers/irqchip/irq-ompic.c @@ -84,6 +84,8 @@ DEFINE_PER_CPU(unsigned long, ops); =20 static void __iomem *ompic_base; =20 +static DEFINE_PER_CPU_READ_MOSTLY(int, ipi_dummy_dev); + static inline u32 ompic_readreg(void __iomem *base, loff_t offset) { return ioread32be(base + offset); @@ -183,12 +185,17 @@ static int __init ompic_of_init(struct device_node *n= ode, goto out_unmap; } =20 - ret =3D request_irq(irq, ompic_ipi_handler, IRQF_PERCPU, - "ompic_ipi", NULL); - if (ret) + irq_set_percpu_devid(irq); + ret =3D request_percpu_irq(irq, ompic_ipi_handler, "ompic_ipi", + &ipi_dummy_dev); + + if (ret) { + pr_err("ompic: failed to request irq %d, error: %d", + irq, ret); goto out_irq_disp; + } =20 - set_smp_cross_call(ompic_raise_softirq); + set_smp_cross_call(ompic_raise_softirq, irq); =20 return 0; =20 diff --git a/drivers/irqchip/irq-or1k-pic.c b/drivers/irqchip/irq-or1k-pic.c index 48126067c54b..73dc99c71d40 100644 --- a/drivers/irqchip/irq-or1k-pic.c +++ b/drivers/irqchip/irq-or1k-pic.c @@ -118,11 +118,36 @@ static void or1k_pic_handle_irq(struct pt_regs *regs) generic_handle_domain_irq(root_domain, irq); } =20 +/* + * The OR1K PIC is a cpu-local interrupt controller and does not distingui= sh or + * use distinct irq number ranges for per-cpu event interrupts (IPI). Since + * information to determine whether a particular irq number should be trea= ted as + * per-cpu is not available at mapping time, we use a wrapper handler func= tion + * which chooses the right handler at runtime based on whether IRQF_PERCPU= was + * used when requesting the irq. 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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47a8f6e58c1sm140532455e9.12.2025.12.14.10.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Dec 2025 10:02:25 -0800 (PST) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonas Bonn , Stefan Kristiansson , Masahiro Yamada , devicetree@vger.kernel.org Subject: [PATCH 4/5] openrisc: dts: Split simple smp dts to dts and dtsi Date: Sun, 14 Dec 2025 18:01:44 +0000 Message-ID: <20251214180158.3955285-5-shorne@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251214180158.3955285-1-shorne@gmail.com> References: <20251214180158.3955285-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Split out the common memory, CPU and PIC definitions of the simple SMP system to a DTSI file which we will later use for our De0 Nano multicore board device tree. We also take this opportunity to swich underscores to dashes as that seems to be the more common convention for DTS files. Signed-off-by: Stafford Horne --- arch/openrisc/boot/dts/simple-smp.dts | 25 +++++++++++++++++++ .../dts/{simple_smp.dts =3D> simple-smp.dtsi} | 12 ++++----- arch/openrisc/configs/simple_smp_defconfig | 2 +- 3 files changed, 32 insertions(+), 7 deletions(-) create mode 100644 arch/openrisc/boot/dts/simple-smp.dts rename arch/openrisc/boot/dts/{simple_smp.dts =3D> simple-smp.dtsi} (89%) diff --git a/arch/openrisc/boot/dts/simple-smp.dts b/arch/openrisc/boot/dts= /simple-smp.dts new file mode 100644 index 000000000000..174c2613c419 --- /dev/null +++ b/arch/openrisc/boot/dts/simple-smp.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "simple_smp.dtsi" + +/ { + model =3D "Simple SMP Board"; +}; + +&cpu0 { + clock-frequency =3D <20000000>; +}; + +&cpu1 { + clock-frequency =3D <20000000>; +}; + +&serial0 { + clock-frequency =3D <20000000>; +}; + +&enet0 { + status =3D "okay"; +}; diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts= /simple-smp.dtsi similarity index 89% rename from arch/openrisc/boot/dts/simple_smp.dts rename to arch/openrisc/boot/dts/simple-smp.dtsi index 71af0e117bfe..92770bb6fcf7 100644 --- a/arch/openrisc/boot/dts/simple_smp.dts +++ b/arch/openrisc/boot/dts/simple-smp.dtsi @@ -1,4 +1,3 @@ -/dts-v1/; / { compatible =3D "opencores,or1ksim"; #address-cells =3D <1>; @@ -22,15 +21,15 @@ memory@0 { cpus { #address-cells =3D <1>; #size-cells =3D <0>; - cpu@0 { + cpu0: cpu@0 { compatible =3D "opencores,or1200-rtlsvn481"; reg =3D <0>; - clock-frequency =3D <20000000>; + clock-frequency =3D <0>; }; - cpu@1 { + cpu1: cpu@1 { compatible =3D "opencores,or1200-rtlsvn481"; reg =3D <1>; - clock-frequency =3D <20000000>; + clock-frequency =3D <0>; }; }; =20 @@ -57,7 +56,7 @@ serial0: serial@90000000 { compatible =3D "opencores,uart16550-rtlsvn105", "ns16550a"; reg =3D <0x90000000 0x100>; interrupts =3D <2>; - clock-frequency =3D <20000000>; + clock-frequency =3D <0>; }; =20 enet0: ethoc@92000000 { @@ -65,5 +64,6 @@ enet0: ethoc@92000000 { reg =3D <0x92000000 0x800>; interrupts =3D <4>; big-endian; + status =3D "disabled"; }; }; diff --git a/arch/openrisc/configs/simple_smp_defconfig b/arch/openrisc/con= figs/simple_smp_defconfig index 6008e824d31c..db77c795225e 100644 --- a/arch/openrisc/configs/simple_smp_defconfig +++ b/arch/openrisc/configs/simple_smp_defconfig @@ -20,7 +20,7 @@ CONFIG_SLUB=3Dy CONFIG_SLUB_TINY=3Dy CONFIG_MODULES=3Dy # CONFIG_BLOCK is not set -CONFIG_BUILTIN_DTB_NAME=3D"simple_smp" +CONFIG_BUILTIN_DTB_NAME=3D"simple-smp" CONFIG_SMP=3Dy CONFIG_HZ_100=3Dy CONFIG_OPENRISC_HAVE_SHADOW_GPRS=3Dy --=20 2.51.0 From nobody Tue Dec 16 07:34:18 2025 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9BAD2D8DD0 for ; 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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-430f280cf05sm9817368f8f.7.2025.12.14.10.02.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Dec 2025 10:02:31 -0800 (PST) From: Stafford Horne To: LKML Cc: Linux OpenRISC , Stafford Horne , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonas Bonn , Stefan Kristiansson , devicetree@vger.kernel.org Subject: [PATCH 5/5] openrisc: dts: Add de0 nano multicore config and devicetree Date: Sun, 14 Dec 2025 18:01:45 +0000 Message-ID: <20251214180158.3955285-6-shorne@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251214180158.3955285-1-shorne@gmail.com> References: <20251214180158.3955285-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a multicore configuration for the Terasic de0 nano FPGA development board. This SoC runs 2 OpenRISC CPUs at 50Mhz with 32MB ram, UART for console and GPIOs for LEDs. This FPGA SoC is based on the simple-smp reference board and brings in devices from the de0 nano common DTSI file. A default config is added that brings together the device tree and driver setup. Link: https://github.com/stffrdhrn/de0_nano-multicore Signed-off-by: Stafford Horne --- arch/openrisc/boot/dts/de0-nano-multicore.dts | 25 +++++ .../configs/de0_nano_multicore_defconfig | 92 +++++++++++++++++++ 2 files changed, 117 insertions(+) create mode 100644 arch/openrisc/boot/dts/de0-nano-multicore.dts create mode 100644 arch/openrisc/configs/de0_nano_multicore_defconfig diff --git a/arch/openrisc/boot/dts/de0-nano-multicore.dts b/arch/openrisc/= boot/dts/de0-nano-multicore.dts new file mode 100644 index 000000000000..b6cf286afaa4 --- /dev/null +++ b/arch/openrisc/boot/dts/de0-nano-multicore.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include + +/dts-v1/; + +#include "simple-smp.dtsi" +#include "de0-nano-common.dtsi" + +/ { + model =3D "Terasic DE0 Nano - Multicore"; +}; + +&cpu0 { + clock-frequency =3D <50000000>; +}; + +&cpu1 { + clock-frequency =3D <50000000>; +}; + +&serial0 { + clock-frequency =3D <50000000>; +}; diff --git a/arch/openrisc/configs/de0_nano_multicore_defconfig b/arch/open= risc/configs/de0_nano_multicore_defconfig new file mode 100644 index 000000000000..d33b1226e09c --- /dev/null +++ b/arch/openrisc/configs/de0_nano_multicore_defconfig @@ -0,0 +1,92 @@ +CONFIG_LOCALVERSION=3D"-de0nano-smp" +CONFIG_SYSVIPC=3Dy +CONFIG_POSIX_MQUEUE=3Dy +CONFIG_NO_HZ=3Dy +CONFIG_LOG_BUF_SHIFT=3D14 +CONFIG_BLK_DEV_INITRD=3Dy +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_EXPERT=3Dy +# CONFIG_EPOLL is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +CONFIG_KALLSYMS_ALL=3Dy +CONFIG_DCACHE_WRITETHROUGH=3Dy +CONFIG_BUILTIN_DTB_NAME=3D"de0-nano-multicore" +CONFIG_OPENRISC_HAVE_INST_CMOV=3Dy +CONFIG_SMP=3Dy +CONFIG_HZ_100=3Dy +CONFIG_JUMP_LABEL=3Dy +# CONFIG_BLOCK is not set +CONFIG_SLUB_TINY=3Dy +# CONFIG_COMPAT_BRK is not set +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_NET=3Dy +CONFIG_PACKET=3Dy +CONFIG_UNIX=3Dy +CONFIG_UNIX_DIAG=3Dy +CONFIG_INET=3Dy +CONFIG_IP_MULTICAST=3Dy +CONFIG_TCP_CONG_ADVANCED=3Dy +# CONFIG_TCP_CONG_BIC is not set +# CONFIG_TCP_CONG_CUBIC is not set +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=3Dy +CONFIG_DEVTMPFS_MOUNT=3Dy +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +CONFIG_NETDEVICES=3Dy +CONFIG_ETHOC=3Dy +CONFIG_MICREL_PHY=3Dy +# CONFIG_WLAN is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=3Dy +CONFIG_SERIAL_8250_CONSOLE=3Dy +CONFIG_SERIAL_OF_PLATFORM=3Dy +# CONFIG_HW_RANDOM is not set +CONFIG_GPIO_SYSFS=3Dy +# CONFIG_GPIO_CDEV_V1 is not set +CONFIG_GPIO_GENERIC_PLATFORM=3Dy +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_NEW_LEDS=3Dy +CONFIG_LEDS_CLASS=3Dy +CONFIG_LEDS_GPIO=3Dy +CONFIG_LEDS_TRIGGERS=3Dy +CONFIG_LEDS_TRIGGER_TIMER=3Dy +CONFIG_LEDS_TRIGGER_ONESHOT=3Dy +CONFIG_LEDS_TRIGGER_HEARTBEAT=3Dy +CONFIG_LEDS_TRIGGER_CPU=3Dy +CONFIG_LEDS_TRIGGER_ACTIVITY=3Dy +CONFIG_LEDS_TRIGGER_GPIO=3Dy +CONFIG_LEDS_TRIGGER_DEFAULT_ON=3Dy +CONFIG_LEDS_TRIGGER_TRANSIENT=3Dy +CONFIG_LEDS_TRIGGER_PANIC=3Dy +CONFIG_LEDS_TRIGGER_NETDEV=3Dy +CONFIG_LEDS_TRIGGER_PATTERN=3Dy +CONFIG_LEDS_TRIGGER_TTY=3Dy +# CONFIG_DNOTIFY is not set +CONFIG_TMPFS=3Dy +CONFIG_NFS_FS=3Dy +CONFIG_XZ_DEC=3Dy +CONFIG_PRINTK_TIME=3Dy +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=3Dy +CONFIG_GDB_SCRIPTS=3Dy +CONFIG_VMLINUX_MAP=3Dy +CONFIG_HARDLOCKUP_DETECTOR=3Dy +CONFIG_WQ_WATCHDOG=3Dy +CONFIG_WQ_CPU_INTENSIVE_REPORT=3Dy +CONFIG_STACKTRACE=3Dy +CONFIG_RCU_CPU_STALL_CPUTIME=3Dy +# CONFIG_RCU_TRACE is not set --=20 2.51.0