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Sun, 14 Dec 2025 13:03:45 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D424E20040; Sun, 14 Dec 2025 13:03:44 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 42F8E20043; Sun, 14 Dec 2025 13:03:38 +0000 (GMT) Received: from li-1a3e774c-28e4-11b2-a85c-acc9f2883e29.ibm.com.com (unknown [9.124.210.21]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Sun, 14 Dec 2025 13:03:38 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, thuth@redhat.com, sshegde@linux.ibm.com, charlie@rivosinc.com, macro@orcam.me.uk, akpm@linux-foundation.org, ldv@strace.io, deller@gmx.de, ankur.a.arora@oracle.com, segher@kernel.crashing.org, tglx@linutronix.de, thomas.weissschuh@linutronix.de, peterz@infradead.org, menglong8.dong@gmail.com, bigeasy@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, atrajeev@linux.vnet.ibm.com, mark.barnett@arm.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/8] powerpc: rename arch_irq_disabled_regs Date: Sun, 14 Dec 2025 18:32:37 +0530 Message-ID: <20251214130245.43664-2-mkchauras@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251214130245.43664-1-mkchauras@linux.ibm.com> References: <20251214130245.43664-1-mkchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=V/JwEOni c=1 sm=1 tr=0 ts=693eb5b6 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=8txWmKPpaVdEF_iBmVcA:9 X-Proofpoint-GUID: nOtvlvCYQ1mM4l2BIZKwbAbgfsGhUPgU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEzMDAyMyBTYWx0ZWRfXxHlQlHZP611L Jkxri/FOrGx4HTcP5qhYAwCqDluNSqApA09cf+HUgSPrGt6qgu54b85a8cwGRk8XN73KJbCFkEz 3mzuABf6aruPHCoU6XoZXsUmQPqjN/f0GmjnhvqhSABda/iHO1aXnHkMpcniMe2tlITcyzUzR/z 70bPQljm6oMupeJp2Shj5uMcLM5LL+GoUmo1rjpHXLQffvA3lK64ZZtGnZTzuz7LeUUjCbxG62f 7wV1oKYpq81hmamNCTKvTm0MwPaBgZxAPEEXu+X5EJ3rEBeg2YJ0tcVyBBpIkviUF50+bdBc6rY F0EO/uEodXweOPiLZdXPov3ar/OZtuBsm5AL0xMxQe3ECZBRuKOv3i6CyVSv2d/KB2CBDVy+Fo1 Nt8zsaXvoKflMn+2CYKMPVJ6dHmeYQ== X-Proofpoint-ORIG-GUID: 9aeGBx41lxahiGOT8rMQ31JC7RO2Gapj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-14_03,2025-12-11_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 bulkscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512130023 Content-Type: text/plain; charset="utf-8" From: Mukesh Kumar Chaurasiya Rename arch_irq_disabled_regs() to regs_irqs_disabled() to align with the naming used in the generic irqentry framework. This makes the function available for use both in the PowerPC architecture code and in the common entry/exit paths shared with other architectures. This is a preparatory change for enabling the generic irqentry framework on PowerPC. Signed-off-by: Mukesh Kumar Chaurasiya Reviewed-by: Shrikanth Hegde --- arch/powerpc/include/asm/hw_irq.h | 4 ++-- arch/powerpc/include/asm/interrupt.h | 16 ++++++++-------- arch/powerpc/kernel/interrupt.c | 4 ++-- arch/powerpc/kernel/syscall.c | 2 +- arch/powerpc/kernel/traps.c | 2 +- arch/powerpc/kernel/watchdog.c | 2 +- arch/powerpc/perf/core-book3s.c | 2 +- 7 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/h= w_irq.h index 1078ba88efaf..8dfe36b442a5 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h @@ -393,7 +393,7 @@ static inline void do_hard_irq_enable(void) __hard_irq_enable(); } =20 -static inline bool arch_irq_disabled_regs(struct pt_regs *regs) +static inline bool regs_irqs_disabled(struct pt_regs *regs) { return (regs->softe & IRQS_DISABLED); } @@ -466,7 +466,7 @@ static inline bool arch_irqs_disabled(void) =20 #define hard_irq_disable() arch_local_irq_disable() =20 -static inline bool arch_irq_disabled_regs(struct pt_regs *regs) +static inline bool regs_irqs_disabled(struct pt_regs *regs) { return !(regs->msr & MSR_EE); } diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/as= m/interrupt.h index eb0e4a20b818..0e2cddf8bd21 100644 --- a/arch/powerpc/include/asm/interrupt.h +++ b/arch/powerpc/include/asm/interrupt.h @@ -172,7 +172,7 @@ static inline void interrupt_enter_prepare(struct pt_re= gs *regs) /* Enable MSR[RI] early, to support kernel SLB and hash faults */ #endif =20 - if (!arch_irq_disabled_regs(regs)) + if (!regs_irqs_disabled(regs)) trace_hardirqs_off(); =20 if (user_mode(regs)) { @@ -192,11 +192,11 @@ static inline void interrupt_enter_prepare(struct pt_= regs *regs) CT_WARN_ON(ct_state() !=3D CT_STATE_KERNEL && ct_state() !=3D CT_STATE_IDLE); INT_SOFT_MASK_BUG_ON(regs, is_implicit_soft_masked(regs)); - INT_SOFT_MASK_BUG_ON(regs, arch_irq_disabled_regs(regs) && - search_kernel_restart_table(regs->nip)); + INT_SOFT_MASK_BUG_ON(regs, regs_irqs_disabled(regs) && + search_kernel_restart_table(regs->nip)); } - INT_SOFT_MASK_BUG_ON(regs, !arch_irq_disabled_regs(regs) && - !(regs->msr & MSR_EE)); + INT_SOFT_MASK_BUG_ON(regs, !regs_irqs_disabled(regs) && + !(regs->msr & MSR_EE)); =20 booke_restore_dbcr0(); } @@ -298,7 +298,7 @@ static inline void interrupt_nmi_enter_prepare(struct p= t_regs *regs, struct inte * Adjust regs->softe to be soft-masked if it had not been * reconcied (e.g., interrupt entry with MSR[EE]=3D0 but softe * not yet set disabled), or if it was in an implicit soft - * masked state. This makes arch_irq_disabled_regs(regs) + * masked state. This makes regs_irqs_disabled(regs) * behave as expected. */ regs->softe =3D IRQS_ALL_DISABLED; @@ -372,7 +372,7 @@ static inline void interrupt_nmi_exit_prepare(struct pt= _regs *regs, struct inter =20 #ifdef CONFIG_PPC64 #ifdef CONFIG_PPC_BOOK3S - if (arch_irq_disabled_regs(regs)) { + if (regs_irqs_disabled(regs)) { unsigned long rst =3D search_kernel_restart_table(regs->nip); if (rst) regs_set_return_ip(regs, rst); @@ -661,7 +661,7 @@ void replay_soft_interrupts(void); =20 static inline void interrupt_cond_local_irq_enable(struct pt_regs *regs) { - if (!arch_irq_disabled_regs(regs)) + if (!regs_irqs_disabled(regs)) local_irq_enable(); } =20 diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrup= t.c index e0c681d0b076..0d8fd47049a1 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -347,7 +347,7 @@ notrace unsigned long interrupt_exit_user_prepare(struc= t pt_regs *regs) unsigned long ret; =20 BUG_ON(regs_is_unrecoverable(regs)); - BUG_ON(arch_irq_disabled_regs(regs)); + BUG_ON(regs_irqs_disabled(regs)); CT_WARN_ON(ct_state() =3D=3D CT_STATE_USER); =20 /* @@ -396,7 +396,7 @@ notrace unsigned long interrupt_exit_kernel_prepare(str= uct pt_regs *regs) =20 local_irq_disable(); =20 - if (!arch_irq_disabled_regs(regs)) { + if (!regs_irqs_disabled(regs)) { /* Returning to a kernel context with local irqs enabled. */ WARN_ON_ONCE(!(regs->msr & MSR_EE)); again: diff --git a/arch/powerpc/kernel/syscall.c b/arch/powerpc/kernel/syscall.c index be159ad4b77b..9f03a6263fb4 100644 --- a/arch/powerpc/kernel/syscall.c +++ b/arch/powerpc/kernel/syscall.c @@ -32,7 +32,7 @@ notrace long system_call_exception(struct pt_regs *regs, = unsigned long r0) =20 BUG_ON(regs_is_unrecoverable(regs)); BUG_ON(!user_mode(regs)); - BUG_ON(arch_irq_disabled_regs(regs)); + BUG_ON(regs_irqs_disabled(regs)); =20 #ifdef CONFIG_PPC_PKEY if (mmu_has_feature(MMU_FTR_PKEY)) { diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index cb8e9357383e..629f2a2d4780 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -1956,7 +1956,7 @@ DEFINE_INTERRUPT_HANDLER_RAW(performance_monitor_exce= ption) * prevent hash faults on user addresses when reading callchains (and * looks better from an irq tracing perspective). */ - if (IS_ENABLED(CONFIG_PPC64) && unlikely(arch_irq_disabled_regs(regs))) + if (IS_ENABLED(CONFIG_PPC64) && unlikely(regs_irqs_disabled(regs))) performance_monitor_exception_nmi(regs); else performance_monitor_exception_async(regs); diff --git a/arch/powerpc/kernel/watchdog.c b/arch/powerpc/kernel/watchdog.c index 2429cb1c7baa..6111cbbde069 100644 --- a/arch/powerpc/kernel/watchdog.c +++ b/arch/powerpc/kernel/watchdog.c @@ -373,7 +373,7 @@ DEFINE_INTERRUPT_HANDLER_NMI(soft_nmi_interrupt) u64 tb; =20 /* should only arrive from kernel, with irqs disabled */ - WARN_ON_ONCE(!arch_irq_disabled_regs(regs)); + WARN_ON_ONCE(!regs_irqs_disabled(regs)); =20 if (!cpumask_test_cpu(cpu, &wd_cpus_enabled)) return 0; diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3= s.c index 8b0081441f85..f7518b7e3055 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -2482,7 +2482,7 @@ static void __perf_event_interrupt(struct pt_regs *re= gs) * will trigger a PMI after waking up from idle. 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Sun, 14 Dec 2025 13:03:44 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, thuth@redhat.com, sshegde@linux.ibm.com, charlie@rivosinc.com, macro@orcam.me.uk, akpm@linux-foundation.org, ldv@strace.io, deller@gmx.de, ankur.a.arora@oracle.com, segher@kernel.crashing.org, tglx@linutronix.de, thomas.weissschuh@linutronix.de, peterz@infradead.org, menglong8.dong@gmail.com, bigeasy@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, atrajeev@linux.vnet.ibm.com, mark.barnett@arm.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/8] powerpc: Prepare to build with generic entry/exit framework Date: Sun, 14 Dec 2025 18:32:38 +0530 Message-ID: <20251214130245.43664-3-mkchauras@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251214130245.43664-1-mkchauras@linux.ibm.com> References: <20251214130245.43664-1-mkchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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The following infrastructure updates are added: - Add a syscall_work field to struct thread_info to hold SYSCALL_WORK_* fl= ags. - Provide a stub implementation of arch_syscall_is_vdso_sigreturn(), returning false for now. - Introduce on_thread_stack() helper to detect if the current stack pointer lies within the task=E2=80=99s kernel stack. These additions enable later integration with the generic entry/exit infrastructure while keeping existing PowerPC behavior unchanged. No functional change is intended in this patch. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/include/asm/entry-common.h | 11 +++++++++++ arch/powerpc/include/asm/stacktrace.h | 6 ++++++ arch/powerpc/include/asm/syscall.h | 5 +++++ arch/powerpc/include/asm/thread_info.h | 1 + 4 files changed, 23 insertions(+) create mode 100644 arch/powerpc/include/asm/entry-common.h diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include= /asm/entry-common.h new file mode 100644 index 000000000000..3af16d821d07 --- /dev/null +++ b/arch/powerpc/include/asm/entry-common.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_PPC_ENTRY_COMMON_H +#define _ASM_PPC_ENTRY_COMMON_H + +#ifdef CONFIG_GENERIC_IRQ_ENTRY + +#include + +#endif /* CONFIG_GENERIC_IRQ_ENTRY */ +#endif /* _ASM_PPC_ENTRY_COMMON_H */ diff --git a/arch/powerpc/include/asm/stacktrace.h b/arch/powerpc/include/a= sm/stacktrace.h index 6149b53b3bc8..a81a9373d723 100644 --- a/arch/powerpc/include/asm/stacktrace.h +++ b/arch/powerpc/include/asm/stacktrace.h @@ -10,4 +10,10 @@ =20 void show_user_instructions(struct pt_regs *regs); =20 +static inline bool on_thread_stack(void) +{ + return !(((unsigned long)(current->stack) ^ current_stack_pointer) + & ~(THREAD_SIZE - 1)); +} + #endif /* _ASM_POWERPC_STACKTRACE_H */ diff --git a/arch/powerpc/include/asm/syscall.h b/arch/powerpc/include/asm/= syscall.h index 4b3c52ed6e9d..834fcc4f7b54 100644 --- a/arch/powerpc/include/asm/syscall.h +++ b/arch/powerpc/include/asm/syscall.h @@ -139,4 +139,9 @@ static inline int syscall_get_arch(struct task_struct *= task) else return AUDIT_ARCH_PPC64; } + +static inline bool arch_syscall_is_vdso_sigreturn(struct pt_regs *regs) +{ + return false; +} #endif /* _ASM_SYSCALL_H */ diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/= asm/thread_info.h index b0f200aba2b3..9c8270354f0b 100644 --- a/arch/powerpc/include/asm/thread_info.h +++ b/arch/powerpc/include/asm/thread_info.h @@ -57,6 +57,7 @@ struct thread_info { #ifdef CONFIG_SMP unsigned int cpu; #endif + unsigned long syscall_work; /* SYSCALL_WORK_ flags */ unsigned long local_flags; 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Sun, 14 Dec 2025 13:03:51 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, thuth@redhat.com, sshegde@linux.ibm.com, charlie@rivosinc.com, macro@orcam.me.uk, akpm@linux-foundation.org, ldv@strace.io, deller@gmx.de, ankur.a.arora@oracle.com, segher@kernel.crashing.org, tglx@linutronix.de, thomas.weissschuh@linutronix.de, peterz@infradead.org, menglong8.dong@gmail.com, bigeasy@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, atrajeev@linux.vnet.ibm.com, mark.barnett@arm.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/8] powerpc: introduce arch_enter_from_user_mode Date: Sun, 14 Dec 2025 18:32:39 +0530 Message-ID: <20251214130245.43664-4-mkchauras@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251214130245.43664-1-mkchauras@linux.ibm.com> References: <20251214130245.43664-1-mkchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEzMDAwMSBTYWx0ZWRfX0GCkjE9pRxFG HbyxLjLKjOowVskVEFsoES/GiC+ZfXHhHlnXHi+UCN8y462LMz+DzqeTbU0C+7l7TcdFVWvV5UB DaDVti1m7TvDtQe7w5xehKv8tlfTQS+djwmVsnvLEzLzGRJES2FNnT3+7WKu1TZT0e9a7t+nvah FG5bGP9iBJf8H1zV/7r5NZCa1rLohc1My2hI7GZVN9zO5z7d/+HhSF3Lz2u810RvhIWYQswQYeA m4sBOvjgY0JdIMV9/gY/S7b54Dp9cKHG4VfxVIBnnrGNLySkRrYtdD7egEnTVNTsndDTQVobovc zJARaCcR3dLe8o105aKh+E29zSP4hVt/gGwOmb/ldgaHa3Qk9ov0T57ZUBAQjEI7O+0mHMIKB84 Vx9/CgI+hjvuKqDjbWCXDz8Palo1xA== X-Proofpoint-GUID: Fn_12JMdKhLRIsMjAVSrrQea5-tm5Dh4 X-Proofpoint-ORIG-GUID: 0ieI2e7XsxJHIBYO424dMUSCtHR7bPSz X-Authority-Analysis: v=2.4 cv=Kq5AGGWN c=1 sm=1 tr=0 ts=693eb5c4 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=T-nl45EEozRawLcqnCYA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-14_03,2025-12-11_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 impostorscore=0 clxscore=1015 spamscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512130001 Content-Type: text/plain; charset="utf-8" From: Mukesh Kumar Chaurasiya Implement the arch_enter_from_user_mode() hook required by the generic entry/exit framework. This helper prepares the CPU state when entering the kernel from userspace, ensuring correct handling of KUAP/KUEP, transactional memory, and debug register state. As part of this change, move booke_load_dbcr0() from interrupt.c to interrupt.h so it can be used by the new helper without introducing cross-file dependencies. This patch contains no functional changes, it is purely preparatory for enabling the generic syscall and interrupt entry path on PowerPC. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/include/asm/entry-common.h | 97 +++++++++++++++++++++++++ arch/powerpc/include/asm/interrupt.h | 22 ++++++ arch/powerpc/kernel/interrupt.c | 22 ------ 3 files changed, 119 insertions(+), 22 deletions(-) diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include= /asm/entry-common.h index 3af16d821d07..093ece06ef79 100644 --- a/arch/powerpc/include/asm/entry-common.h +++ b/arch/powerpc/include/asm/entry-common.h @@ -5,7 +5,104 @@ =20 #ifdef CONFIG_GENERIC_IRQ_ENTRY =20 +#include +#include #include +#include + +static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) +{ + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) + BUG_ON(irq_soft_mask_return() !=3D IRQS_ALL_DISABLED); + + BUG_ON(regs_is_unrecoverable(regs)); + BUG_ON(!user_mode(regs)); + BUG_ON(regs_irqs_disabled(regs)); + +#ifdef CONFIG_PPC_PKEY + if (mmu_has_feature(MMU_FTR_PKEY) && trap_is_syscall(regs)) { + unsigned long amr, iamr; + bool flush_needed =3D false; + /* + * When entering from userspace we mostly have the AMR/IAMR + * different from kernel default values. Hence don't compare. + */ + amr =3D mfspr(SPRN_AMR); + iamr =3D mfspr(SPRN_IAMR); + regs->amr =3D amr; + regs->iamr =3D iamr; + if (mmu_has_feature(MMU_FTR_KUAP)) { + mtspr(SPRN_AMR, AMR_KUAP_BLOCKED); + flush_needed =3D true; + } + if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) { + mtspr(SPRN_IAMR, AMR_KUEP_BLOCKED); + flush_needed =3D true; + } + if (flush_needed) + isync(); + } else +#endif + kuap_assert_locked(); + + booke_restore_dbcr0(); + + account_cpu_user_entry(); + + account_stolen_time(); + + /* + * This is not required for the syscall exit path, but makes the + * stack frame look nicer. If this was initialised in the first stack + * frame, or if the unwinder was taught the first stack frame always + * returns to user with IRQS_ENABLED, this store could be avoided! + */ + irq_soft_mask_regs_set_state(regs, IRQS_ENABLED); + + /* + * If system call is called with TM active, set _TIF_RESTOREALL to + * prevent RFSCV being used to return to userspace, because POWER9 + * TM implementation has problems with this instruction returning to + * transactional state. Final register values are not relevant because + * the transaction will be aborted upon return anyway. Or in the case + * of unsupported_scv SIGILL fault, the return state does not much + * matter because it's an edge case. + */ + if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && + unlikely(MSR_TM_TRANSACTIONAL(regs->msr))) + set_bits(_TIF_RESTOREALL, ¤t_thread_info()->flags); + + /* + * If the system call was made with a transaction active, doom it and + * return without performing the system call. Unless it was an + * unsupported scv vector, in which case it's treated like an illegal + * instruction. + */ +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + if (unlikely(MSR_TM_TRANSACTIONAL(regs->msr)) && + !trap_is_unsupported_scv(regs)) { + /* Enable TM in the kernel, and disable EE (for scv) */ + hard_irq_disable(); + mtmsr(mfmsr() | MSR_TM); + + /* tabort, this dooms the transaction, nothing else */ + asm volatile(".long 0x7c00071d | ((%0) << 16)" + :: "r"(TM_CAUSE_SYSCALL | TM_CAUSE_PERSISTENT)); + + /* + * Userspace will never see the return value. Execution will + * resume after the tbegin. of the aborted transaction with the + * checkpointed register state. A context switch could occur + * or signal delivered to the process before resuming the + * doomed transaction context, but that should all be handled + * as expected. + */ + return; + } +#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ +} + +#define arch_enter_from_user_mode arch_enter_from_user_mode =20 #endif /* CONFIG_GENERIC_IRQ_ENTRY */ #endif /* _ASM_PPC_ENTRY_COMMON_H */ diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/as= m/interrupt.h index 0e2cddf8bd21..ca8a2cda9400 100644 --- a/arch/powerpc/include/asm/interrupt.h +++ b/arch/powerpc/include/asm/interrupt.h @@ -138,6 +138,28 @@ static inline void nap_adjust_return(struct pt_regs *r= egs) #endif } =20 +static inline void booke_load_dbcr0(void) +{ +#ifdef CONFIG_PPC_ADV_DEBUG_REGS + unsigned long dbcr0 =3D current->thread.debug.dbcr0; + + if (likely(!(dbcr0 & DBCR0_IDM))) + return; + + /* + * Check to see if the dbcr0 register is set up to debug. + * Use the internal debug mode bit to do this. + */ + mtmsr(mfmsr() & ~MSR_DE); + if (IS_ENABLED(CONFIG_PPC32)) { + isync(); + global_dbcr0[smp_processor_id()] =3D mfspr(SPRN_DBCR0); + } + mtspr(SPRN_DBCR0, dbcr0); + mtspr(SPRN_DBSR, -1); +#endif +} + static inline void booke_restore_dbcr0(void) { #ifdef CONFIG_PPC_ADV_DEBUG_REGS diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrup= t.c index 0d8fd47049a1..2a09ac5dabd6 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -78,28 +78,6 @@ static notrace __always_inline bool prep_irq_for_enabled= _exit(bool restartable) return true; } =20 -static notrace void booke_load_dbcr0(void) -{ -#ifdef CONFIG_PPC_ADV_DEBUG_REGS - unsigned long dbcr0 =3D current->thread.debug.dbcr0; - - if (likely(!(dbcr0 & DBCR0_IDM))) - return; - - /* - * Check to see if the dbcr0 register is set up to debug. - * Use the internal debug mode bit to do this. - */ - mtmsr(mfmsr() & ~MSR_DE); - if (IS_ENABLED(CONFIG_PPC32)) { - isync(); - global_dbcr0[smp_processor_id()] =3D mfspr(SPRN_DBCR0); - } - mtspr(SPRN_DBCR0, dbcr0); - mtspr(SPRN_DBSR, -1); -#endif -} - static notrace void check_return_regs_valid(struct pt_regs *regs) { #ifdef CONFIG_PPC_BOOK3S_64 --=20 2.52.0 From nobody Tue Dec 16 07:41:28 2025 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DD9D3770B for ; Sun, 14 Dec 2025 13:04:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.158.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765717488; cv=none; b=HPuhCYrYLqf2Lr336YCTIJbkrMJx11CIlj0Puhc3waKqljSuTckNqMOlQ/6zMOpxwT+5uOZZBMtzXcI/cdiYGJsj1TGvUPiS0YNWJYeafr9uY9wmwfW+KLslQ3zbcGhXGQXdo3wW4o95YZXtUYGSoFlW9UjtXJfVKHtABdT6TSM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765717488; c=relaxed/simple; bh=ljHJcJDo1ONSHeHEu8pyHYoCjUtWPyki+75hovWBI1A=; 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Sun, 14 Dec 2025 13:03:58 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, thuth@redhat.com, sshegde@linux.ibm.com, charlie@rivosinc.com, macro@orcam.me.uk, akpm@linux-foundation.org, ldv@strace.io, deller@gmx.de, ankur.a.arora@oracle.com, segher@kernel.crashing.org, tglx@linutronix.de, thomas.weissschuh@linutronix.de, peterz@infradead.org, menglong8.dong@gmail.com, bigeasy@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, atrajeev@linux.vnet.ibm.com, mark.barnett@arm.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/8] powerpc: Introduce syscall exit arch functions Date: Sun, 14 Dec 2025 18:32:40 +0530 Message-ID: <20251214130245.43664-5-mkchauras@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251214130245.43664-1-mkchauras@linux.ibm.com> References: <20251214130245.43664-1-mkchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEzMDAwMSBTYWx0ZWRfXzRBQESpRwMRy sm0D2roqmEbCpZq2EQsZ69K19smMR2VZajuJ8LVwUx4x3NeQXtX7LVfdwwzzaZs3en6lNS0GdWv FOm/jTXd/aGCY60eEA0jUU5ODnV84DW8iE2WH91wUQi4c8UdC7YkPhF2cjDJWu9o5K6Eux5VZhS 0kx6BpAGfesVP90eHIm4uokrZRXOVEacCYbZpew4pk8ZyGNBvC1KpF/LLIyE1yYU1NfJlyZ89CK srinjpVALouhr5MCxxeqQixXPQgbkTgBUMEvXI+CXpiMv4cb94XY0ARexSuNnBqkxm1oGvNNqyA M2ldaZL5qK7sKeAXVlnIDqOpN/fkt9YiimWVr/cEsNBn1rT6UPiIyKHZPWK4hLdGhYZGZiQhOfk EjZtw3K6zK30LXkTqNglMvVrDzkgEA== X-Proofpoint-GUID: Skk0TDzN03hjddwt9vfbVTHbN97kpPlT X-Proofpoint-ORIG-GUID: agosFuUJhXXg2hcbVYE-1gbfCL-T4_ty X-Authority-Analysis: v=2.4 cv=Kq5AGGWN c=1 sm=1 tr=0 ts=693eb5cb cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=1zgF-uAQnxabbVpijEgA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-14_03,2025-12-11_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 impostorscore=0 clxscore=1015 spamscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512130001 Content-Type: text/plain; charset="utf-8" From: Mukesh Kumar Chaurasiya Add PowerPC-specific implementations of the generic syscall exit hooks used by the generic entry/exit framework: - arch_exit_to_user_mode_work_prepare() - arch_exit_to_user_mode_work() These helpers handle user state restoration when returning from the kernel to userspace, including FPU/VMX/VSX state, transactional memory, KUAP restore, and per-CPU accounting. Additionally, move check_return_regs_valid() from interrupt.c to interrupt.h so it can be shared by the new entry/exit logic, and add arch_do_signal_or_restart() for use with the generic entry flow. No functional change is intended with this patch. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/include/asm/entry-common.h | 49 +++++++++++++++ arch/powerpc/include/asm/interrupt.h | 82 +++++++++++++++++++++++++ arch/powerpc/kernel/interrupt.c | 81 ------------------------ arch/powerpc/kernel/signal.c | 14 +++++ 4 files changed, 145 insertions(+), 81 deletions(-) diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include= /asm/entry-common.h index 093ece06ef79..e8ebd42a4e6d 100644 --- a/arch/powerpc/include/asm/entry-common.h +++ b/arch/powerpc/include/asm/entry-common.h @@ -8,6 +8,7 @@ #include #include #include +#include #include =20 static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) @@ -104,5 +105,53 @@ static __always_inline void arch_enter_from_user_mode(= struct pt_regs *regs) =20 #define arch_enter_from_user_mode arch_enter_from_user_mode =20 +static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, + unsigned long ti_work) +{ + unsigned long mathflags; + + if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && IS_ENABLED(CONFIG_PPC_FPU)) { + if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && + unlikely((ti_work & _TIF_RESTORE_TM))) { + restore_tm_state(regs); + } else { + mathflags =3D MSR_FP; + + if (cpu_has_feature(CPU_FTR_VSX)) + mathflags |=3D MSR_VEC | MSR_VSX; + else if (cpu_has_feature(CPU_FTR_ALTIVEC)) + mathflags |=3D MSR_VEC; + + /* + * If userspace MSR has all available FP bits set, + * then they are live and no need to restore. If not, + * it means the regs were given up and restore_math + * may decide to restore them (to avoid taking an FP + * fault). + */ + if ((regs->msr & mathflags) !=3D mathflags) + restore_math(regs); + } + } + + check_return_regs_valid(regs); +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + local_paca->tm_scratch =3D regs->msr; +#endif + /* Restore user access locks last */ + kuap_user_restore(regs); +} + +#define arch_exit_to_user_mode_prepare arch_exit_to_user_mode_prepare + +static __always_inline void arch_exit_to_user_mode(void) +{ + booke_load_dbcr0(); + + account_cpu_user_exit(); +} + +#define arch_exit_to_user_mode arch_exit_to_user_mode + #endif /* CONFIG_GENERIC_IRQ_ENTRY */ #endif /* _ASM_PPC_ENTRY_COMMON_H */ diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/as= m/interrupt.h index ca8a2cda9400..77ff8e33f8cd 100644 --- a/arch/powerpc/include/asm/interrupt.h +++ b/arch/powerpc/include/asm/interrupt.h @@ -68,6 +68,8 @@ =20 #include #include +#include /* for show_regs */ + #include #include #include @@ -172,6 +174,86 @@ static inline void booke_restore_dbcr0(void) #endif } =20 +static inline void check_return_regs_valid(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC_BOOK3S_64 + unsigned long trap, srr0, srr1; + static bool warned; + u8 *validp; + char *h; + + if (trap_is_scv(regs)) + return; + + trap =3D TRAP(regs); + // EE in HV mode sets HSRRs like 0xea0 + if (cpu_has_feature(CPU_FTR_HVMODE) && trap =3D=3D INTERRUPT_EXTERNAL) + trap =3D 0xea0; + + switch (trap) { + case 0x980: + case INTERRUPT_H_DATA_STORAGE: + case 0xe20: + case 0xe40: + case INTERRUPT_HMI: + case 0xe80: + case 0xea0: + case INTERRUPT_H_FAC_UNAVAIL: + case 0x1200: + case 0x1500: + case 0x1600: + case 0x1800: + validp =3D &local_paca->hsrr_valid; + if (!READ_ONCE(*validp)) + return; + + srr0 =3D mfspr(SPRN_HSRR0); + srr1 =3D mfspr(SPRN_HSRR1); + h =3D "H"; + + break; + default: + validp =3D &local_paca->srr_valid; + if (!READ_ONCE(*validp)) + return; + + srr0 =3D mfspr(SPRN_SRR0); + srr1 =3D mfspr(SPRN_SRR1); + h =3D ""; + break; + } + + if (srr0 =3D=3D regs->nip && srr1 =3D=3D regs->msr) + return; + + /* + * A NMI / soft-NMI interrupt may have come in after we found + * srr_valid and before the SRRs are loaded. The interrupt then + * comes in and clobbers SRRs and clears srr_valid. Then we load + * the SRRs here and test them above and find they don't match. + * + * Test validity again after that, to catch such false positives. + * + * This test in general will have some window for false negatives + * and may not catch and fix all such cases if an NMI comes in + * later and clobbers SRRs without clearing srr_valid, but hopefully + * such things will get caught most of the time, statistically + * enough to be able to get a warning out. + */ + if (!READ_ONCE(*validp)) + return; + + if (!data_race(warned)) { + data_race(warned =3D true); + pr_warn("%sSRR0 was: %lx should be: %lx\n", h, srr0, regs->nip); + pr_warn("%sSRR1 was: %lx should be: %lx\n", h, srr1, regs->msr); + show_regs(regs); + } + + WRITE_ONCE(*validp, 0); /* fixup */ +#endif +} + static inline void interrupt_enter_prepare(struct pt_regs *regs) { #ifdef CONFIG_PPC64 diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrup= t.c index 2a09ac5dabd6..f53d432f6087 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -4,7 +4,6 @@ #include #include #include -#include /* for show_regs */ =20 #include #include @@ -78,86 +77,6 @@ static notrace __always_inline bool prep_irq_for_enabled= _exit(bool restartable) return true; } =20 -static notrace void check_return_regs_valid(struct pt_regs *regs) -{ -#ifdef CONFIG_PPC_BOOK3S_64 - unsigned long trap, srr0, srr1; - static bool warned; - u8 *validp; - char *h; - - if (trap_is_scv(regs)) - return; - - trap =3D TRAP(regs); - // EE in HV mode sets HSRRs like 0xea0 - if (cpu_has_feature(CPU_FTR_HVMODE) && trap =3D=3D INTERRUPT_EXTERNAL) - trap =3D 0xea0; - - switch (trap) { - case 0x980: - case INTERRUPT_H_DATA_STORAGE: - case 0xe20: - case 0xe40: - case INTERRUPT_HMI: - case 0xe80: - case 0xea0: - case INTERRUPT_H_FAC_UNAVAIL: - case 0x1200: - case 0x1500: - case 0x1600: - case 0x1800: - validp =3D &local_paca->hsrr_valid; - if (!READ_ONCE(*validp)) - return; - - srr0 =3D mfspr(SPRN_HSRR0); - srr1 =3D mfspr(SPRN_HSRR1); - h =3D "H"; - - break; - default: - validp =3D &local_paca->srr_valid; - if (!READ_ONCE(*validp)) - return; - - srr0 =3D mfspr(SPRN_SRR0); - srr1 =3D mfspr(SPRN_SRR1); - h =3D ""; - break; - } - - if (srr0 =3D=3D regs->nip && srr1 =3D=3D regs->msr) - return; - - /* - * A NMI / soft-NMI interrupt may have come in after we found - * srr_valid and before the SRRs are loaded. The interrupt then - * comes in and clobbers SRRs and clears srr_valid. Then we load - * the SRRs here and test them above and find they don't match. - * - * Test validity again after that, to catch such false positives. - * - * This test in general will have some window for false negatives - * and may not catch and fix all such cases if an NMI comes in - * later and clobbers SRRs without clearing srr_valid, but hopefully - * such things will get caught most of the time, statistically - * enough to be able to get a warning out. - */ - if (!READ_ONCE(*validp)) - return; - - if (!data_race(warned)) { - data_race(warned =3D true); - printk("%sSRR0 was: %lx should be: %lx\n", h, srr0, regs->nip); - printk("%sSRR1 was: %lx should be: %lx\n", h, srr1, regs->msr); - show_regs(regs); - } - - WRITE_ONCE(*validp, 0); /* fixup */ -#endif -} - static notrace unsigned long interrupt_exit_user_prepare_main(unsigned long ret, struct pt_regs *regs) { diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c index aa17e62f3754..719930cf4ae1 100644 --- a/arch/powerpc/kernel/signal.c +++ b/arch/powerpc/kernel/signal.c @@ -22,6 +22,11 @@ =20 #include "signal.h" =20 +/* This will be removed */ +#ifdef CONFIG_GENERIC_ENTRY +#include +#endif /* CONFIG_GENERIC_ENTRY */ + #ifdef CONFIG_VSX unsigned long copy_fpr_to_user(void __user *to, struct task_struct *task) @@ -368,3 +373,12 @@ void signal_fault(struct task_struct *tsk, struct pt_r= egs *regs, printk_ratelimited(regs->msr & MSR_64BIT ? fm64 : fm32, tsk->comm, task_pid_nr(tsk), where, ptr, regs->nip, regs->link); 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Sun, 14 Dec 2025 13:04:05 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, thuth@redhat.com, sshegde@linux.ibm.com, charlie@rivosinc.com, macro@orcam.me.uk, akpm@linux-foundation.org, ldv@strace.io, deller@gmx.de, ankur.a.arora@oracle.com, segher@kernel.crashing.org, tglx@linutronix.de, thomas.weissschuh@linutronix.de, peterz@infradead.org, menglong8.dong@gmail.com, bigeasy@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, atrajeev@linux.vnet.ibm.com, mark.barnett@arm.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/8] powerpc: add exit_flags field in pt_regs Date: Sun, 14 Dec 2025 18:32:41 +0530 Message-ID: <20251214130245.43664-6-mkchauras@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251214130245.43664-1-mkchauras@linux.ibm.com> References: <20251214130245.43664-1-mkchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=V/JwEOni c=1 sm=1 tr=0 ts=693eb5d1 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=mnynasnECEr2HgeGZQUA:9 X-Proofpoint-GUID: WxMgjE8SmAVb8RL1zWV9P8CcNEWmHv7o X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEzMDAyMyBTYWx0ZWRfX94Eyw74eG1pX iaXGsfU/i5O0miSl+o3lde+r4SRWibLz2lKCqnOJjSOM0dgiMMw8I7VuEpHi5l43IAIPqXsp1xh iCAFOc1ioCavsL310vj6f73RB5EOr5buE/bK3oyl7tYH+BxNw5ytJkPrHK3B5ucIbi9MYqr9YE9 MjrnePqAyNf116SPx1+28Aeb9sGK4uf45RDGJEeKO1cwd7mHMbVYkxfVjiONA6pYoDem1CjhoII fumsUPyMQs86LW8uVV5jFFryWPgynTbw2h6rWYUbWbpjakm9Z/r3o7fwx/cFOCQV+CPZGT6bjy+ h6qBhIrcOhg95B8Q6os7AfctYiRbKOis6TkCbMh/89DxeMe7sLipXu8oNMnvqP9mREiQjMg+Uxa XO/6mKmOfCB5XTOFoW3TGqxdtJBkNw== X-Proofpoint-ORIG-GUID: lpPw985BP5J-rwiiBnV-e3rkFpIPpVWf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-14_03,2025-12-11_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 bulkscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512130023 Content-Type: text/plain; charset="utf-8" From: Mukesh Kumar Chaurasiya Add a new field `exit_flags` in the pt_regs structure. This field will hold the flags set during interrupt or syscall execution that are required during exit to user mode. Specifically, the `TIF_RESTOREALL` flag, stored in this field, helps the exit routine determine if any NVGPRs were modified and need to be restored before returning to userspace. This addition ensures a clean and architecture-specific mechanism to track per-syscall or per-interrupt state transitions related to register restore. Changes: - Add `exit_flags` and `__pt_regs_pad` to maintain 16-byte stack alignment - Update asm-offsets.c and ptrace.c for offset and validation - Update PT_* constants in uapi header to reflect the new layout Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/include/asm/ptrace.h | 3 +++ arch/powerpc/include/uapi/asm/ptrace.h | 14 +++++++++----- arch/powerpc/kernel/asm-offsets.c | 1 + arch/powerpc/kernel/ptrace/ptrace.c | 1 + 4 files changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/p= trace.h index 94aa1de2b06e..3af8a5898fe3 100644 --- a/arch/powerpc/include/asm/ptrace.h +++ b/arch/powerpc/include/asm/ptrace.h @@ -53,6 +53,9 @@ struct pt_regs unsigned long esr; }; unsigned long result; + unsigned long exit_flags; + /* Maintain 16 byte interrupt stack alignment */ + unsigned long __pt_regs_pad[1]; }; }; #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_KUAP) diff --git a/arch/powerpc/include/uapi/asm/ptrace.h b/arch/powerpc/include/= uapi/asm/ptrace.h index 01e630149d48..de56b216c9c5 100644 --- a/arch/powerpc/include/uapi/asm/ptrace.h +++ b/arch/powerpc/include/uapi/asm/ptrace.h @@ -55,6 +55,8 @@ struct pt_regs unsigned long dar; /* Fault registers */ unsigned long dsisr; /* on 4xx/Book-E used for ESR */ unsigned long result; /* Result of a system call */ + unsigned long exit_flags; /* System call exit flags */ + unsigned long __pt_regs_pad[1]; /* Maintain 16 byte interrupt stack align= ment */ }; =20 #endif /* __ASSEMBLER__ */ @@ -114,10 +116,12 @@ struct pt_regs #define PT_DAR 41 #define PT_DSISR 42 #define PT_RESULT 43 -#define PT_DSCR 44 -#define PT_REGS_COUNT 44 +#define PT_EXIT_FLAGS 44 +#define PT_PAD 45 +#define PT_DSCR 46 +#define PT_REGS_COUNT 46 =20 -#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ +#define PT_FPR0 (PT_REGS_COUNT + 4) /* each FP reg occupies 2 slots in thi= s space */ =20 #ifndef __powerpc64__ =20 @@ -129,7 +133,7 @@ struct pt_regs #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit s= pace */ =20 =20 -#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */ +#define PT_VR0 (PT_FPSCR + 2) /* <82> each Vector reg occupies 2 slots in = 64-bit */ #define PT_VSCR (PT_VR0 + 32*2 + 1) #define PT_VRSAVE (PT_VR0 + 33*2) =20 @@ -137,7 +141,7 @@ struct pt_regs /* * Only store first 32 VSRs here. The second 32 VSRs in VR0-31 */ -#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */ +#define PT_VSR0 (PT_VRSAVE + 2) /* each VSR reg occupies 2 slots in 64-bit= */ #define PT_VSR31 (PT_VSR0 + 2*31) #endif /* __powerpc64__ */ =20 diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-of= fsets.c index a4bc80b30410..c0bb09f1db78 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -292,6 +292,7 @@ int main(void) STACK_PT_REGS_OFFSET(_ESR, esr); STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3); STACK_PT_REGS_OFFSET(RESULT, result); + STACK_PT_REGS_OFFSET(EXIT_FLAGS, exit_flags); STACK_PT_REGS_OFFSET(_TRAP, trap); #ifdef CONFIG_PPC64 STACK_PT_REGS_OFFSET(SOFTE, softe); diff --git a/arch/powerpc/kernel/ptrace/ptrace.c b/arch/powerpc/kernel/ptra= ce/ptrace.c index c6997df63287..2134b6d155ff 100644 --- a/arch/powerpc/kernel/ptrace/ptrace.c +++ b/arch/powerpc/kernel/ptrace/ptrace.c @@ -432,6 +432,7 @@ void __init pt_regs_check(void) CHECK_REG(PT_DAR, dar); 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Sun, 14 Dec 2025 13:04:12 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, thuth@redhat.com, sshegde@linux.ibm.com, charlie@rivosinc.com, macro@orcam.me.uk, akpm@linux-foundation.org, ldv@strace.io, deller@gmx.de, ankur.a.arora@oracle.com, segher@kernel.crashing.org, tglx@linutronix.de, thomas.weissschuh@linutronix.de, peterz@infradead.org, menglong8.dong@gmail.com, bigeasy@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, atrajeev@linux.vnet.ibm.com, mark.barnett@arm.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/8] powerpc: Prepare for IRQ entry exit Date: Sun, 14 Dec 2025 18:32:42 +0530 Message-ID: <20251214130245.43664-7-mkchauras@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251214130245.43664-1-mkchauras@linux.ibm.com> References: <20251214130245.43664-1-mkchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEzMDAyMyBTYWx0ZWRfX4hEa928hVlF9 zwkfXq7ShQSKiBfsSJsDalpmCqcnwOuk4b9fh4q9FOeFW3f94cSvAX/IHeS6BZ8mq+iWd9Q4YLp nNPf/9iMHIaS7nQtfPfZwGMRHPWBWF+di4E/sDiEZsGTPYQO3NHTwSnThlN2M3tUU4O5p8gyGZk h+Jy7BtUQ4hPQrC+fB12FszTelRggrWvCgIpqXDmO40cVO+h6a3CVaYztbmXjjmTXu/37j8CSq/ dYuLHGx+jgoqniM/nRNijD9IIP7GLODKVUKE7qhW1Pn+AQvuwflsU40J5VgQl6DcOwGi9c9IijX 7buiQoT6sW6EVeegjNfWt2bvcjFWlkBLM9XtXh04/OTAYSmpXeTY5kzByu4kNiYD3Rk+svvYg/h EWGCyY7y1HJcyocjWfcd6EZPLat1Cw== X-Proofpoint-ORIG-GUID: 5s6Vgn1uCoeR9lf_6KovSIdCAIpjM4eB X-Authority-Analysis: v=2.4 cv=QtRTHFyd c=1 sm=1 tr=0 ts=693eb5d8 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=Ed76zSDasvk_NLogn_cA:9 X-Proofpoint-GUID: yUdzeqo1x4lFZjKHq5_V1Rt-7bieuoSa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-14_03,2025-12-11_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512130023 Content-Type: text/plain; charset="utf-8" From: Mukesh Kumar Chaurasiya Move interrupt entry and exit helper routines from interrupt.h into the PowerPC-specific entry-common.h header as a preparatory step for enabling the generic entry/exit framework. This consolidation places all PowerPC interrupt entry/exit handling in a single common header, aligning with the generic entry infrastructure. The helpers provide architecture-specific handling for interrupt and NMI entry/exit sequences, including: - arch_interrupt_enter/exit_prepare() - arch_interrupt_async_enter/exit_prepare() - arch_interrupt_nmi_enter/exit_prepare() - Supporting helpers such as nap_adjust_return(), check_return_regs_valid(= ), debug register maintenance, and soft mask handling. The functions are copied verbatim from interrupt.h to avoid functional changes at this stage. Subsequent patches will integrate these routines into the generic entry/exit flow. No functional change intended. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/include/asm/entry-common.h | 422 ++++++++++++++++++++++++ 1 file changed, 422 insertions(+) diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include= /asm/entry-common.h index e8ebd42a4e6d..e8bde4c67eaf 100644 --- a/arch/powerpc/include/asm/entry-common.h +++ b/arch/powerpc/include/asm/entry-common.h @@ -7,10 +7,432 @@ =20 #include #include +#include #include #include #include =20 +#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG +/* + * WARN/BUG is handled with a program interrupt so minimise checks here to + * avoid recursion and maximise the chance of getting the first oops handl= ed. + */ +#define INT_SOFT_MASK_BUG_ON(regs, cond) \ +do { \ + if ((user_mode(regs) || (TRAP(regs) !=3D INTERRUPT_PROGRAM))) \ + BUG_ON(cond); \ +} while (0) +#else +#define INT_SOFT_MASK_BUG_ON(regs, cond) +#endif + +#ifdef CONFIG_PPC_BOOK3S_64 +extern char __end_soft_masked[]; +bool search_kernel_soft_mask_table(unsigned long addr); +unsigned long search_kernel_restart_table(unsigned long addr); + +DECLARE_STATIC_KEY_FALSE(interrupt_exit_not_reentrant); + +static inline bool is_implicit_soft_masked(struct pt_regs *regs) +{ + if (user_mode(regs)) + return false; + + if (regs->nip >=3D (unsigned long)__end_soft_masked) + return false; + + return search_kernel_soft_mask_table(regs->nip); +} + +static inline void srr_regs_clobbered(void) +{ + local_paca->srr_valid =3D 0; + local_paca->hsrr_valid =3D 0; +} +#else +static inline unsigned long search_kernel_restart_table(unsigned long addr) +{ + return 0; +} + +static inline bool is_implicit_soft_masked(struct pt_regs *regs) +{ + return false; +} + +static inline void srr_regs_clobbered(void) +{ +} +#endif + +static inline void nap_adjust_return(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC_970_NAP + if (unlikely(test_thread_local_flags(_TLF_NAPPING))) { + /* Can avoid a test-and-clear because NMIs do not call this */ + clear_thread_local_flags(_TLF_NAPPING); + regs_set_return_ip(regs, (unsigned long)power4_idle_nap_return); + } +#endif +} + +static inline void booke_load_dbcr0(void) +{ +#ifdef CONFIG_PPC_ADV_DEBUG_REGS + unsigned long dbcr0 =3D current->thread.debug.dbcr0; + + if (likely(!(dbcr0 & DBCR0_IDM))) + return; + + /* + * Check to see if the dbcr0 register is set up to debug. + * Use the internal debug mode bit to do this. + */ + mtmsr(mfmsr() & ~MSR_DE); + if (IS_ENABLED(CONFIG_PPC32)) { + isync(); + global_dbcr0[smp_processor_id()] =3D mfspr(SPRN_DBCR0); + } + mtspr(SPRN_DBCR0, dbcr0); + mtspr(SPRN_DBSR, -1); +#endif +} + +static inline void booke_restore_dbcr0(void) +{ +#ifdef CONFIG_PPC_ADV_DEBUG_REGS + unsigned long dbcr0 =3D current->thread.debug.dbcr0; + + if (IS_ENABLED(CONFIG_PPC32) && unlikely(dbcr0 & DBCR0_IDM)) { + mtspr(SPRN_DBSR, -1); + mtspr(SPRN_DBCR0, global_dbcr0[smp_processor_id()]); + } +#endif +} + +static inline void check_return_regs_valid(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC_BOOK3S_64 + unsigned long trap, srr0, srr1; + static bool warned; + u8 *validp; + char *h; + + if (trap_is_scv(regs)) + return; + + trap =3D TRAP(regs); + // EE in HV mode sets HSRRs like 0xea0 + if (cpu_has_feature(CPU_FTR_HVMODE) && trap =3D=3D INTERRUPT_EXTERNAL) + trap =3D 0xea0; + + switch (trap) { + case 0x980: + case INTERRUPT_H_DATA_STORAGE: + case 0xe20: + case 0xe40: + case INTERRUPT_HMI: + case 0xe80: + case 0xea0: + case INTERRUPT_H_FAC_UNAVAIL: + case 0x1200: + case 0x1500: + case 0x1600: + case 0x1800: + validp =3D &local_paca->hsrr_valid; + if (!READ_ONCE(*validp)) + return; + + srr0 =3D mfspr(SPRN_HSRR0); + srr1 =3D mfspr(SPRN_HSRR1); + h =3D "H"; + + break; + default: + validp =3D &local_paca->srr_valid; + if (!READ_ONCE(*validp)) + return; + + srr0 =3D mfspr(SPRN_SRR0); + srr1 =3D mfspr(SPRN_SRR1); + h =3D ""; + break; + } + + if (srr0 =3D=3D regs->nip && srr1 =3D=3D regs->msr) + return; + + /* + * A NMI / soft-NMI interrupt may have come in after we found + * srr_valid and before the SRRs are loaded. The interrupt then + * comes in and clobbers SRRs and clears srr_valid. Then we load + * the SRRs here and test them above and find they don't match. + * + * Test validity again after that, to catch such false positives. + * + * This test in general will have some window for false negatives + * and may not catch and fix all such cases if an NMI comes in + * later and clobbers SRRs without clearing srr_valid, but hopefully + * such things will get caught most of the time, statistically + * enough to be able to get a warning out. + */ + if (!READ_ONCE(*validp)) + return; + + if (!data_race(warned)) { + data_race(warned =3D true); + pr_warn("%sSRR0 was: %lx should be: %lx\n", h, srr0, regs->nip); + pr_warn("%sSRR1 was: %lx should be: %lx\n", h, srr1, regs->msr); + show_regs(regs); + } + + WRITE_ONCE(*validp, 0); /* fixup */ +#endif +} + +static inline void arch_interrupt_enter_prepare(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC64 + irq_soft_mask_set(IRQS_ALL_DISABLED); + + /* + * If the interrupt was taken with HARD_DIS clear, then enable MSR[EE]. + * Asynchronous interrupts get here with HARD_DIS set (see below), so + * this enables MSR[EE] for synchronous interrupts. IRQs remain + * soft-masked. The interrupt handler may later call + * interrupt_cond_local_irq_enable() to achieve a regular process + * context. + */ + if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) { + INT_SOFT_MASK_BUG_ON(regs, !(regs->msr & MSR_EE)); + __hard_irq_enable(); + } else { + __hard_RI_enable(); + } + /* Enable MSR[RI] early, to support kernel SLB and hash faults */ +#endif + + if (!regs_irqs_disabled(regs)) + trace_hardirqs_off(); + + if (user_mode(regs)) { + kuap_lock(); + CT_WARN_ON(ct_state() !=3D CT_STATE_USER); + user_exit_irqoff(); + + account_cpu_user_entry(); + account_stolen_time(); + } else { + kuap_save_and_lock(regs); + /* + * CT_WARN_ON comes here via program_check_exception, + * so avoid recursion. + */ + if (TRAP(regs) !=3D INTERRUPT_PROGRAM) + CT_WARN_ON(ct_state() !=3D CT_STATE_KERNEL && + ct_state() !=3D CT_STATE_IDLE); + INT_SOFT_MASK_BUG_ON(regs, is_implicit_soft_masked(regs)); + INT_SOFT_MASK_BUG_ON(regs, regs_irqs_disabled(regs) && + search_kernel_restart_table(regs->nip)); + } + INT_SOFT_MASK_BUG_ON(regs, !regs_irqs_disabled(regs) && + !(regs->msr & MSR_EE)); + + booke_restore_dbcr0(); +} + +/* + * Care should be taken to note that arch_interrupt_exit_prepare and + * arch_interrupt_async_exit_prepare do not necessarily return immediately= to + * regs context (e.g., if regs is usermode, we don't necessarily return to + * user mode). Other interrupts might be taken between here and return, + * context switch / preemption may occur in the exit path after this, or a + * signal may be delivered, etc. + * + * The real interrupt exit code is platform specific, e.g., + * interrupt_exit_user_prepare / interrupt_exit_kernel_prepare for 64s. + * + * However arch_interrupt_nmi_exit_prepare does return directly to regs, b= ecause + * NMIs do not do "exit work" or replay soft-masked interrupts. + */ +static inline void arch_interrupt_exit_prepare(struct pt_regs *regs) +{ +} + +static inline void arch_interrupt_async_enter_prepare(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC64 + /* Ensure arch_interrupt_enter_prepare does not enable MSR[EE] */ + local_paca->irq_happened |=3D PACA_IRQ_HARD_DIS; +#endif + arch_interrupt_enter_prepare(regs); +#ifdef CONFIG_PPC_BOOK3S_64 + /* + * RI=3D1 is set by arch_interrupt_enter_prepare, so this thread flags ac= cess + * has to come afterward (it can cause SLB faults). + */ + if (cpu_has_feature(CPU_FTR_CTRL) && + !test_thread_local_flags(_TLF_RUNLATCH)) + __ppc64_runlatch_on(); +#endif + irq_enter(); +} + +static inline void arch_interrupt_async_exit_prepare(struct pt_regs *regs) +{ + /* + * Adjust at exit so the main handler sees the true NIA. This must + * come before irq_exit() because irq_exit can enable interrupts, and + * if another interrupt is taken before nap_adjust_return has run + * here, then that interrupt would return directly to idle nap return. + */ + nap_adjust_return(regs); + + irq_exit(); + arch_interrupt_exit_prepare(regs); +} + +struct interrupt_nmi_state { +#ifdef CONFIG_PPC64 + u8 irq_soft_mask; + u8 irq_happened; + u8 ftrace_enabled; + u64 softe; +#endif +}; + +static inline bool nmi_disables_ftrace(struct pt_regs *regs) +{ + /* Allow DEC and PMI to be traced when they are soft-NMI */ + if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) { + if (TRAP(regs) =3D=3D INTERRUPT_DECREMENTER) + return false; + if (TRAP(regs) =3D=3D INTERRUPT_PERFMON) + return false; + } + if (IS_ENABLED(CONFIG_PPC_BOOK3E_64)) { + if (TRAP(regs) =3D=3D INTERRUPT_PERFMON) + return false; + } + + return true; +} + +static inline void arch_interrupt_nmi_enter_prepare(struct pt_regs *regs, + struct interrupt_nmi_state *state) +{ +#ifdef CONFIG_PPC64 + state->irq_soft_mask =3D local_paca->irq_soft_mask; + state->irq_happened =3D local_paca->irq_happened; + state->softe =3D regs->softe; + + /* + * Set IRQS_ALL_DISABLED unconditionally so irqs_disabled() does + * the right thing, and set IRQ_HARD_DIS. We do not want to reconcile + * because that goes through irq tracing which we don't want in NMI. + */ + local_paca->irq_soft_mask =3D IRQS_ALL_DISABLED; + local_paca->irq_happened |=3D PACA_IRQ_HARD_DIS; + + if (!(regs->msr & MSR_EE) || is_implicit_soft_masked(regs)) { + /* + * Adjust regs->softe to be soft-masked if it had not been + * reconcied (e.g., interrupt entry with MSR[EE]=3D0 but softe + * not yet set disabled), or if it was in an implicit soft + * masked state. This makes regs_irqs_disabled(regs) + * behave as expected. + */ + regs->softe =3D IRQS_ALL_DISABLED; + } + + __hard_RI_enable(); + + /* Don't do any per-CPU operations until interrupt state is fixed */ + + if (nmi_disables_ftrace(regs)) { + state->ftrace_enabled =3D this_cpu_get_ftrace_enabled(); + this_cpu_set_ftrace_enabled(0); + } +#endif + + /* If data relocations are enabled, it's safe to use nmi_enter() */ + if (mfmsr() & MSR_DR) { + nmi_enter(); + return; + } + + /* + * But do not use nmi_enter() for pseries hash guest taking a real-mode + * NMI because not everything it touches is within the RMA limit. + */ + if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && + firmware_has_feature(FW_FEATURE_LPAR) && + !radix_enabled()) + return; + + /* + * Likewise, don't use it if we have some form of instrumentation (like + * KASAN shadow) that is not safe to access in real mode (even on radix) + */ + if (IS_ENABLED(CONFIG_KASAN)) + return; + + /* + * Likewise, do not use it in real mode if percpu first chunk is not + * embedded. With CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK enabled there + * are chances where percpu allocation can come from vmalloc area. + */ + if (percpu_first_chunk_is_paged) + return; + + /* Otherwise, it should be safe to call it */ + nmi_enter(); +} + +static inline void arch_interrupt_nmi_exit_prepare(struct pt_regs *regs, + struct interrupt_nmi_state *state) +{ + if (mfmsr() & MSR_DR) { + // nmi_exit if relocations are on + nmi_exit(); + } else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && + firmware_has_feature(FW_FEATURE_LPAR) && + !radix_enabled()) { + // no nmi_exit for a pseries hash guest taking a real mode exception + } else if (IS_ENABLED(CONFIG_KASAN)) { + // no nmi_exit for KASAN in real mode + } else if (percpu_first_chunk_is_paged) { + // no nmi_exit if percpu first chunk is not embedded + } else { + nmi_exit(); + } + + /* + * nmi does not call nap_adjust_return because nmi should not create + * new work to do (must use irq_work for that). + */ + +#ifdef CONFIG_PPC64 +#ifdef CONFIG_PPC_BOOK3S + if (regs_irqs_disabled(regs)) { + unsigned long rst =3D search_kernel_restart_table(regs->nip); + + if (rst) + regs_set_return_ip(regs, rst); + } +#endif + + if (nmi_disables_ftrace(regs)) + this_cpu_set_ftrace_enabled(state->ftrace_enabled); + + /* Check we didn't change the pending interrupt mask. */ + WARN_ON_ONCE((state->irq_happened | PACA_IRQ_HARD_DIS) !=3D local_paca->i= rq_happened); + regs->softe =3D state->softe; + local_paca->irq_happened =3D state->irq_happened; + local_paca->irq_soft_mask =3D state->irq_soft_mask; +#endif +} + static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) { if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) --=20 2.52.0 From nobody Tue Dec 16 07:41:28 2025 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 206D621019C for ; Sun, 14 Dec 2025 13:05:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.158.5 ARC-Seal: i=1; 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Sun, 14 Dec 2025 13:04:25 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5D7F720043; Sun, 14 Dec 2025 13:04:25 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1268120040; Sun, 14 Dec 2025 13:04:19 +0000 (GMT) Received: from li-1a3e774c-28e4-11b2-a85c-acc9f2883e29.ibm.com.com (unknown [9.124.210.21]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Sun, 14 Dec 2025 13:04:18 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, thuth@redhat.com, sshegde@linux.ibm.com, charlie@rivosinc.com, macro@orcam.me.uk, akpm@linux-foundation.org, ldv@strace.io, deller@gmx.de, ankur.a.arora@oracle.com, segher@kernel.crashing.org, tglx@linutronix.de, thomas.weissschuh@linutronix.de, peterz@infradead.org, menglong8.dong@gmail.com, bigeasy@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, atrajeev@linux.vnet.ibm.com, mark.barnett@arm.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/8] powerpc: Enable IRQ generic entry/exit path. Date: Sun, 14 Dec 2025 18:32:43 +0530 Message-ID: <20251214130245.43664-8-mkchauras@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251214130245.43664-1-mkchauras@linux.ibm.com> References: <20251214130245.43664-1-mkchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: UwG_wH-8PPbf7_bWUmohQ2ubP2UD1nif X-Proofpoint-ORIG-GUID: 73Zalvo_9tc3E3H-2Ekim4efjDiRzmL9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEzMDAyMyBTYWx0ZWRfXwrcV25jmKld6 Id8iUL8ob4NYzmF4VgTCoBlttUEzfsYN9MQVGL3K4ZvSA+hevTc40HpOkU0r41JMbjsvUhN4tE/ Ct32gqQPL84y1iNrUknaZChryJ4g2pDAOeTVE5cEGd8MtOtkcrK7UGyb0WCSKJApyoTryx5urrW xjQ7e9CYlewJbGgeYHsCLU51xvbnLG53gFT1Z8865EqkeNTnPB5vzSF5R2IDJsbC1yFVh6lKWcm j6kfCIeumcl5Qc3S0NOo1dlLyIGq6DUKOr3WYvXjXy5BrO6jyQ3h7/L9bEUr3esfF1NSWBbjFtD FsR6sgzLN9KiREhEuDLYU4bU344lsGTOj9Mh/xKKvPJcRtteck9ITZvXOuTpbRdGyChetf9d3Es +7O0XquM2U6C5I+5D5Nq18L/U4HA1g== X-Authority-Analysis: v=2.4 cv=L/MQguT8 c=1 sm=1 tr=0 ts=693eb5df cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=NIz8WlYnyIp8l4wp2tMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-14_03,2025-12-11_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 malwarescore=0 adultscore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 bulkscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512130023 From: Mukesh Kumar Chaurasiya Enable the generic IRQ entry/exit infrastructure on PowerPC by selecting GENERIC_IRQ_ENTRY and integrating the architecture-specific interrupt handlers with the generic entry/exit APIs. This change replaces PowerPC=E2=80=99s local interrupt entry/exit handling = with calls to the generic irqentry_* helpers, aligning the architecture with the common kernel entry model. The macros that define interrupt, async, and NMI handlers are updated to use irqentry_enter()/irqentry_exit() and irqentry_nmi_enter()/irqentry_nmi_exit() where applicable. Key updates include: - Select GENERIC_IRQ_ENTRY in Kconfig. - Replace interrupt_enter/exit_prepare() with arch_interrupt_* helpers. - Integrate irqentry_enter()/exit() in standard and async interrupt paths. - Integrate irqentry_nmi_enter()/exit() in NMI handlers. - Remove redundant irq_enter()/irq_exit() calls now handled generically. - Use irqentry_exit_cond_resched() for preemption checks. This change establishes the necessary wiring for PowerPC to use the generic IRQ entry/exit framework while maintaining existing semantics. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/Kconfig | 1 + arch/powerpc/include/asm/entry-common.h | 66 +--- arch/powerpc/include/asm/interrupt.h | 499 +++--------------------- arch/powerpc/kernel/interrupt.c | 13 +- 4 files changed, 74 insertions(+), 505 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index e24f4d88885a..b0c602c3bbe1 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -206,6 +206,7 @@ config PPC select GENERIC_GETTIMEOFDAY select GENERIC_IDLE_POLL_SETUP select GENERIC_IOREMAP + select GENERIC_IRQ_ENTRY select GENERIC_IRQ_SHOW select GENERIC_IRQ_SHOW_LEVEL select GENERIC_PCI_IOMAP if PCI diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include= /asm/entry-common.h index e8bde4c67eaf..e2ae7416dee1 100644 --- a/arch/powerpc/include/asm/entry-common.h +++ b/arch/powerpc/include/asm/entry-common.h @@ -257,6 +257,17 @@ static inline void arch_interrupt_enter_prepare(struct= pt_regs *regs) */ static inline void arch_interrupt_exit_prepare(struct pt_regs *regs) { + if (user_mode(regs)) { + BUG_ON(regs_is_unrecoverable(regs)); + BUG_ON(regs_irqs_disabled(regs)); + /* + * We don't need to restore AMR on the way back to userspace for KUAP. + * AMR can only have been unlocked if we interrupted the kernel. + */ + kuap_assert_locked(); + + local_irq_disable(); + } } =20 static inline void arch_interrupt_async_enter_prepare(struct pt_regs *regs) @@ -275,7 +286,6 @@ static inline void arch_interrupt_async_enter_prepare(s= truct pt_regs *regs) !test_thread_local_flags(_TLF_RUNLATCH)) __ppc64_runlatch_on(); #endif - irq_enter(); } =20 static inline void arch_interrupt_async_exit_prepare(struct pt_regs *regs) @@ -288,7 +298,6 @@ static inline void arch_interrupt_async_exit_prepare(st= ruct pt_regs *regs) */ nap_adjust_return(regs); =20 - irq_exit(); arch_interrupt_exit_prepare(regs); } =20 @@ -354,59 +363,11 @@ static inline void arch_interrupt_nmi_enter_prepare(s= truct pt_regs *regs, this_cpu_set_ftrace_enabled(0); } #endif - - /* If data relocations are enabled, it's safe to use nmi_enter() */ - if (mfmsr() & MSR_DR) { - nmi_enter(); - return; - } - - /* - * But do not use nmi_enter() for pseries hash guest taking a real-mode - * NMI because not everything it touches is within the RMA limit. - */ - if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && - firmware_has_feature(FW_FEATURE_LPAR) && - !radix_enabled()) - return; - - /* - * Likewise, don't use it if we have some form of instrumentation (like - * KASAN shadow) that is not safe to access in real mode (even on radix) - */ - if (IS_ENABLED(CONFIG_KASAN)) - return; - - /* - * Likewise, do not use it in real mode if percpu first chunk is not - * embedded. With CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK enabled there - * are chances where percpu allocation can come from vmalloc area. - */ - if (percpu_first_chunk_is_paged) - return; - - /* Otherwise, it should be safe to call it */ - nmi_enter(); } =20 static inline void arch_interrupt_nmi_exit_prepare(struct pt_regs *regs, struct interrupt_nmi_state *state) { - if (mfmsr() & MSR_DR) { - // nmi_exit if relocations are on - nmi_exit(); - } else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && - firmware_has_feature(FW_FEATURE_LPAR) && - !radix_enabled()) { - // no nmi_exit for a pseries hash guest taking a real mode exception - } else if (IS_ENABLED(CONFIG_KASAN)) { - // no nmi_exit for KASAN in real mode - } else if (percpu_first_chunk_is_paged) { - // no nmi_exit if percpu first chunk is not embedded - } else { - nmi_exit(); - } - /* * nmi does not call nap_adjust_return because nmi should not create * new work to do (must use irq_work for that). @@ -435,6 +396,8 @@ static inline void arch_interrupt_nmi_exit_prepare(stru= ct pt_regs *regs, =20 static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) { + kuap_lock(); + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) BUG_ON(irq_soft_mask_return() !=3D IRQS_ALL_DISABLED); =20 @@ -467,11 +430,8 @@ static __always_inline void arch_enter_from_user_mode(= struct pt_regs *regs) } else #endif kuap_assert_locked(); - booke_restore_dbcr0(); - account_cpu_user_entry(); - account_stolen_time(); =20 /* diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/as= m/interrupt.h index 77ff8e33f8cd..e2376de85370 100644 --- a/arch/powerpc/include/asm/interrupt.h +++ b/arch/powerpc/include/asm/interrupt.h @@ -66,433 +66,10 @@ =20 #ifndef __ASSEMBLER__ =20 -#include -#include #include /* for show_regs */ +#include =20 -#include -#include -#include #include -#include - -#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG -/* - * WARN/BUG is handled with a program interrupt so minimise checks here to - * avoid recursion and maximise the chance of getting the first oops handl= ed. - */ -#define INT_SOFT_MASK_BUG_ON(regs, cond) \ -do { \ - if ((user_mode(regs) || (TRAP(regs) !=3D INTERRUPT_PROGRAM))) \ - BUG_ON(cond); \ -} while (0) -#else -#define INT_SOFT_MASK_BUG_ON(regs, cond) -#endif - -#ifdef CONFIG_PPC_BOOK3S_64 -extern char __end_soft_masked[]; -bool search_kernel_soft_mask_table(unsigned long addr); -unsigned long search_kernel_restart_table(unsigned long addr); - -DECLARE_STATIC_KEY_FALSE(interrupt_exit_not_reentrant); - -static inline bool is_implicit_soft_masked(struct pt_regs *regs) -{ - if (user_mode(regs)) - return false; - - if (regs->nip >=3D (unsigned long)__end_soft_masked) - return false; - - return search_kernel_soft_mask_table(regs->nip); -} - -static inline void srr_regs_clobbered(void) -{ - local_paca->srr_valid =3D 0; - local_paca->hsrr_valid =3D 0; -} -#else -static inline unsigned long search_kernel_restart_table(unsigned long addr) -{ - return 0; -} - -static inline bool is_implicit_soft_masked(struct pt_regs *regs) -{ - return false; -} - -static inline void srr_regs_clobbered(void) -{ -} -#endif - -static inline void nap_adjust_return(struct pt_regs *regs) -{ -#ifdef CONFIG_PPC_970_NAP - if (unlikely(test_thread_local_flags(_TLF_NAPPING))) { - /* Can avoid a test-and-clear because NMIs do not call this */ - clear_thread_local_flags(_TLF_NAPPING); - regs_set_return_ip(regs, (unsigned long)power4_idle_nap_return); - } -#endif -} - -static inline void booke_load_dbcr0(void) -{ -#ifdef CONFIG_PPC_ADV_DEBUG_REGS - unsigned long dbcr0 =3D current->thread.debug.dbcr0; - - if (likely(!(dbcr0 & DBCR0_IDM))) - return; - - /* - * Check to see if the dbcr0 register is set up to debug. - * Use the internal debug mode bit to do this. - */ - mtmsr(mfmsr() & ~MSR_DE); - if (IS_ENABLED(CONFIG_PPC32)) { - isync(); - global_dbcr0[smp_processor_id()] =3D mfspr(SPRN_DBCR0); - } - mtspr(SPRN_DBCR0, dbcr0); - mtspr(SPRN_DBSR, -1); -#endif -} - -static inline void booke_restore_dbcr0(void) -{ -#ifdef CONFIG_PPC_ADV_DEBUG_REGS - unsigned long dbcr0 =3D current->thread.debug.dbcr0; - - if (IS_ENABLED(CONFIG_PPC32) && unlikely(dbcr0 & DBCR0_IDM)) { - mtspr(SPRN_DBSR, -1); - mtspr(SPRN_DBCR0, global_dbcr0[smp_processor_id()]); - } -#endif -} - -static inline void check_return_regs_valid(struct pt_regs *regs) -{ -#ifdef CONFIG_PPC_BOOK3S_64 - unsigned long trap, srr0, srr1; - static bool warned; - u8 *validp; - char *h; - - if (trap_is_scv(regs)) - return; - - trap =3D TRAP(regs); - // EE in HV mode sets HSRRs like 0xea0 - if (cpu_has_feature(CPU_FTR_HVMODE) && trap =3D=3D INTERRUPT_EXTERNAL) - trap =3D 0xea0; - - switch (trap) { - case 0x980: - case INTERRUPT_H_DATA_STORAGE: - case 0xe20: - case 0xe40: - case INTERRUPT_HMI: - case 0xe80: - case 0xea0: - case INTERRUPT_H_FAC_UNAVAIL: - case 0x1200: - case 0x1500: - case 0x1600: - case 0x1800: - validp =3D &local_paca->hsrr_valid; - if (!READ_ONCE(*validp)) - return; - - srr0 =3D mfspr(SPRN_HSRR0); - srr1 =3D mfspr(SPRN_HSRR1); - h =3D "H"; - - break; - default: - validp =3D &local_paca->srr_valid; - if (!READ_ONCE(*validp)) - return; - - srr0 =3D mfspr(SPRN_SRR0); - srr1 =3D mfspr(SPRN_SRR1); - h =3D ""; - break; - } - - if (srr0 =3D=3D regs->nip && srr1 =3D=3D regs->msr) - return; - - /* - * A NMI / soft-NMI interrupt may have come in after we found - * srr_valid and before the SRRs are loaded. The interrupt then - * comes in and clobbers SRRs and clears srr_valid. Then we load - * the SRRs here and test them above and find they don't match. - * - * Test validity again after that, to catch such false positives. - * - * This test in general will have some window for false negatives - * and may not catch and fix all such cases if an NMI comes in - * later and clobbers SRRs without clearing srr_valid, but hopefully - * such things will get caught most of the time, statistically - * enough to be able to get a warning out. - */ - if (!READ_ONCE(*validp)) - return; - - if (!data_race(warned)) { - data_race(warned =3D true); - pr_warn("%sSRR0 was: %lx should be: %lx\n", h, srr0, regs->nip); - pr_warn("%sSRR1 was: %lx should be: %lx\n", h, srr1, regs->msr); - show_regs(regs); - } - - WRITE_ONCE(*validp, 0); /* fixup */ -#endif -} - -static inline void interrupt_enter_prepare(struct pt_regs *regs) -{ -#ifdef CONFIG_PPC64 - irq_soft_mask_set(IRQS_ALL_DISABLED); - - /* - * If the interrupt was taken with HARD_DIS clear, then enable MSR[EE]. - * Asynchronous interrupts get here with HARD_DIS set (see below), so - * this enables MSR[EE] for synchronous interrupts. IRQs remain - * soft-masked. The interrupt handler may later call - * interrupt_cond_local_irq_enable() to achieve a regular process - * context. - */ - if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) { - INT_SOFT_MASK_BUG_ON(regs, !(regs->msr & MSR_EE)); - __hard_irq_enable(); - } else { - __hard_RI_enable(); - } - /* Enable MSR[RI] early, to support kernel SLB and hash faults */ -#endif - - if (!regs_irqs_disabled(regs)) - trace_hardirqs_off(); - - if (user_mode(regs)) { - kuap_lock(); - CT_WARN_ON(ct_state() !=3D CT_STATE_USER); - user_exit_irqoff(); - - account_cpu_user_entry(); - account_stolen_time(); - } else { - kuap_save_and_lock(regs); - /* - * CT_WARN_ON comes here via program_check_exception, - * so avoid recursion. - */ - if (TRAP(regs) !=3D INTERRUPT_PROGRAM) - CT_WARN_ON(ct_state() !=3D CT_STATE_KERNEL && - ct_state() !=3D CT_STATE_IDLE); - INT_SOFT_MASK_BUG_ON(regs, is_implicit_soft_masked(regs)); - INT_SOFT_MASK_BUG_ON(regs, regs_irqs_disabled(regs) && - search_kernel_restart_table(regs->nip)); - } - INT_SOFT_MASK_BUG_ON(regs, !regs_irqs_disabled(regs) && - !(regs->msr & MSR_EE)); - - booke_restore_dbcr0(); -} - -/* - * Care should be taken to note that interrupt_exit_prepare and - * interrupt_async_exit_prepare do not necessarily return immediately to - * regs context (e.g., if regs is usermode, we don't necessarily return to - * user mode). Other interrupts might be taken between here and return, - * context switch / preemption may occur in the exit path after this, or a - * signal may be delivered, etc. - * - * The real interrupt exit code is platform specific, e.g., - * interrupt_exit_user_prepare / interrupt_exit_kernel_prepare for 64s. - * - * However interrupt_nmi_exit_prepare does return directly to regs, because - * NMIs do not do "exit work" or replay soft-masked interrupts. - */ -static inline void interrupt_exit_prepare(struct pt_regs *regs) -{ -} - -static inline void interrupt_async_enter_prepare(struct pt_regs *regs) -{ -#ifdef CONFIG_PPC64 - /* Ensure interrupt_enter_prepare does not enable MSR[EE] */ - local_paca->irq_happened |=3D PACA_IRQ_HARD_DIS; -#endif - interrupt_enter_prepare(regs); -#ifdef CONFIG_PPC_BOOK3S_64 - /* - * RI=3D1 is set by interrupt_enter_prepare, so this thread flags access - * has to come afterward (it can cause SLB faults). - */ - if (cpu_has_feature(CPU_FTR_CTRL) && - !test_thread_local_flags(_TLF_RUNLATCH)) - __ppc64_runlatch_on(); -#endif - irq_enter(); -} - -static inline void interrupt_async_exit_prepare(struct pt_regs *regs) -{ - /* - * Adjust at exit so the main handler sees the true NIA. This must - * come before irq_exit() because irq_exit can enable interrupts, and - * if another interrupt is taken before nap_adjust_return has run - * here, then that interrupt would return directly to idle nap return. - */ - nap_adjust_return(regs); - - irq_exit(); - interrupt_exit_prepare(regs); -} - -struct interrupt_nmi_state { -#ifdef CONFIG_PPC64 - u8 irq_soft_mask; - u8 irq_happened; - u8 ftrace_enabled; - u64 softe; -#endif -}; - -static inline bool nmi_disables_ftrace(struct pt_regs *regs) -{ - /* Allow DEC and PMI to be traced when they are soft-NMI */ - if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) { - if (TRAP(regs) =3D=3D INTERRUPT_DECREMENTER) - return false; - if (TRAP(regs) =3D=3D INTERRUPT_PERFMON) - return false; - } - if (IS_ENABLED(CONFIG_PPC_BOOK3E_64)) { - if (TRAP(regs) =3D=3D INTERRUPT_PERFMON) - return false; - } - - return true; -} - -static inline void interrupt_nmi_enter_prepare(struct pt_regs *regs, struc= t interrupt_nmi_state *state) -{ -#ifdef CONFIG_PPC64 - state->irq_soft_mask =3D local_paca->irq_soft_mask; - state->irq_happened =3D local_paca->irq_happened; - state->softe =3D regs->softe; - - /* - * Set IRQS_ALL_DISABLED unconditionally so irqs_disabled() does - * the right thing, and set IRQ_HARD_DIS. We do not want to reconcile - * because that goes through irq tracing which we don't want in NMI. - */ - local_paca->irq_soft_mask =3D IRQS_ALL_DISABLED; - local_paca->irq_happened |=3D PACA_IRQ_HARD_DIS; - - if (!(regs->msr & MSR_EE) || is_implicit_soft_masked(regs)) { - /* - * Adjust regs->softe to be soft-masked if it had not been - * reconcied (e.g., interrupt entry with MSR[EE]=3D0 but softe - * not yet set disabled), or if it was in an implicit soft - * masked state. This makes regs_irqs_disabled(regs) - * behave as expected. - */ - regs->softe =3D IRQS_ALL_DISABLED; - } - - __hard_RI_enable(); - - /* Don't do any per-CPU operations until interrupt state is fixed */ - - if (nmi_disables_ftrace(regs)) { - state->ftrace_enabled =3D this_cpu_get_ftrace_enabled(); - this_cpu_set_ftrace_enabled(0); - } -#endif - - /* If data relocations are enabled, it's safe to use nmi_enter() */ - if (mfmsr() & MSR_DR) { - nmi_enter(); - return; - } - - /* - * But do not use nmi_enter() for pseries hash guest taking a real-mode - * NMI because not everything it touches is within the RMA limit. - */ - if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && - firmware_has_feature(FW_FEATURE_LPAR) && - !radix_enabled()) - return; - - /* - * Likewise, don't use it if we have some form of instrumentation (like - * KASAN shadow) that is not safe to access in real mode (even on radix) - */ - if (IS_ENABLED(CONFIG_KASAN)) - return; - - /* - * Likewise, do not use it in real mode if percpu first chunk is not - * embedded. With CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK enabled there - * are chances where percpu allocation can come from vmalloc area. - */ - if (percpu_first_chunk_is_paged) - return; - - /* Otherwise, it should be safe to call it */ - nmi_enter(); -} - -static inline void interrupt_nmi_exit_prepare(struct pt_regs *regs, struct= interrupt_nmi_state *state) -{ - if (mfmsr() & MSR_DR) { - // nmi_exit if relocations are on - nmi_exit(); - } else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && - firmware_has_feature(FW_FEATURE_LPAR) && - !radix_enabled()) { - // no nmi_exit for a pseries hash guest taking a real mode exception - } else if (IS_ENABLED(CONFIG_KASAN)) { - // no nmi_exit for KASAN in real mode - } else if (percpu_first_chunk_is_paged) { - // no nmi_exit if percpu first chunk is not embedded - } else { - nmi_exit(); - } - - /* - * nmi does not call nap_adjust_return because nmi should not create - * new work to do (must use irq_work for that). - */ - -#ifdef CONFIG_PPC64 -#ifdef CONFIG_PPC_BOOK3S - if (regs_irqs_disabled(regs)) { - unsigned long rst =3D search_kernel_restart_table(regs->nip); - if (rst) - regs_set_return_ip(regs, rst); - } -#endif - - if (nmi_disables_ftrace(regs)) - this_cpu_set_ftrace_enabled(state->ftrace_enabled); - - /* Check we didn't change the pending interrupt mask. */ - WARN_ON_ONCE((state->irq_happened | PACA_IRQ_HARD_DIS) !=3D local_paca->i= rq_happened); - regs->softe =3D state->softe; - local_paca->irq_happened =3D state->irq_happened; - local_paca->irq_soft_mask =3D state->irq_soft_mask; -#endif -} =20 /* * Don't use noinstr here like x86, but rather add NOKPROBE_SYMBOL to each @@ -574,11 +151,14 @@ static __always_inline void ____##func(struct pt_regs= *regs); \ \ interrupt_handler void func(struct pt_regs *regs) \ { \ - interrupt_enter_prepare(regs); \ - \ + irqentry_state_t state; \ + arch_interrupt_enter_prepare(regs); \ + state =3D irqentry_enter(regs); \ + instrumentation_begin(); \ ____##func (regs); \ - \ - interrupt_exit_prepare(regs); \ + instrumentation_end(); \ + arch_interrupt_exit_prepare(regs); \ + irqentry_exit(regs, state); \ } \ NOKPROBE_SYMBOL(func); \ \ @@ -608,12 +188,15 @@ static __always_inline long ____##func(struct pt_regs= *regs); \ interrupt_handler long func(struct pt_regs *regs) \ { \ long ret; \ + irqentry_state_t state; \ \ - interrupt_enter_prepare(regs); \ - \ + arch_interrupt_enter_prepare(regs); \ + state =3D irqentry_enter(regs); \ + instrumentation_begin(); \ ret =3D ____##func (regs); \ - \ - interrupt_exit_prepare(regs); \ + instrumentation_end(); \ + arch_interrupt_exit_prepare(regs); \ + irqentry_exit(regs, state); \ \ return ret; \ } \ @@ -642,11 +225,16 @@ static __always_inline void ____##func(struct pt_regs= *regs); \ \ interrupt_handler void func(struct pt_regs *regs) \ { \ - interrupt_async_enter_prepare(regs); \ - \ + irqentry_state_t state; \ + arch_interrupt_async_enter_prepare(regs); \ + state =3D irqentry_enter(regs); \ + instrumentation_begin(); \ + irq_enter_rcu(); \ ____##func (regs); \ - \ - interrupt_async_exit_prepare(regs); \ + irq_exit_rcu(); \ + instrumentation_end(); \ + arch_interrupt_async_exit_prepare(regs); \ + irqentry_exit(regs, state); \ } \ NOKPROBE_SYMBOL(func); \ \ @@ -676,14 +264,43 @@ ____##func(struct pt_regs *regs); \ \ interrupt_handler long func(struct pt_regs *regs) \ { \ - struct interrupt_nmi_state state; \ + irqentry_state_t state; \ + struct interrupt_nmi_state nmi_state; \ long ret; \ \ - interrupt_nmi_enter_prepare(regs, &state); \ - \ + arch_interrupt_nmi_enter_prepare(regs, &nmi_state); \ + if (mfmsr() & MSR_DR) { \ + /* nmi_entry if relocations are on */ \ + state =3D irqentry_nmi_enter(regs); \ + } else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && \ + firmware_has_feature(FW_FEATURE_LPAR) && \ + !radix_enabled()) { \ + /* no nmi_entry for a pseries hash guest \ + * taking a real mode exception */ \ + } else if (IS_ENABLED(CONFIG_KASAN)) { \ + /* no nmi_entry for KASAN in real mode */ \ + } else if (percpu_first_chunk_is_paged) { \ + /* no nmi_entry if percpu first chunk is not embedded */\ + } else { \ + state =3D irqentry_nmi_enter(regs); \ + } \ ret =3D ____##func (regs); \ - \ - interrupt_nmi_exit_prepare(regs, &state); \ + arch_interrupt_nmi_exit_prepare(regs, &nmi_state); \ + if (mfmsr() & MSR_DR) { \ + /* nmi_exit if relocations are on */ \ + irqentry_nmi_exit(regs, state); \ + } else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && \ + firmware_has_feature(FW_FEATURE_LPAR) && \ + !radix_enabled()) { \ + /* no nmi_exit for a pseries hash guest \ + * taking a real mode exception */ \ + } else if (IS_ENABLED(CONFIG_KASAN)) { \ + /* no nmi_exit for KASAN in real mode */ \ + } else if (percpu_first_chunk_is_paged) { \ + /* no nmi_exit if percpu first chunk is not embedded */ \ + } else { \ + irqentry_nmi_exit(regs, state); \ + } \ \ return ret; \ } \ diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrup= t.c index f53d432f6087..7f67f0b9d627 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -24,10 +24,6 @@ unsigned long global_dbcr0[NR_CPUS]; #endif =20 -#if defined(CONFIG_PREEMPT_DYNAMIC) -DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched); 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Sun, 14 Dec 2025 13:04:32 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E43F420043; Sun, 14 Dec 2025 13:04:31 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C000320040; Sun, 14 Dec 2025 13:04:25 +0000 (GMT) Received: from li-1a3e774c-28e4-11b2-a85c-acc9f2883e29.ibm.com.com (unknown [9.124.210.21]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Sun, 14 Dec 2025 13:04:25 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, thuth@redhat.com, sshegde@linux.ibm.com, charlie@rivosinc.com, macro@orcam.me.uk, akpm@linux-foundation.org, ldv@strace.io, deller@gmx.de, ankur.a.arora@oracle.com, segher@kernel.crashing.org, tglx@linutronix.de, thomas.weissschuh@linutronix.de, peterz@infradead.org, menglong8.dong@gmail.com, bigeasy@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, atrajeev@linux.vnet.ibm.com, mark.barnett@arm.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 8/8] powerpc: Enable Generic Entry/Exit for syscalls. Date: Sun, 14 Dec 2025 18:32:44 +0530 Message-ID: <20251214130245.43664-9-mkchauras@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251214130245.43664-1-mkchauras@linux.ibm.com> References: <20251214130245.43664-1-mkchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: IKUSDUgTDjFlb6G0CpclGYfjyETjej8C X-Proofpoint-ORIG-GUID: Kv8K1I1OBoMTCmY46_q-haJoqlrj0Rgy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEzMDAyMyBTYWx0ZWRfXwzr0CBJV5wmy Ysgf7lVWO7oY6u5b/2UYV04Aw2exBXLkgx9+vUwv7MbozjKFSL+Xf9yGsd9TmmWhwpv85fM1N75 di418o8BUqn3Af5ZyEr30VoTrvU7XI9IMMtSlgfap+pQSsUja/9jEHG7jBd+qRRc0kIc+F4DoDJ pi5qSGXB/eMyV7OnvDU4hNcrRQmQNeMXVpa2XyoOEpJ7GkODA1yjLXVK4n+mRwDrtEUsGy17d+A 7VydArDM9FQKQ668uxltMOup6kifmQlj+33HZBA1QQ6vZMDYi+ZFZbhgG4aW2PKSQMeXuWBpBlv 0/RrAuEmDIsstrUlloZJAlH3DXaoWFTj3LIiFpBPBrQeS53Q8pgN99oQDbNANxkYNAhkHca+f0Z t7CoOBhGUIIVDsvL3gjocatV/lUi2A== X-Authority-Analysis: v=2.4 cv=L/MQguT8 c=1 sm=1 tr=0 ts=693eb5e5 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=N1XQQ8_H-WpO_rPlItIA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-14_03,2025-12-11_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 malwarescore=0 adultscore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 bulkscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512130023 Content-Type: text/plain; charset="utf-8" From: Mukesh Kumar Chaurasiya Convert the PowerPC syscall entry and exit paths to use the generic entry/exit framework by selecting GENERIC_ENTRY and integrating with the common syscall handling routines. This change transitions PowerPC away from its custom syscall entry and exit code to use the generic helpers such as: - syscall_enter_from_user_mode() - syscall_exit_to_user_mode() As part of this migration: - The architecture now selects GENERIC_ENTRY in Kconfig. - Old tracing, seccomp, and audit handling in ptrace.c is removed in favor of generic entry infrastructure. - interrupt.c and syscall.c are simplified to delegate context management and user exit handling to the generic entry path. - The new pt_regs field `exit_flags` introduced earlier is now used to carry per-syscall exit state flags (e.g. _TIF_RESTOREALL). This aligns PowerPC with the common entry code used by other architectures and reduces duplicated logic around syscall tracing, context tracking, and signal handling. The performance benchmarks from perf bench basic syscall are below: perf bench syscall usec/op | Test | With Patch | Without Patch | % Change | | --------------- | ---------- | ------------- | -------- | | getppid usec/op | 0.207795 | 0.210373 | -1.22% | | getpgid usec/op | 0.206282 | 0.211676 | -2.55% | | fork usec/op | 833.986 | 814.809 | +2.35% | | execve usec/op | 360.939 | 365.168 | -1.16% | perf bench syscall ops/sec | Test | With Patch | Without Patch | % Change | | --------------- | ---------- | ------------- | -------- | | getppid ops/sec | 48,12,433 | 47,53,459 | +1.24% | | getpgid ops/sec | 48,47,744 | 47,24,192 | +2.61% | | fork ops/sec | 1,199 | 1,227 | -2.28% | | execve ops/sec | 2,770 | 2,738 | +1.16% | IPI latency benchmark | Metric | With Patch | Without Patch | % Change | | ----------------------- | ---------------- | ---------------- | -------- | | Dry-run (ns) | 206,675.81 | 206,719.36 | -0.02% | | Self-IPI avg (ns) | 1,939,991.00 | 1,976,116.15 | -1.83% | | Self-IPI max (ns) | 3,533,718.93 | 3,582,650.33 | -1.37% | | Normal IPI avg (ns) | 111,110,034.23 | 110,513,373.51 | +0.54% | | Normal IPI max (ns) | 150,393,442.64 | 149,669,477.89 | +0.48% | | Broadcast IPI max (ns) | 3,978,231,022.96 | 4,359,916,859.46 | -8.73% | | Broadcast lock max (ns) | 4,025,425,714.49 | 4,384,956,730.83 | -8.20% | Thats very close to performance earlier with arch specific handling. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/Kconfig | 1 + arch/powerpc/include/asm/entry-common.h | 5 +- arch/powerpc/kernel/interrupt.c | 139 +++++++---------------- arch/powerpc/kernel/ptrace/ptrace.c | 141 ------------------------ arch/powerpc/kernel/signal.c | 10 +- arch/powerpc/kernel/syscall.c | 119 +------------------- 6 files changed, 49 insertions(+), 366 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index b0c602c3bbe1..a4330775b254 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -203,6 +203,7 @@ config PPC select GENERIC_CPU_AUTOPROBE select GENERIC_CPU_VULNERABILITIES if PPC_BARRIER_NOSPEC select GENERIC_EARLY_IOREMAP + select GENERIC_ENTRY select GENERIC_GETTIMEOFDAY select GENERIC_IDLE_POLL_SETUP select GENERIC_IOREMAP diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include= /asm/entry-common.h index e2ae7416dee1..77129174f882 100644 --- a/arch/powerpc/include/asm/entry-common.h +++ b/arch/powerpc/include/asm/entry-common.h @@ -3,7 +3,7 @@ #ifndef _ASM_PPC_ENTRY_COMMON_H #define _ASM_PPC_ENTRY_COMMON_H =20 -#ifdef CONFIG_GENERIC_IRQ_ENTRY +#ifdef CONFIG_GENERIC_ENTRY =20 #include #include @@ -217,9 +217,6 @@ static inline void arch_interrupt_enter_prepare(struct = pt_regs *regs) =20 if (user_mode(regs)) { kuap_lock(); - CT_WARN_ON(ct_state() !=3D CT_STATE_USER); - user_exit_irqoff(); - account_cpu_user_entry(); account_stolen_time(); } else { diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrup= t.c index 7f67f0b9d627..7d5cd4b5a610 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 #include +#include #include #include #include @@ -73,79 +74,6 @@ static notrace __always_inline bool prep_irq_for_enabled= _exit(bool restartable) return true; } =20 -static notrace unsigned long -interrupt_exit_user_prepare_main(unsigned long ret, struct pt_regs *regs) -{ - unsigned long ti_flags; - -again: - ti_flags =3D read_thread_flags(); - while (unlikely(ti_flags & (_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM))) { - local_irq_enable(); - if (ti_flags & (_TIF_NEED_RESCHED | _TIF_NEED_RESCHED_LAZY)) { - schedule(); - } else { - /* - * SIGPENDING must restore signal handler function - * argument GPRs, and some non-volatiles (e.g., r1). - * Restore all for now. This could be made lighter. - */ - if (ti_flags & _TIF_SIGPENDING) - ret |=3D _TIF_RESTOREALL; - do_notify_resume(regs, ti_flags); - } - local_irq_disable(); - ti_flags =3D read_thread_flags(); - } - - if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && IS_ENABLED(CONFIG_PPC_FPU)) { - if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && - unlikely((ti_flags & _TIF_RESTORE_TM))) { - restore_tm_state(regs); - } else { - unsigned long mathflags =3D MSR_FP; - - if (cpu_has_feature(CPU_FTR_VSX)) - mathflags |=3D MSR_VEC | MSR_VSX; - else if (cpu_has_feature(CPU_FTR_ALTIVEC)) - mathflags |=3D MSR_VEC; - - /* - * If userspace MSR has all available FP bits set, - * then they are live and no need to restore. If not, - * it means the regs were given up and restore_math - * may decide to restore them (to avoid taking an FP - * fault). - */ - if ((regs->msr & mathflags) !=3D mathflags) - restore_math(regs); - } - } - - check_return_regs_valid(regs); - - user_enter_irqoff(); - if (!prep_irq_for_enabled_exit(true)) { - user_exit_irqoff(); - local_irq_enable(); - local_irq_disable(); - goto again; - } - -#ifdef CONFIG_PPC_TRANSACTIONAL_MEM - local_paca->tm_scratch =3D regs->msr; -#endif - - booke_load_dbcr0(); - - account_cpu_user_exit(); - - /* Restore user access locks last */ - kuap_user_restore(regs); - - return ret; -} - /* * This should be called after a syscall returns, with r3 the return value * from the syscall. If this function returns non-zero, the system call @@ -160,17 +88,12 @@ notrace unsigned long syscall_exit_prepare(unsigned lo= ng r3, long scv) { unsigned long ti_flags; - unsigned long ret =3D 0; bool is_not_scv =3D !IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !scv; =20 - CT_WARN_ON(ct_state() =3D=3D CT_STATE_USER); - kuap_assert_locked(); =20 regs->result =3D r3; - - /* Check whether the syscall is issued inside a restartable sequence */ - rseq_syscall(regs); + regs->exit_flags =3D 0; =20 ti_flags =3D read_thread_flags(); =20 @@ -183,7 +106,7 @@ notrace unsigned long syscall_exit_prepare(unsigned lon= g r3, =20 if (unlikely(ti_flags & _TIF_PERSYSCALL_MASK)) { if (ti_flags & _TIF_RESTOREALL) - ret =3D _TIF_RESTOREALL; + regs->exit_flags =3D _TIF_RESTOREALL; else regs->gpr[3] =3D r3; clear_bits(_TIF_PERSYSCALL_MASK, ¤t_thread_info()->flags); @@ -192,18 +115,28 @@ notrace unsigned long syscall_exit_prepare(unsigned l= ong r3, } =20 if (unlikely(ti_flags & _TIF_SYSCALL_DOTRACE)) { - do_syscall_trace_leave(regs); - ret |=3D _TIF_RESTOREALL; + regs->exit_flags |=3D _TIF_RESTOREALL; } =20 - local_irq_disable(); - ret =3D interrupt_exit_user_prepare_main(ret, regs); + syscall_exit_to_user_mode(regs); + +again: + user_enter_irqoff(); + if (!prep_irq_for_enabled_exit(true)) { + user_exit_irqoff(); + local_irq_enable(); + local_irq_disable(); + goto again; + } + + /* Restore user access locks last */ + kuap_user_restore(regs); =20 #ifdef CONFIG_PPC64 - regs->exit_result =3D ret; + regs->exit_result =3D regs->exit_flags; #endif =20 - return ret; + return regs->exit_flags; } =20 #ifdef CONFIG_PPC64 @@ -223,13 +156,16 @@ notrace unsigned long syscall_exit_restart(unsigned l= ong r3, struct pt_regs *reg set_kuap(AMR_KUAP_BLOCKED); #endif =20 - trace_hardirqs_off(); - user_exit_irqoff(); - account_cpu_user_entry(); - - BUG_ON(!user_mode(regs)); +again: + user_enter_irqoff(); + if (!prep_irq_for_enabled_exit(true)) { + user_exit_irqoff(); + local_irq_enable(); + local_irq_disable(); + goto again; + } =20 - regs->exit_result =3D interrupt_exit_user_prepare_main(regs->exit_result,= regs); + regs->exit_result |=3D regs->exit_flags; =20 return regs->exit_result; } @@ -241,7 +177,6 @@ notrace unsigned long interrupt_exit_user_prepare(struc= t pt_regs *regs) =20 BUG_ON(regs_is_unrecoverable(regs)); BUG_ON(regs_irqs_disabled(regs)); - CT_WARN_ON(ct_state() =3D=3D CT_STATE_USER); =20 /* * We don't need to restore AMR on the way back to userspace for KUAP. @@ -250,8 +185,21 @@ notrace unsigned long interrupt_exit_user_prepare(stru= ct pt_regs *regs) kuap_assert_locked(); =20 local_irq_disable(); + regs->exit_flags =3D 0; +again: + check_return_regs_valid(regs); + user_enter_irqoff(); + if (!prep_irq_for_enabled_exit(true)) { + user_exit_irqoff(); + local_irq_enable(); + local_irq_disable(); + goto again; + } + + /* Restore user access locks last */ + kuap_user_restore(regs); =20 - ret =3D interrupt_exit_user_prepare_main(0, regs); + ret =3D regs->exit_flags; =20 #ifdef CONFIG_PPC64 regs->exit_result =3D ret; @@ -293,8 +241,6 @@ notrace unsigned long interrupt_exit_kernel_prepare(str= uct pt_regs *regs) /* Returning to a kernel context with local irqs enabled. */ WARN_ON_ONCE(!(regs->msr & MSR_EE)); again: - if (need_irq_preemption()) - irqentry_exit_cond_resched(); =20 check_return_regs_valid(regs); =20 @@ -364,7 +310,6 @@ notrace unsigned long interrupt_exit_user_restart(struc= t pt_regs *regs) #endif =20 trace_hardirqs_off(); - user_exit_irqoff(); account_cpu_user_entry(); =20 BUG_ON(!user_mode(regs)); diff --git a/arch/powerpc/kernel/ptrace/ptrace.c b/arch/powerpc/kernel/ptra= ce/ptrace.c index 2134b6d155ff..316d4f5ead8e 100644 --- a/arch/powerpc/kernel/ptrace/ptrace.c +++ b/arch/powerpc/kernel/ptrace/ptrace.c @@ -21,9 +21,6 @@ #include #include =20 -#define CREATE_TRACE_POINTS -#include - #include "ptrace-decl.h" =20 /* @@ -195,144 +192,6 @@ long arch_ptrace(struct task_struct *child, long requ= est, return ret; } =20 -#ifdef CONFIG_SECCOMP -static int do_seccomp(struct pt_regs *regs) -{ - if (!test_thread_flag(TIF_SECCOMP)) - return 0; - - /* - * The ABI we present to seccomp tracers is that r3 contains - * the syscall return value and orig_gpr3 contains the first - * syscall parameter. This is different to the ptrace ABI where - * both r3 and orig_gpr3 contain the first syscall parameter. - */ - regs->gpr[3] =3D -ENOSYS; - - /* - * We use the __ version here because we have already checked - * TIF_SECCOMP. If this fails, there is nothing left to do, we - * have already loaded -ENOSYS into r3, or seccomp has put - * something else in r3 (via SECCOMP_RET_ERRNO/TRACE). - */ - if (__secure_computing()) - return -1; - - /* - * The syscall was allowed by seccomp, restore the register - * state to what audit expects. - * Note that we use orig_gpr3, which means a seccomp tracer can - * modify the first syscall parameter (in orig_gpr3) and also - * allow the syscall to proceed. - */ - regs->gpr[3] =3D regs->orig_gpr3; - - return 0; -} -#else -static inline int do_seccomp(struct pt_regs *regs) { return 0; } -#endif /* CONFIG_SECCOMP */ - -/** - * do_syscall_trace_enter() - Do syscall tracing on kernel entry. - * @regs: the pt_regs of the task to trace (current) - * - * Performs various types of tracing on syscall entry. This includes secco= mp, - * ptrace, syscall tracepoints and audit. - * - * The pt_regs are potentially visible to userspace via ptrace, so their - * contents is ABI. - * - * One or more of the tracers may modify the contents of pt_regs, in parti= cular - * to modify arguments or even the syscall number itself. - * - * It's also possible that a tracer can choose to reject the system call. = In - * that case this function will return an illegal syscall number, and will= put - * an appropriate return value in regs->r3. - * - * Return: the (possibly changed) syscall number. - */ -long do_syscall_trace_enter(struct pt_regs *regs) -{ - u32 flags; - - flags =3D read_thread_flags() & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE); - - if (flags) { - int rc =3D ptrace_report_syscall_entry(regs); - - if (unlikely(flags & _TIF_SYSCALL_EMU)) { - /* - * A nonzero return code from - * ptrace_report_syscall_entry() tells us to prevent - * the syscall execution, but we are not going to - * execute it anyway. - * - * Returning -1 will skip the syscall execution. We want - * to avoid clobbering any registers, so we don't goto - * the skip label below. - */ - return -1; - } - - if (rc) { - /* - * The tracer decided to abort the syscall. Note that - * the tracer may also just change regs->gpr[0] to an - * invalid syscall number, that is handled below on the - * exit path. - */ - goto skip; - } - } - - /* Run seccomp after ptrace; allow it to set gpr[3]. */ - if (do_seccomp(regs)) - return -1; - - /* Avoid trace and audit when syscall is invalid. */ - if (regs->gpr[0] >=3D NR_syscalls) - goto skip; - - if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) - trace_sys_enter(regs, regs->gpr[0]); - - if (!is_32bit_task()) - audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4], - regs->gpr[5], regs->gpr[6]); - else - audit_syscall_entry(regs->gpr[0], - regs->gpr[3] & 0xffffffff, - regs->gpr[4] & 0xffffffff, - regs->gpr[5] & 0xffffffff, - regs->gpr[6] & 0xffffffff); - - /* Return the possibly modified but valid syscall number */ - return regs->gpr[0]; - -skip: - /* - * If we are aborting explicitly, or if the syscall number is - * now invalid, set the return value to -ENOSYS. - */ - regs->gpr[3] =3D -ENOSYS; - return -1; -} - -void do_syscall_trace_leave(struct pt_regs *regs) -{ - int step; - - audit_syscall_exit(regs); - - if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) - trace_sys_exit(regs, regs->result); - - step =3D test_thread_flag(TIF_SINGLESTEP); - if (step || test_thread_flag(TIF_SYSCALL_TRACE)) - ptrace_report_syscall_exit(regs, step); -} - void __init pt_regs_check(void); =20 /* diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c index 719930cf4ae1..9f1847b4742e 100644 --- a/arch/powerpc/kernel/signal.c +++ b/arch/powerpc/kernel/signal.c @@ -6,6 +6,7 @@ * Extracted from signal_32.c and signal_64.c */ =20 +#include #include #include #include @@ -22,11 +23,6 @@ =20 #include "signal.h" =20 -/* This will be removed */ -#ifdef CONFIG_GENERIC_ENTRY -#include -#endif /* CONFIG_GENERIC_ENTRY */ - #ifdef CONFIG_VSX unsigned long copy_fpr_to_user(void __user *to, struct task_struct *task) @@ -374,11 +370,9 @@ void signal_fault(struct task_struct *tsk, struct pt_r= egs *regs, task_pid_nr(tsk), where, ptr, regs->nip, regs->link); } =20 -#ifdef CONFIG_GENERIC_ENTRY void arch_do_signal_or_restart(struct pt_regs *regs) { BUG_ON(regs !=3D current->thread.regs); - local_paca->generic_fw_flags |=3D GFW_RESTORE_ALL; + regs->exit_flags |=3D _TIF_RESTOREALL; do_signal(current); } -#endif /* CONFIG_GENERIC_ENTRY */ diff --git a/arch/powerpc/kernel/syscall.c b/arch/powerpc/kernel/syscall.c index 9f03a6263fb4..df1c9a8d62bc 100644 --- a/arch/powerpc/kernel/syscall.c +++ b/arch/powerpc/kernel/syscall.c @@ -3,6 +3,7 @@ #include #include #include +#include =20 #include #include @@ -18,124 +19,10 @@ notrace long system_call_exception(struct pt_regs *reg= s, unsigned long r0) long ret; syscall_fn f; =20 - kuap_lock(); - add_random_kstack_offset(); + r0 =3D syscall_enter_from_user_mode(regs, r0); =20 - if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) - BUG_ON(irq_soft_mask_return() !=3D IRQS_ALL_DISABLED); - - trace_hardirqs_off(); /* finish reconciling */ - - CT_WARN_ON(ct_state() =3D=3D CT_STATE_KERNEL); - user_exit_irqoff(); - - BUG_ON(regs_is_unrecoverable(regs)); - BUG_ON(!user_mode(regs)); - BUG_ON(regs_irqs_disabled(regs)); - -#ifdef CONFIG_PPC_PKEY - if (mmu_has_feature(MMU_FTR_PKEY)) { - unsigned long amr, iamr; - bool flush_needed =3D false; - /* - * When entering from userspace we mostly have the AMR/IAMR - * different from kernel default values. Hence don't compare. - */ - amr =3D mfspr(SPRN_AMR); - iamr =3D mfspr(SPRN_IAMR); - regs->amr =3D amr; - regs->iamr =3D iamr; - if (mmu_has_feature(MMU_FTR_KUAP)) { - mtspr(SPRN_AMR, AMR_KUAP_BLOCKED); - flush_needed =3D true; - } - if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) { - mtspr(SPRN_IAMR, AMR_KUEP_BLOCKED); - flush_needed =3D true; - } - if (flush_needed) - isync(); - } else -#endif - kuap_assert_locked(); - - booke_restore_dbcr0(); - - account_cpu_user_entry(); - - account_stolen_time(); - - /* - * This is not required for the syscall exit path, but makes the - * stack frame look nicer. If this was initialised in the first stack - * frame, or if the unwinder was taught the first stack frame always - * returns to user with IRQS_ENABLED, this store could be avoided! - */ - irq_soft_mask_regs_set_state(regs, IRQS_ENABLED); - - /* - * If system call is called with TM active, set _TIF_RESTOREALL to - * prevent RFSCV being used to return to userspace, because POWER9 - * TM implementation has problems with this instruction returning to - * transactional state. Final register values are not relevant because - * the transaction will be aborted upon return anyway. Or in the case - * of unsupported_scv SIGILL fault, the return state does not much - * matter because it's an edge case. - */ - if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && - unlikely(MSR_TM_TRANSACTIONAL(regs->msr))) - set_bits(_TIF_RESTOREALL, ¤t_thread_info()->flags); - - /* - * If the system call was made with a transaction active, doom it and - * return without performing the system call. Unless it was an - * unsupported scv vector, in which case it's treated like an illegal - * instruction. - */ -#ifdef CONFIG_PPC_TRANSACTIONAL_MEM - if (unlikely(MSR_TM_TRANSACTIONAL(regs->msr)) && - !trap_is_unsupported_scv(regs)) { - /* Enable TM in the kernel, and disable EE (for scv) */ - hard_irq_disable(); - mtmsr(mfmsr() | MSR_TM); - - /* tabort, this dooms the transaction, nothing else */ - asm volatile(".long 0x7c00071d | ((%0) << 16)" - :: "r"(TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)); - - /* - * Userspace will never see the return value. Execution will - * resume after the tbegin. of the aborted transaction with the - * checkpointed register state. A context switch could occur - * or signal delivered to the process before resuming the - * doomed transaction context, but that should all be handled - * as expected. - */ - return -ENOSYS; - } -#endif // CONFIG_PPC_TRANSACTIONAL_MEM - - local_irq_enable(); - - if (unlikely(read_thread_flags() & _TIF_SYSCALL_DOTRACE)) { - if (unlikely(trap_is_unsupported_scv(regs))) { - /* Unsupported scv vector */ - _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); - return regs->gpr[3]; - } - /* - * We use the return value of do_syscall_trace_enter() as the - * syscall number. If the syscall was rejected for any reason - * do_syscall_trace_enter() returns an invalid syscall number - * and the test against NR_syscalls will fail and the return - * value to be used is in regs->gpr[3]. - */ - r0 =3D do_syscall_trace_enter(regs); - if (unlikely(r0 >=3D NR_syscalls)) - return regs->gpr[3]; - - } else if (unlikely(r0 >=3D NR_syscalls)) { + if (unlikely(r0 >=3D NR_syscalls)) { if (unlikely(trap_is_unsupported_scv(regs))) { /* Unsupported scv vector */ _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); --=20 2.52.0