From nobody Tue Dec 16 14:57:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70BF728507B; Sun, 14 Dec 2025 22:15:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765750553; cv=none; b=oKmQ57OB2iWNh1FDibmTk3oT3nNW1UdHYg8Gi/B+6PXktSDLTjTQAGQZP5yC2O4c2X3Mc4KZ3i5IYaV7Q6xygoc6XCUE666l3A6jz/Hx+3wBTkFUzI55cRta7X4RAlL8C7SG4o/97x472W63dN0lo/WrY8usnxaryjm7ATEOv3Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765750553; c=relaxed/simple; bh=tU2+6Pb/oX5YAV0ZTflaY/39SJdBwWrzv2W2jOQyNP8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WQTCoBBqaEPYaukjI9VADsNFDgcMIoGCQlFZydMCMKmsXNIiFFwS9E/n0NOQZqQUVpW6eddpHYLDZ/O1ovJk5a9hmtQKHdnElZQA4FzSInkTqbO0PkxojWio3wujuxxgb+GW1TIc5IGFV/yCvKgsmxX6gn5n+/a0SO7abkVMI40= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BZtRIgVM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BZtRIgVM" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2186EC4AF09; Sun, 14 Dec 2025 22:15:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1765750553; bh=tU2+6Pb/oX5YAV0ZTflaY/39SJdBwWrzv2W2jOQyNP8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=BZtRIgVMl+mkuEaQhFGg18fD1YbUL6hJcO35N+/DxTkBp1jSvlxDTrw1ooJfJuMBO h5EvtpX+MfNA/oXPm3niHKFpYvpE8vTz2toGz74BYIG3BxZmR2mj5LGeerwdRxEDdd 9qiBj+ZXnLHYfmbdDS6SXZrrgApG5JZ9zL9xzljQ5cs9QcV15gAbECRsR/FTgI0ZqR qnT9DlOZHql+cZezuoaokgV1PLYjE2/d3XY56IILj49+CWAwdWYqYxacfElKOZpodV OYpjQQgKqZdWVXCtd9kzGPKXuO7vcYBsF6fIGovIB1k93dtzXYMejwdQeFzvskrxeR 82FVXID0DkIGg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12CCFD5B16C; Sun, 14 Dec 2025 22:15:53 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Sun, 14 Dec 2025 23:15:38 +0100 Subject: [PATCH RFC 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251214-dwmac_multi_irq-v1-2-36562ab0e9f7@oss.nxp.com> References: <20251214-dwmac_multi_irq-v1-0-36562ab0e9f7@oss.nxp.com> In-Reply-To: <20251214-dwmac_multi_irq-v1-0-36562ab0e9f7@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765750551; l=2770; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=IldkiiaE2HL3rzaW8zGi6tUPu8CmlMWAI7ZTb3y524w=; b=9RpivU02+xR8xHnBlK8CbtNluzrfS5Bal86SQwNE5Hv6SZvkQ9kUV3grTZEI1ic3xTNv5SLmT AcuZEZ1y4alD3hEIQQtHMiygiTY76zMCN1SlyDfY7GBBXC18x1n3JEO X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The DWMAC IP on supported SoCs has connected queue-based IRQ lines. Signed-off-by: Jan Petrous (OSS) --- .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 40 ++++++++++++++++++= +--- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Doc= umentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 2b8b74c5feec..b5e42fa49110 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -33,10 +33,22 @@ properties: - description: GMAC PHY mode control register =20 interrupts: - maxItems: 1 + minItems: 11 + maxItems: 11 =20 interrupt-names: - const: macirq + - items: + - const: macirq + - const: rx-queue-0 + - const: tx-queue-0 + - const: rx-queue-1 + - const: tx-queue-1 + - const: rx-queue-2 + - const: tx-queue-2 + - const: rx-queue-3 + - const: tx-queue-3 + - const: rx-queue-4 + - const: tx-queue-4 =20 clocks: items: @@ -75,8 +87,28 @@ examples: reg =3D <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */ <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4", snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; clocks =3D <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>; --=20 2.47.0