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[5.94.28.5]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47a8f4f4150sm106040995e9.11.2025.12.13.15.09.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Dec 2025 15:09:28 -0800 (PST) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/6] arm64: dts: imx8mp-var-som: Move USDHC2 support to Symphony carrier Date: Sun, 14 Dec 2025 00:09:01 +0100 Message-ID: <20251213230909.16810-2-stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251213230909.16810-1-stefano.r@variscite.com> References: <20251213230909.16810-1-stefano.r@variscite.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The VAR-SOM-MX8MP module does not include a microSD slot connected to USDHC2. The USDHC2 interface is routed only on the Symphony carrier board, and it may optionally be used or omitted depending on the customer's carrier design. Move the USDHC2 node, its regulators, pinctrl groups and related GPIOs from the SOM device tree to the Symphony carrier DTS, keeping the SOM description limited to hardware populated on the module. Signed-off-by: Stefano Radaelli --- .../dts/freescale/imx8mp-var-som-symphony.dts | 77 +++++++++++++++++++ .../boot/dts/freescale/imx8mp-var-som.dtsi | 75 ------------------ 2 files changed, 77 insertions(+), 75 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/ar= ch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 36d3eb865202..ea3c193bb684 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -8,4 +8,81 @@ / { model =3D "Variscite VAR-SOM-MX8M-PLUS on Symphony-Board"; compatible =3D "variscite,var-som-mx8mp-symphony", "variscite,var-som-mx8= mp", "fsl,imx8mp"; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "VSD_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&gpio4 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us =3D <100>; + off-on-delay-us =3D <12000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible =3D "regulator-gpio"; + regulator-name =3D "VSD_VSEL"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&gpio2 12 GPIO_ACTIVE_HIGH>; + states =3D <3300000 0x0 1800000 0x1>; + vin-supply =3D <&ldo5>; + }; +}; + +/* SD-card */ +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio1 14 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + vqmmc-supply =3D <®_usdhc2_vqmmc>; + bus-width =3D <4>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64= /boot/dts/freescale/imx8mp-var-som.dtsi index 29f080904482..949d9878f395 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -35,27 +35,6 @@ memory@40000000 { <0x1 0x00000000 0 0xc0000000>; }; =20 - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible =3D "regulator-fixed"; - regulator-name =3D "VSD_3V3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - gpios =3D <&gpio4 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us =3D <100>; - off-on-delay-us =3D <12000>; - }; - - reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { - compatible =3D "regulator-gpio"; - regulator-name =3D "VSD_VSEL"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <3300000>; - gpios =3D <&gpio2 12 GPIO_ACTIVE_HIGH>; - states =3D <3300000 0x0 1800000 0x1>; - vin-supply =3D <&ldo5>; - }; - reg_phy_supply: regulator-phy-supply { compatible =3D "regulator-fixed"; regulator-name =3D "phy-supply"; @@ -271,19 +250,6 @@ &uart2 { status =3D "okay"; }; =20 -/* SD-card */ -&usdhc2 { - pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; - pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios =3D <&gpio1 14 GPIO_ACTIVE_LOW>; - vmmc-supply =3D <®_usdhc2_vmmc>; - vqmmc-supply =3D <®_usdhc2_vqmmc>; - bus-width =3D <4>; - status =3D "okay"; -}; - /* eMMC */ &usdhc3 { pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; @@ -358,47 +324,6 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX = 0x40 >; }; =20 - pinctrl_usdhc2_gpio: usdhc2-gpiogrp { - fsl,pins =3D < - MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 = 0x1c4 - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 = 0x10 - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 = 0xc0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins =3D < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK = 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD = 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 = 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 = 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 = 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 = 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins =3D < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK = 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD = 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 = 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 = 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 = 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 = 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins =3D < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK = 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD = 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 = 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 = 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 = 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 = 0x1d6 - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins =3D < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 --=20 2.47.3