From nobody Sun Dec 14 05:56:52 2025 Received: from out198-2.us.a.mail.aliyun.com (out198-2.us.a.mail.aliyun.com [47.90.198.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 169B623EAB3; Sat, 13 Dec 2025 07:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765611561; cv=none; b=AGTbg0kb2skNZYuBAJf1L/XPqIgy7/hOZjfxeeaOh8jHH6XTLlXo8kmSgGZE2vgIWnPnSeqLsWoBAX9U+6PfPQvTQdibu5LZTykBB8gjViDFmIsQIjRXqFM1xoLwVje4+0UFNduWThZ7Gg533Qv4lw5RkcwRpHJpeaSqM55QWQE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765611561; c=relaxed/simple; bh=PWVX4P/C70Eb5WxPZWLOS8flK6NgL+KCQmC97/5fE7U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LlM9FTFYcaZV9zPjQfDYyE13nwQ4l9x3Z8t7yOrlznRJOuwN1rb8ZVjw5VQ94aCtIZCAAM2AjS1jtaKTKYCNb224+Sg6b1Cr8IGeHy2I+pAUn0JCPVWjS9gQAxuS4cMonVH0EVGekzUMYmpwvQIMe/jIf2pSfSceYuoC1b3FwZM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=47.90.198.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net Received: from localhost.localdomain(mailfrom:shenxiaochen@open-hieco.net fp:SMTPD_---.fjNqpoN_1765611537 cluster:ay29) by smtp.aliyun-inc.com; Sat, 13 Dec 2025 15:38:59 +0800 From: Xiaochen Shen To: tony.luck@intel.com, reinette.chatre@intel.com, bp@alien8.de, fenghuay@nvidia.com, shuah@kernel.org, skhan@linuxfoundation.org Cc: babu.moger@amd.com, james.morse@arm.com, Dave.Martin@arm.com, x86@kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, shenxiaochen@open-hieco.net Subject: [PATCH v4 1/4] selftests/resctrl: Fix a division by zero error on Hygon Date: Sat, 13 Dec 2025 15:38:08 +0800 Message-ID: <20251213073811.3016864-2-shenxiaochen@open-hieco.net> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251213073811.3016864-1-shenxiaochen@open-hieco.net> References: <20251213073811.3016864-1-shenxiaochen@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit a1cd99e700ec ("selftests/resctrl: Adjust effective L3 cache size with SNC= enabled") introduced the snc_nodes_per_l3_cache() function to detect the Intel Sub-NUMA Clustering (SNC) feature by comparing #CPUs in node0 with #CPUs sharing LLC with CPU0. The function was designed to return: (1) >1: SNC mode is enabled. (2) 1: SNC mode is not enabled or not supported. However, on certain Hygon CPUs, #CPUs sharing LLC with CPU0 is actually less than #CPUs in node0. This results in snc_nodes_per_l3_cache() returning 0 (calculated as cache_cpus / node_cpus). This leads to a division by zero error in get_cache_size(): *cache_size /=3D snc_nodes_per_l3_cache(); Causing the resctrl selftest to fail with: "Floating point exception (core dumped)" Fix the issue by ensuring snc_nodes_per_l3_cache() returns 1 when SNC mode is not supported on the platform. Fixes: a1cd99e700ec ("selftests/resctrl: Adjust effective L3 cache size wit= h SNC enabled") Signed-off-by: Xiaochen Shen Reviewed-by: Reinette Chatre Reviewed-by: Fenghua Yu --- tools/testing/selftests/resctrl/resctrlfs.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/testing/selftests/resctrl/resctrlfs.c b/tools/testing/se= lftests/resctrl/resctrlfs.c index 195f04c4d158..b9c1bfb6cc02 100644 --- a/tools/testing/selftests/resctrl/resctrlfs.c +++ b/tools/testing/selftests/resctrl/resctrlfs.c @@ -243,6 +243,16 @@ int snc_nodes_per_l3_cache(void) } snc_mode =3D cache_cpus / node_cpus; =20 + /* + * On some platforms (e.g. Hygon), + * cache_cpus < node_cpus, the calculated snc_mode is 0. + * + * Set snc_mode =3D 1 to indicate that SNC mode is not + * supported on the platform. + */ + if (!snc_mode) + snc_mode =3D 1; + if (snc_mode > 1) ksft_print_msg("SNC-%d mode discovered.\n", snc_mode); } --=20 2.47.3 From nobody Sun Dec 14 05:56:52 2025 Received: from out28-172.mail.aliyun.com (out28-172.mail.aliyun.com [115.124.28.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3436A219E8; Sat, 13 Dec 2025 07:39:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765611559; cv=none; b=QJfkpTgeuZxveNvS5EMn2Lqil3T/hIyv1UM/X6Wit0xqQyyTuty+sLFl9goiY7b1CsFBBswkM4Y/FrQZ9D3VZWvmrL6vr2IJIAUFP6dJOfi3CMmxQlmAdMyuaoScEecQpirTKZD5quuD91VDHJvP9YGZkCIEiqk0ElhAOKVr5GE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765611559; c=relaxed/simple; bh=Ob1z+21rD4i0I/w7vo7MH52MRJO6sFsR8hG+Frj/3Mo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e/th00CKqVNrfg6CrsOW/9oGNR4gnQU/CEF57xt2Jz67SqZr0BZgAfjaweXHhgpg4RC7ykt483DgFJ5jfG30oS/klYCuVe8yQ1KPEZcS+44ok5cpT9hr2PN741syVR+ys4yyYR1yyoQVaiO2VFM5tf+3AyoQp6vAZruWgIi5FNM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net Received: from localhost.localdomain(mailfrom:shenxiaochen@open-hieco.net fp:SMTPD_---.fjNqpry_1765611540 cluster:ay29) by smtp.aliyun-inc.com; Sat, 13 Dec 2025 15:39:02 +0800 From: Xiaochen Shen To: tony.luck@intel.com, reinette.chatre@intel.com, bp@alien8.de, fenghuay@nvidia.com, shuah@kernel.org, skhan@linuxfoundation.org Cc: babu.moger@amd.com, james.morse@arm.com, Dave.Martin@arm.com, x86@kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, shenxiaochen@open-hieco.net Subject: [PATCH v4 2/4] selftests/resctrl: Define CPU vendor IDs as bits to match usage Date: Sat, 13 Dec 2025 15:38:09 +0800 Message-ID: <20251213073811.3016864-3-shenxiaochen@open-hieco.net> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251213073811.3016864-1-shenxiaochen@open-hieco.net> References: <20251213073811.3016864-1-shenxiaochen@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CPU vendor IDs are required to be unique bits because they're used for vendor_specific bitmask in the struct resctrl_test. Consider for example their usage in test_vendor_specific_check(): return get_vendor() & test->vendor_specific However, the definitions of CPU vendor IDs in file resctrl.h is quite subtle as a bitmask value: #define ARCH_INTEL 1 #define ARCH_AMD 2 A clearer and more maintainable approach is to define these CPU vendor IDs using BIT(). This ensures each vendor corresponds to a distinct bit and makes it obvious when adding new vendor IDs. Accordingly, update the return types of detect_vendor() and get_vendor() from 'int' to 'unsigned int' to align with their usage as bitmask values and to prevent potentially risky type conversions. Furthermore, introduce a bool flag 'initialized' to simplify the get_vendor() -> detect_vendor() logic. This ensures the vendor ID is detected only once and resolves the ambiguity of using the same variable 'vendor' both as a value and as a state. Suggested-by: Reinette Chatre Suggested-by: Fenghua Yu Signed-off-by: Xiaochen Shen --- tools/testing/selftests/resctrl/resctrl.h | 7 ++--- .../testing/selftests/resctrl/resctrl_tests.c | 26 +++++++++++++------ 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/self= tests/resctrl/resctrl.h index 3c51bdac2dfa..4f9c7d04c98d 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -23,6 +23,7 @@ #include #include #include +#include #include "kselftest.h" =20 #define MB (1024 * 1024) @@ -36,8 +37,8 @@ * Define as bits because they're used for vendor_specific bitmask in * the struct resctrl_test. */ -#define ARCH_INTEL 1 -#define ARCH_AMD 2 +#define ARCH_INTEL BIT(0) +#define ARCH_AMD BIT(1) =20 #define END_OF_TESTS 1 =20 @@ -163,7 +164,7 @@ extern int snc_unreliable; extern char llc_occup_path[1024]; =20 int snc_nodes_per_l3_cache(void); -int get_vendor(void); +unsigned int get_vendor(void); bool check_resctrlfs_support(void); int filter_dmesg(void); int get_domain_id(const char *resource, int cpu_no, int *domain_id); diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testin= g/selftests/resctrl/resctrl_tests.c index 5154ffd821c4..980ecf2bcf10 100644 --- a/tools/testing/selftests/resctrl/resctrl_tests.c +++ b/tools/testing/selftests/resctrl/resctrl_tests.c @@ -23,16 +23,24 @@ static struct resctrl_test *resctrl_tests[] =3D { &l2_noncont_cat_test, }; =20 -static int detect_vendor(void) +static unsigned int detect_vendor(void) { - FILE *inf =3D fopen("/proc/cpuinfo", "r"); - int vendor_id =3D 0; + FILE *inf; + static unsigned int vendor_id; char *s =3D NULL; char *res; + static bool initialized; =20 - if (!inf) + if (initialized) return vendor_id; =20 + inf =3D fopen("/proc/cpuinfo", "r"); + if (!inf) { + vendor_id =3D 0; + initialized =3D true; + return vendor_id; + } + res =3D fgrep(inf, "vendor_id"); =20 if (res) @@ -45,15 +53,17 @@ static int detect_vendor(void) =20 fclose(inf); free(res); + + initialized =3D true; return vendor_id; } =20 -int get_vendor(void) +unsigned int get_vendor(void) { - static int vendor =3D -1; + unsigned int vendor; + + vendor =3D detect_vendor(); =20 - if (vendor =3D=3D -1) - vendor =3D detect_vendor(); if (vendor =3D=3D 0) ksft_print_msg("Can not get vendor info...\n"); =20 --=20 2.47.3 From nobody Sun Dec 14 05:56:52 2025 Received: from out28-52.mail.aliyun.com (out28-52.mail.aliyun.com [115.124.28.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5BD2214A64; Sat, 13 Dec 2025 07:39:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765611558; cv=none; b=ZnOY2kkJsmIZb+Qcvrv6PHHKlYfUDDQMmjRs/yYkGI7kU+C4hYd80Cm/ZNbGr10j55ZRmJpZPW8jErxqRYRvbOuPf3jKohfhw8TCe91XdAQtd27KtR1JzQox6I9ZZ1qRVJFGr4Y7pgbJPOWkuxONXEj+01gXrRmPfbMqVXmTgwU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765611558; c=relaxed/simple; bh=0Ca7myKC8kmKRiG/2n/eciaKr7dyRWmpXAVFSAJLv3A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ja1peKOZFpWK5V+ZyfJMvL7cP1Bt1IPvRrmdqlfzYYKkpHTvxGF27j3k1EnFDUb5+arQIfxiIzl9ZbDRF1OcA/C9buI+BtIE7NQ3wD8MrdBi0nCgBfLB6QK/XCViPtZ2DOOOl1VT4ed/m46pvRa7aCoHpfrlZhWoHU5gUN30IR8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net Received: from localhost.localdomain(mailfrom:shenxiaochen@open-hieco.net fp:SMTPD_---.fjNqpvI_1765611543 cluster:ay29) by smtp.aliyun-inc.com; Sat, 13 Dec 2025 15:39:05 +0800 From: Xiaochen Shen To: tony.luck@intel.com, reinette.chatre@intel.com, bp@alien8.de, fenghuay@nvidia.com, shuah@kernel.org, skhan@linuxfoundation.org Cc: babu.moger@amd.com, james.morse@arm.com, Dave.Martin@arm.com, x86@kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, shenxiaochen@open-hieco.net Subject: [PATCH v4 3/4] selftests/resctrl: Add CPU vendor detection for Hygon Date: Sat, 13 Dec 2025 15:38:10 +0800 Message-ID: <20251213073811.3016864-4-shenxiaochen@open-hieco.net> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251213073811.3016864-1-shenxiaochen@open-hieco.net> References: <20251213073811.3016864-1-shenxiaochen@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The resctrl selftest currently fails on Hygon CPUs that support Platform QoS features, printing the error: "# Can not get vendor info..." This occurs because vendor detection is missing for Hygon CPUs. Fix this by extending the CPU vendor detection logic to include Hygon's vendor ID. Signed-off-by: Xiaochen Shen Reviewed-by: Reinette Chatre --- tools/testing/selftests/resctrl/resctrl.h | 1 + tools/testing/selftests/resctrl/resctrl_tests.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/self= tests/resctrl/resctrl.h index 4f9c7d04c98d..afe635b6e48d 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -39,6 +39,7 @@ */ #define ARCH_INTEL BIT(0) #define ARCH_AMD BIT(1) +#define ARCH_HYGON BIT(2) =20 #define END_OF_TESTS 1 =20 diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testin= g/selftests/resctrl/resctrl_tests.c index 980ecf2bcf10..78626bbae976 100644 --- a/tools/testing/selftests/resctrl/resctrl_tests.c +++ b/tools/testing/selftests/resctrl/resctrl_tests.c @@ -50,6 +50,8 @@ static unsigned int detect_vendor(void) vendor_id =3D ARCH_INTEL; else if (s && !strcmp(s, ": AuthenticAMD\n")) vendor_id =3D ARCH_AMD; + else if (s && !strcmp(s, ": HygonGenuine\n")) + vendor_id =3D ARCH_HYGON; =20 fclose(inf); free(res); --=20 2.47.3 From nobody Sun Dec 14 05:56:52 2025 Received: from out28-101.mail.aliyun.com (out28-101.mail.aliyun.com [115.124.28.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE4792192EE; Sat, 13 Dec 2025 07:39:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765611559; cv=none; b=JYkNmSanlezo0RQPhFVUlV8I3pq5x2dRhv8GZaDUbtvWUqxOnzSQxUB/QEJC15vKinOeHOcEoCjo4555LS4D8tRF15aq+mS33qyeXbvXRvAcw2ygFtqGz/GYcyTef2LRWfolIH779Mn0ge0Yxt+bUy3bZGRO4C5IfPSdUT8hq4I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765611559; c=relaxed/simple; bh=PxGqK+Upare33OSoP8+pD90vk5IxEEo1RRc2j6W6CP8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XTWVPGBSCgSAhFs6zGNVr7c68HZGYWD58eN6bKwbV5EudObOlDnAvF7Si2Zr3l1pGTxz/RX7gH7jizPzRhzyaQSGyGepfXEXwdS5iI2iWQMjeB20EZShTddRmNO+dMZ3DUtJsmQCHsS05im4cu+DPtv/Vs4a/QuYZytQq/qTtXY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net Received: from localhost.localdomain(mailfrom:shenxiaochen@open-hieco.net fp:SMTPD_---.fjNqpxr_1765611545 cluster:ay29) by smtp.aliyun-inc.com; Sat, 13 Dec 2025 15:39:06 +0800 From: Xiaochen Shen To: tony.luck@intel.com, reinette.chatre@intel.com, bp@alien8.de, fenghuay@nvidia.com, shuah@kernel.org, skhan@linuxfoundation.org Cc: babu.moger@amd.com, james.morse@arm.com, Dave.Martin@arm.com, x86@kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, shenxiaochen@open-hieco.net Subject: [PATCH v4 4/4] selftests/resctrl: Fix non-contiguous CBM check for Hygon Date: Sat, 13 Dec 2025 15:38:11 +0800 Message-ID: <20251213073811.3016864-5-shenxiaochen@open-hieco.net> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251213073811.3016864-1-shenxiaochen@open-hieco.net> References: <20251213073811.3016864-1-shenxiaochen@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The resctrl selftest currently fails on Hygon CPUs that always supports non-contiguous CBM, printing the error: "# Hardware and kernel differ on non-contiguous CBM support!" This occurs because the arch_supports_noncont_cat() function lacks vendor detection for Hygon CPUs, preventing proper identification of their non-contiguous CBM capability. Fix this by adding Hygon vendor ID detection to arch_supports_noncont_cat(). Signed-off-by: Xiaochen Shen Reviewed-by: Reinette Chatre Reviewed-by: Fenghua Yu --- tools/testing/selftests/resctrl/cat_test.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/sel= ftests/resctrl/cat_test.c index 94cfdba5308d..f00b622c1460 100644 --- a/tools/testing/selftests/resctrl/cat_test.c +++ b/tools/testing/selftests/resctrl/cat_test.c @@ -290,8 +290,10 @@ static int cat_run_test(const struct resctrl_test *tes= t, const struct user_param =20 static bool arch_supports_noncont_cat(const struct resctrl_test *test) { - /* AMD always supports non-contiguous CBM. */ - if (get_vendor() =3D=3D ARCH_AMD) + unsigned int vendor_id =3D get_vendor(); + + /* AMD and Hygon always support non-contiguous CBM. */ + if (vendor_id =3D=3D ARCH_AMD || vendor_id =3D=3D ARCH_HYGON) return true; =20 #if defined(__i386__) || defined(__x86_64__) /* arch */ --=20 2.47.3