From nobody Sun Dec 14 12:12:43 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6261331076A; Fri, 12 Dec 2025 21:07:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765573644; cv=none; b=mTLSnWGl+np37c1kHmIb0MvCnTgTQ2Y7jr4PpZk7QACcAtx2XFJHPVkPEN6pvkbbUqVDOwHMs/ge0bFK//4OuKLDDjbA7Lqhk6ioFE3UjIykPT3FngDRqJjjv4VE0GIIt2w3qfSLxtcD7q5Egd4jyNltC1lioSp7D62R7HbdWLE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765573644; c=relaxed/simple; bh=5gw6pjfeueiALaxtetN467gFL+pdUzVeIy03ukQ3tew=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JjjkjCc0UNw9XGD/mtCmnfcksYeOqdroeJtinFCB2NDbsornJuidhnYWcTVCz5Xyf8o7wG/WxJxHM9NS2mcSDEMGC/9QA46t81QbO6HOOhx/m8fMwJIWA8kB3L1gC+MGutf+Pk8eRWNT0luk29dH4uDZ6JojKvWXZ76lUfIJqx4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Sth/kDB7; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Sth/kDB7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765573643; x=1797109643; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5gw6pjfeueiALaxtetN467gFL+pdUzVeIy03ukQ3tew=; b=Sth/kDB7LXZGcXScLQsOttL2B49/Vj9Yne4DcdSHkshxZOAI2N7JSJi+ svIXgqeQ6yYshOMjAfSClvsGIxOMPakCsMuU0GLuDfitqSqBvKWYcvYNO n8Mj4OyU0sOj2GswY35E/wwc8z+eYID0MfyijHPL4FdM8I17ojDE8hT+L Z+4E4dQx5kMTyVI64pLOpUFamOTnDdk3RPrykwx5ACO1zw4l2hbKIb/7H xnxoYRoYa3fV5iG9SOScWSvhZmHbJ+uG6i9j55ZwdRR5jFMDeqyrwtdeh PeArqWPtXjWEevkpd2ts+2Q10BhYN8QC+0oO+0/HhW4rl7LVBC2hNoc7X w==; X-CSE-ConnectionGUID: K6izLNZkSGiBxZ9GCs/mbA== X-CSE-MsgGUID: wYHk3CsaQ0emsM7TpfaYqw== X-IronPort-AV: E=McAfee;i="6800,10657,11640"; a="67333593" X-IronPort-AV: E=Sophos;i="6.21,144,1763452800"; d="scan'208";a="67333593" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2025 13:07:17 -0800 X-CSE-ConnectionGUID: /zaRPayZQo6AHvQTX/iN4A== X-CSE-MsgGUID: flpQL1EXSjynJu+hgLm3Nw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,144,1763452800"; d="scan'208";a="202269531" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2025 13:07:16 -0800 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas Subject: [PATCH 5/7] perf/x86/intel/uncore: Support IIO free-running counters on DMR Date: Fri, 12 Dec 2025 13:00:05 -0800 Message-ID: <20251212210007.13986-6-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251212210007.13986-1-zide.chen@intel.com> References: <20251212210007.13986-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The free-running counters for IIO uncore blocks on Diamond Rapids are similar to Sapphire Rapids IMC freecounters, with the following differences: - The counters are MMIO based. - Only a subset of IP blocks implement free-running counters: HIOP0 (IP Base Addr: 2E7000h) HIOP1 (IP Base Addr: 2EF000h) HIOP3 (IP Base Addr: 2FF000h) HIOP4 (IP Base Addr: 307000h) - IMH2 (Secondary IMH) does not provide free-running counters. Signed-off-by: Zide Chen --- arch/x86/events/intel/uncore_snbep.c | 120 +++++++++++++++++++++++++-- 1 file changed, 115 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 56c6ac86f28e..21cca1b28075 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -472,10 +472,14 @@ #define SPR_C0_MSR_PMON_BOX_FILTER0 0x200e =20 /* DMR */ +#define DMR_IMH1_HIOP_MMIO_BASE 0x1ffff6ae7000 +#define DMR_HIOP_MMIO_SIZE 0x8000 #define DMR_CXLCM_EVENT_MASK_EXT 0xf #define DMR_HAMVF_EVENT_MASK_EXT 0xffffffff #define DMR_PCIE4_EVENT_MASK_EXT 0xffffff =20 +#define UNCORE_DMR_ITC 0x30 + #define DMR_IMC_PMON_FIXED_CTR 0x18 #define DMR_IMC_PMON_FIXED_CTL 0x10 =20 @@ -6442,7 +6446,11 @@ static int uncore_type_max_boxes(struct intel_uncore= _type **types, for (node =3D rb_first(type->boxes); node; node =3D rb_next(node)) { unit =3D rb_entry(node, struct intel_uncore_discovery_unit, node); =20 - if (unit->id > max) + /* + * on DMR IMH2, the unit id starts from 0x8000, + * and we don't need to count it. + */ + if ((unit->id > max) && (unit->id < 0x8000)) max =3D unit->id; } return max + 1; @@ -6925,6 +6933,103 @@ int dmr_uncore_units_ignore[] =3D { UNCORE_IGNORE_END }; =20 +static unsigned int dmr_iio_freerunning_box_offsets[] =3D { + 0x0, 0x8000, 0x18000, 0x20000 +}; + +static void dmr_uncore_freerunning_init_box(struct intel_uncore_box *box) +{ + struct intel_uncore_type *type =3D box->pmu->type; + u64 mmio_base; + + if (box->pmu->pmu_idx >=3D type->num_boxes) { + pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name); + return; + } + + mmio_base =3D DMR_IMH1_HIOP_MMIO_BASE; + mmio_base +=3D dmr_iio_freerunning_box_offsets[box->pmu->pmu_idx]; + + box->io_addr =3D ioremap(mmio_base, type->mmio_map_size); + if (!box->io_addr) + pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name); +} + +static struct intel_uncore_ops dmr_uncore_freerunning_ops =3D { + .init_box =3D dmr_uncore_freerunning_init_box, + .exit_box =3D uncore_mmio_exit_box, + .read_counter =3D uncore_mmio_read_counter, + .hw_config =3D uncore_freerunning_hw_config, +}; + +enum perf_uncore_dmr_iio_freerunning_type_id { + DMR_ITC_INB_DATA_BW, + DMR_ITC_BW_IN, + DMR_OTC_BW_OUT, + DMR_OTC_CLOCK_TICKS, + + DMR_IIO_FREERUNNING_TYPE_MAX, +}; + +static struct freerunning_counters dmr_iio_freerunning[] =3D { + [DMR_ITC_INB_DATA_BW] =3D { 0x4d40, 0x8, 0, 8, 48}, + [DMR_ITC_BW_IN] =3D { 0x6b00, 0x8, 0, 8, 48}, + [DMR_OTC_BW_OUT] =3D { 0x6b60, 0x8, 0, 8, 48}, + [DMR_OTC_CLOCK_TICKS] =3D { 0x6bb0, 0x8, 0, 1, 48}, +}; + +static struct uncore_event_desc dmr_uncore_iio_freerunning_events[] =3D { + /* ITC Free Running Data BW counter for inbound traffic */ + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port0, 0x10, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port1, 0x11, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port2, 0x12, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port3, 0x13, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port4, 0x14, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port5, 0x15, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port6, 0x16, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port7, 0x17, "3.814697266e-6"), + + /* ITC Free Running BW IN counters */ + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port4, 0x24, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port5, 0x25, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port6, 0x26, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port7, 0x27, "3.814697266e-6"), + + /* ITC Free Running BW OUT counters */ + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port0, 0x30, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port1, 0x31, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port2, 0x32, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port3, 0x33, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port4, 0x34, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port5, 0x35, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port6, 0x36, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port7, 0x37, "3.814697266e-6"), + + /* Free Running Clock Counter */ + INTEL_UNCORE_EVENT_DESC(clockticks, "event=3D0xff,umask=3D0x40"), + { /* end: all zeroes */ }, +}; + +static struct intel_uncore_type dmr_uncore_iio_free_running =3D { + .name =3D "iio_free_running", + .num_counters =3D 25, + .mmio_map_size =3D DMR_HIOP_MMIO_SIZE, + .num_freerunning_types =3D DMR_IIO_FREERUNNING_TYPE_MAX, + .freerunning =3D dmr_iio_freerunning, + .ops =3D &dmr_uncore_freerunning_ops, + .event_descs =3D dmr_uncore_iio_freerunning_events, + .format_group =3D &skx_uncore_iio_freerunning_format_group, +}; + +#define UNCORE_DMR_MMIO_EXTRA_UNCORES 1 +static struct intel_uncore_type *dmr_mmio_uncores[UNCORE_DMR_MMIO_EXTRA_UN= CORES] =3D { + &dmr_uncore_iio_free_running, +}; + int dmr_uncore_pci_init(void) { uncore_pci_uncores =3D uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL, @@ -6932,11 +7037,16 @@ int dmr_uncore_pci_init(void) dmr_uncores); return 0; } + void dmr_uncore_mmio_init(void) { - uncore_mmio_uncores =3D uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL, - UNCORE_DMR_NUM_UNCORE_TYPES, - dmr_uncores); -} + uncore_mmio_uncores =3D uncore_get_uncores(UNCORE_ACCESS_MMIO, + UNCORE_DMR_MMIO_EXTRA_UNCORES, + dmr_mmio_uncores, + UNCORE_DMR_NUM_UNCORE_TYPES, + dmr_uncores); =20 + dmr_uncore_iio_free_running.num_boxes =3D + uncore_type_max_boxes(uncore_mmio_uncores, UNCORE_DMR_ITC); +} /* end of DMR uncore support */ --=20 2.52.0