From nobody Sun Feb 8 09:39:39 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 407CF3101CD; Fri, 12 Dec 2025 12:23:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765542215; cv=none; b=TI/y23J/HeMwsyPm68xfMHZNt5ouAovPlHNsGkbqM+qfdSRlbIGLd7rvR7bwJ1W2SBDktpZps4LSoPNnJFCNRbHciA0VRjYcX8WoRb/hfeqQo2hCcCqeJYvUwD9ElMXeqJM+sfbu3VCj0NA+HdB29QUIbb2AknK7lJTY6hIU7is= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765542215; c=relaxed/simple; bh=z3iLHALp4QjoSfAihQGMe1LpUc1uk/U89OzWJDUUWRo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mDLSAgEkErAMkaq2t5hSIGLv82gttQd3swjKFwU0DMwwXVa4gQUkhlJed8MTTOMHST23hUt8lSniGE4ZsG3feR6mRCZI5bmn7Kzqqba2AUjQQLxTBFaytv738u7JW5lgsVQIpg08wsdqZAsy2sUQgfr6amEBj58Dgmyl5Cllh+Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=kPO9xW4a; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="kPO9xW4a" Received: from pps.filterd (m0431383.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BBNS5W03755297; Fri, 12 Dec 2025 04:23:24 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=C qaDlcW0GYz9WcX0FQkvVVCI8qdsi0Muh2f+A2RNuLw=; b=kPO9xW4aUdHoFFsBx iR0ZCunOx62rBPrm+EIQBYEJJxHJBihV94fh7zPAaDIliRsTt5qvyGIDZO07/Ov+ DKABNEhgDgqck+S9X1dLCdxmAPa9phTVtcKlfkuuk/oBsmtsrAQFfB+OhPrfU9WW pwyUCqZv2ohz0cYKc7Rn+PCPHSaOoiKh5BM3IJQBMYFVx4087/9pNSkgsYm5Pbvl aiI8ARmcnJBgMvuihmnobbfaKs12XlxPszXWZ8aq0GB0I582iLiHLNn5995I41Kw 7AEKK4jWYFetslE/6qv9pjui6M2r3rBC/Q9QT7/71jNtDjazgmTgysTy52cRyiO6 DjxOQ== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 4b07nfsb7u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 Dec 2025 04:23:23 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Fri, 12 Dec 2025 04:23:35 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Fri, 12 Dec 2025 04:23:35 -0800 Received: from sapphire1.sclab.marvell.com (unknown [10.111.132.245]) by maili.marvell.com (Postfix) with ESMTP id 505313F7088; Fri, 12 Dec 2025 04:23:21 -0800 (PST) From: Vimlesh Kumar To: , CC: , , , "Vimlesh Kumar" , Veerasenareddy Burru , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , "Paolo Abeni" , Satananda Burla , "Abhijit Ayarekar" Subject: [PATCH net v1 1/3] octeon_ep: disable per ring interrupts Date: Fri, 12 Dec 2025 12:23:00 +0000 Message-ID: <20251212122304.2562229-2-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251212122304.2562229-1-vimleshk@marvell.com> References: <20251212122304.2562229-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 0ElD2GWRArAuWo_HAfHtdddTO5sFXqoD X-Authority-Analysis: v=2.4 cv=QtZTHFyd c=1 sm=1 tr=0 ts=693c093c cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=e4-9pDM4cGMqtLHJL1gA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEyMDA5NiBTYWx0ZWRfX/5zx3RG2ZAW4 IXzlpxFBLqjySVPzUxCk9jZvtJb6u8lSGJCmOPjU/k5sctCM8NLryxqjtg88T90hmXvS+rLQvOV iMIZXpxZjimmpQhO2onJ4DXc0uck9ym3LLmkMpiwBTvdgkf04RzpcvG889iBYIjWAGkk9ThxMUQ mCtgagz1Pb4vuerYgN0f45iveC6J5nU/Kzp9RUczWbhJYupw7qqMdRip4Tu0XbTFFYkbB3DdxqB BpY/UUr+NIvSL/52dE7bwM0SJ1SJhVTgCxfIGdJWNSq2PBvzSuzzc7yjKSjMYtqoZLsNVhRFkIu z9CVu5jtwQK51L7iBjGOlBWUHI6JbFR+l6jlH9eECRq7l4unBwYevLnhQSHtsFQlPBmc6McaYQs dA8Pq6PaTdtu/85qP157lAcH3IOWxg== X-Proofpoint-ORIG-GUID: 0ElD2GWRArAuWo_HAfHtdddTO5sFXqoD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-12_03,2025-12-11_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Disable the MSI-X per ring interrupt for every PF ring when PF netdev goes down. Fixes: 1f2c2d0cee023 ("octeon_ep: add hardware configuration APIs") Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- .../net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c | 12 ++++++++++-- .../net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c | 12 ++++++++++-- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c index b5805969404f..db8ae1734e1b 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c @@ -696,14 +696,22 @@ static void octep_enable_interrupts_cn93_pf(struct oc= tep_device *oct) /* Disable all interrupts */ static void octep_disable_interrupts_cn93_pf(struct octep_device *oct) { - u64 intr_mask =3D 0ULL; + u64 reg_val, intr_mask =3D 0ULL; int srn, num_rings, i; =20 srn =3D CFG_GET_PORTS_PF_SRN(oct->conf); num_rings =3D CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); =20 - for (i =3D 0; i < num_rings; i++) + for (i =3D 0; i < num_rings; i++) { intr_mask |=3D (0x1ULL << (srn + i)); + reg_val =3D octep_read_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(srn + i)); + reg_val &=3D ~(0x1ULL << 62); + octep_write_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(srn + i), reg_val); + + reg_val =3D octep_read_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(srn + i)); + reg_val &=3D ~(0x1ULL << 62); + octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(srn + i), reg_val); + } =20 octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask); octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask); diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c index 5de0b5ecbc5f..6369c4dedf46 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c @@ -720,14 +720,22 @@ static void octep_enable_interrupts_cnxk_pf(struct oc= tep_device *oct) /* Disable all interrupts */ static void octep_disable_interrupts_cnxk_pf(struct octep_device *oct) { - u64 intr_mask =3D 0ULL; + u64 reg_val, intr_mask =3D 0ULL; int srn, num_rings, i; =20 srn =3D CFG_GET_PORTS_PF_SRN(oct->conf); num_rings =3D CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); =20 - for (i =3D 0; i < num_rings; i++) + for (i =3D 0; i < num_rings; i++) { intr_mask |=3D (0x1ULL << (srn + i)); + reg_val =3D octep_read_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(srn + i)); + reg_val &=3D ~(0x1ULL << 62); + octep_write_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(srn + i), reg_val); + + reg_val =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(srn + i)); + reg_val &=3D ~(0x1ULL << 62); + octep_write_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(srn + i), reg_val); + } =20 octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask); octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask); --=20 2.47.0 From nobody Sun Feb 8 09:39:39 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC9423161A7; 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Fri, 12 Dec 2025 04:23:28 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Fri, 12 Dec 2025 04:23:41 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Fri, 12 Dec 2025 04:23:41 -0800 Received: from sapphire1.sclab.marvell.com (unknown [10.111.132.245]) by maili.marvell.com (Postfix) with ESMTP id 08F4F3F7088; Fri, 12 Dec 2025 04:23:27 -0800 (PST) From: Vimlesh Kumar To: , CC: , , , "Vimlesh Kumar" , Veerasenareddy Burru , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , "Paolo Abeni" Subject: [PATCH net v1 2/3] octeon_ep: ensure dbell BADDR updation Date: Fri, 12 Dec 2025 12:23:01 +0000 Message-ID: <20251212122304.2562229-3-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251212122304.2562229-1-vimleshk@marvell.com> References: <20251212122304.2562229-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=XtT3+FF9 c=1 sm=1 tr=0 ts=693c0941 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=HOYU1IKHfkVmsGA0y00A:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: yOXrcUV_nlcGzOlebu4FxTBz25KjGFXS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEyMDA5NiBTYWx0ZWRfX8Ya1CUX6qTY/ reVqbH1VMFSc2aIcpAAIAhiIQ5g64EvjeAUetfa2smXrt7MWyIFoGCoCXeCV+Phf+aYxWPbwrUq pEPG9dQ4ZB1AEaAOYkc3Ha3dnTTeEfkPZ32P433fJURq5ndVIrr8qqm3Mo50qQhb2b2nTtTnKlV bA3RvJj8goeTr9ustZ5QXd2Y7Mpsyr6gNLkOMtMrSQCgJ2NUg7mWW/ZPbtsLZTyyQQlJqJdiNDw /KUkymNtUM7UR5JD+Xl67Ow3VSpyIEZT8BK/Ch1AsDg8UQRmeEB2uFMZ8LwfDx9iZjjopfJDxwd a6gZOL+SNeVbYvf4sysWynfUnpwtv70VQkOdGUMxeV9E5ajS4N3U4Zq4LZWXNKCm2Ptlc6Mulg+ 22b427WGml8P/lsgynKQrIbGomrM1g== X-Proofpoint-GUID: yOXrcUV_nlcGzOlebu4FxTBz25KjGFXS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-12_03,2025-12-11_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Make sure the OUT DBELL base address reflects the latest values written to it. Fix: Add a wait until the OUT DBELL base address register is updated with the DMA ring descriptor address, and modify the setup_oq function to properly handle failures. Fixes: 0807dc76f3bf5("octeon_ep: support Octeon CN10K devices") Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- .../marvell/octeon_ep/octep_cn9k_pf.c | 3 ++- .../marvell/octeon_ep/octep_cnxk_pf.c | 25 +++++++++++++++---- .../ethernet/marvell/octeon_ep/octep_main.h | 6 ++++- .../net/ethernet/marvell/octeon_ep/octep_rx.c | 4 ++- 4 files changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c index db8ae1734e1b..32057a6351c1 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c @@ -307,7 +307,7 @@ static void octep_setup_iq_regs_cn93_pf(struct octep_de= vice *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_setup_oq_regs_cn93_pf(struct octep_device *oct, int oq_n= o) +static int octep_setup_oq_regs_cn93_pf(struct octep_device *oct, int oq_no) { u64 reg_val; u64 oq_ctl =3D 0ULL; @@ -355,6 +355,7 @@ static void octep_setup_oq_regs_cn93_pf(struct octep_de= vice *oct, int oq_no) reg_val =3D ((u64)time_threshold << 32) | CFG_GET_OQ_INTR_PKT(oct->conf); octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no), reg_val); + return 0; } =20 /* Setup registers for a PF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c index 6369c4dedf46..80f658bf5418 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c @@ -327,10 +327,11 @@ static void octep_setup_iq_regs_cnxk_pf(struct octep_= device *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_n= o) +static int octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_no) { u64 reg_val; u64 oq_ctl =3D 0ULL; + u64 reg_ba_val; u32 time_threshold =3D 0; struct octep_oq *oq =3D oct->oq[oq_no]; =20 @@ -343,6 +344,23 @@ static void octep_setup_oq_regs_cnxk_pf(struct octep_d= evice *oct, int oq_no) reg_val =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); } while (!(reg_val & CNXK_R_OUT_CTL_IDLE)); } + octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), oq->max_count); + /* Wait for WMARK to get applied */ + usleep_range(10, 15); + + octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), oq->desc_ring_d= ma); + octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), oq->max_count); + reg_ba_val =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no)); + if (reg_ba_val !=3D oq->desc_ring_dma) { + do { + if (reg_ba_val =3D=3D UINT64_MAX) + return -1; + octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), + oq->desc_ring_dma); + octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), oq->max_count= ); + reg_ba_val =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no)); + } while (reg_ba_val !=3D oq->desc_ring_dma); + } =20 reg_val &=3D ~(CNXK_R_OUT_CTL_IMODE); reg_val &=3D ~(CNXK_R_OUT_CTL_ROR_P); @@ -356,10 +374,6 @@ static void octep_setup_oq_regs_cnxk_pf(struct octep_d= evice *oct, int oq_no) reg_val |=3D (CNXK_R_OUT_CTL_ES_P); =20 octep_write_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no), reg_val); - octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), - oq->desc_ring_dma); - octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), - oq->max_count); =20 oq_ctl =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); =20 @@ -385,6 +399,7 @@ static void octep_setup_oq_regs_cnxk_pf(struct octep_de= vice *oct, int oq_no) reg_val &=3D ~0xFFFFFFFFULL; reg_val |=3D CFG_GET_OQ_WMARK(oct->conf); octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), reg_val); + return 0; } =20 /* Setup registers for a PF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_main.h b/drivers/= net/ethernet/marvell/octeon_ep/octep_main.h index 81ac4267811c..76622cdf577d 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_main.h +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_main.h @@ -55,6 +55,10 @@ (iq_)->max_count - IQ_INSTR_PENDING(iq_); \ }) =20 +#ifndef UINT64_MAX +#define UINT64_MAX ((u64)(~((u64)0))) /* 0xFFFFFFFFFFFFFFFF */ +#endif + /* PCI address space mapping information. * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of * Octeon gets mapped to different physical address spaces in @@ -77,7 +81,7 @@ struct octep_pci_win_regs { =20 struct octep_hw_ops { void (*setup_iq_regs)(struct octep_device *oct, int q); - void (*setup_oq_regs)(struct octep_device *oct, int q); + int (*setup_oq_regs)(struct octep_device *oct, int q); void (*setup_mbox_regs)(struct octep_device *oct, int mbox); =20 irqreturn_t (*mbox_intr_handler)(void *ioq_vector); diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c b/drivers/ne= t/ethernet/marvell/octeon_ep/octep_rx.c index 82b6b19e76b4..1581cc468d74 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c @@ -170,7 +170,9 @@ static int octep_setup_oq(struct octep_device *oct, int= q_no) goto oq_fill_buff_err; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Subject: [PATCH net v1 3/3] octeon_ep_vf: ensure dbell BADDR updation Date: Fri, 12 Dec 2025 12:23:02 +0000 Message-ID: <20251212122304.2562229-4-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251212122304.2562229-1-vimleshk@marvell.com> References: <20251212122304.2562229-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: SMBZumO5rdAjs1FlWfITfJVpJrNiYvup X-Authority-Analysis: v=2.4 cv=QtZTHFyd c=1 sm=1 tr=0 ts=693c0948 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=9s7rcsES4n5jIWhP9eIA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEyMDA5NiBTYWx0ZWRfX9t5YTyDPmd0Z K+KDiM36fsX1cbSmMIfyKYi903ohmq5A7XiI6CJh59BAYyGqSOF+w8L4+bR6YgDO1GVHhHoL6/l 3awDUsww7IH6V6EggmHg3Z58f7A/hVfYg3SioUJ28jglr7t+G18sNgH7GBt9DeKTRnhkblgjZuW DF4+Xi61g/67rCm12vVFsPe9B1d7ft0P7kTgEq7EUyY1bSOCqxjamETqg9ARqW4a7hCiNsPnwh2 Z48fmMj/uO9+OGzlb6Dex1TVW7Vb1vQaBJV32gVEpEDoYi/Aedx0v9mAbbOjM5DhrcI7nggAQxK agCqcbK1WVggOVHjjWDh+peOiQqAv4N7ufYGe8RRyfkScfLLybPlP7E5nSxU/a60Tv8AEfmCcLt ymTtmrIduODRoFgxae40Hkd9tjzbGw== X-Proofpoint-ORIG-GUID: SMBZumO5rdAjs1FlWfITfJVpJrNiYvup X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-12_03,2025-12-11_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Make sure the OUT DBELL base address reflects the latest values written to it. Fix: Add a wait until the OUT DBELL base address register is updated with the DMA ring descriptor address, and modify the setup_oq function to properly handle failures. Fixes: 2c0c32c72be29 ("octeon_ep_vf: add hardware configuration APIs") Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- .../marvell/octeon_ep_vf/octep_vf_cn9k.c | 3 ++- .../marvell/octeon_ep_vf/octep_vf_cnxk.c | 25 ++++++++++++++++--- .../marvell/octeon_ep_vf/octep_vf_main.h | 6 ++++- .../marvell/octeon_ep_vf/octep_vf_rx.c | 4 ++- 4 files changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c b/dr= ivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c index 88937fce75f1..4c769b27c278 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c @@ -196,7 +196,7 @@ static void octep_vf_setup_iq_regs_cn93(struct octep_vf= _device *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_vf_setup_oq_regs_cn93(struct octep_vf_device *oct, int o= q_no) +static int octep_vf_setup_oq_regs_cn93(struct octep_vf_device *oct, int oq= _no) { struct octep_vf_oq *oq =3D oct->oq[oq_no]; u32 time_threshold =3D 0; @@ -239,6 +239,7 @@ static void octep_vf_setup_oq_regs_cn93(struct octep_vf= _device *oct, int oq_no) time_threshold =3D CFG_GET_OQ_INTR_TIME(oct->conf); reg_val =3D ((u64)time_threshold << 32) | CFG_GET_OQ_INTR_PKT(oct->conf); octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_INT_LEVELS(oq_no), reg_val); + return 0; } =20 /* Setup registers for a VF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c b/dr= ivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c index 1f79dfad42c6..30dc09205446 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c @@ -199,11 +199,12 @@ static void octep_vf_setup_iq_regs_cnxk(struct octep_= vf_device *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_vf_setup_oq_regs_cnxk(struct octep_vf_device *oct, int o= q_no) +static int octep_vf_setup_oq_regs_cnxk(struct octep_vf_device *oct, int oq= _no) { struct octep_vf_oq *oq =3D oct->oq[oq_no]; u32 time_threshold =3D 0; u64 oq_ctl =3D ULL(0); + u64 reg_ba_val; u64 reg_val; =20 reg_val =3D octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); @@ -214,6 +215,25 @@ static void octep_vf_setup_oq_regs_cnxk(struct octep_v= f_device *oct, int oq_no) reg_val =3D octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); } while (!(reg_val & CNXK_VF_R_OUT_CTL_IDLE)); } + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no), oq->max_count); + /* Wait for WMARK to get applied */ + usleep_range(10, 15); + + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no), oq->desc_= ring_dma); + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_RSIZE(oq_no), oq->max_c= ount); + reg_ba_val =3D octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_= no)); + if (reg_ba_val !=3D oq->desc_ring_dma) { + do { + if (reg_ba_val =3D=3D UINT64_MAX) + return -1; + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no), + oq->desc_ring_dma); + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_RSIZE(oq_no), + oq->max_count); + reg_ba_val =3D octep_vf_read_csr64(oct, + CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no)); + } while (reg_ba_val !=3D oq->desc_ring_dma); + } =20 reg_val &=3D ~(CNXK_VF_R_OUT_CTL_IMODE); reg_val &=3D ~(CNXK_VF_R_OUT_CTL_ROR_P); @@ -227,8 +247,6 @@ static void octep_vf_setup_oq_regs_cnxk(struct octep_vf= _device *oct, int oq_no) reg_val |=3D (CNXK_VF_R_OUT_CTL_ES_P); =20 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no), reg_val); - octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no), oq->desc_= ring_dma); - octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_RSIZE(oq_no), oq->max_c= ount); =20 oq_ctl =3D octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); /* Clear the ISIZE and BSIZE (22-0) */ @@ -250,6 +268,7 @@ static void octep_vf_setup_oq_regs_cnxk(struct octep_vf= _device *oct, int oq_no) reg_val &=3D ~GENMASK_ULL(31, 0); reg_val |=3D CFG_GET_OQ_WMARK(oct->conf); octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no), reg_val); + return 0; } =20 /* Setup registers for a VF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h b/dr= ivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h index b9f13506f462..65454d875677 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h @@ -40,6 +40,10 @@ (iq_)->max_count - IQ_INSTR_PENDING(iq_); \ }) =20 +#ifndef UINT64_MAX +#define UINT64_MAX ((u64)(~((u64)0))) /* 0xFFFFFFFFFFFFFFFF */ +#endif + /* PCI address space mapping information. * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of * Octeon gets mapped to different physical address spaces in @@ -55,7 +59,7 @@ struct octep_vf_mmio { =20 struct octep_vf_hw_ops { void (*setup_iq_regs)(struct octep_vf_device *oct, int q); - void (*setup_oq_regs)(struct octep_vf_device *oct, int q); + int (*setup_oq_regs)(struct octep_vf_device *oct, int q); void (*setup_mbox_regs)(struct octep_vf_device *oct, int mbox); =20 irqreturn_t (*non_ioq_intr_handler)(void *ioq_vector); diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c b/driv= ers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c index d70c8be3cfc4..6446f6bf0b90 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c @@ -171,7 +171,9 @@ static int octep_vf_setup_oq(struct octep_vf_device *oc= t, int q_no) goto oq_fill_buff_err; =20 octep_vf_oq_reset_indices(oq); - oct->hw_ops.setup_oq_regs(oct, q_no); + if (oct->hw_ops.setup_oq_regs(oct, q_no)) + goto oq_fill_buff_err; + oct->num_oqs++; =20 return 0; --=20 2.47.0