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From: "xiaoshun.xu" Add support for MT8189 DEVAPC, DEVAPC debug registers have new version, so refine the structure of devapc_regs_ofs_xxxx to devapc_regs_ofs_verX, and rename the infra_base to base in mtk_devapc_context because DEVAPC not only access the infra_base to dump debug information when violation happens Signed-off-by: xiaoshun.xu --- drivers/soc/mediatek/mtk-devapc.c | 146 +++++++++++++++++++++++------- 1 file changed, 114 insertions(+), 32 deletions(-) diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-d= evapc.c index f54c966138b5..6dbec4016a24 100644 --- a/drivers/soc/mediatek/mtk-devapc.c +++ b/drivers/soc/mediatek/mtk-devapc.c @@ -26,9 +26,19 @@ struct mtk_devapc_vio_dbgs { u32 addr_h:4; u32 resv:4; } dbg0_bits; + + struct { + u32 dmnid:6; + u32 vio_w:1; + u32 vio_r:1; + u32 addr_h:4; + u32 resv:20; + } dbg0_bits_ver2; }; u32 vio_dbg1; + u32 vio_dbg2; + u32 vio_dbg3; }; struct mtk_devapc_regs_ofs { @@ -37,6 +47,8 @@ struct mtk_devapc_regs_ofs { u32 vio_sta_offset; u32 vio_dbg0_offset; u32 vio_dbg1_offset; + u32 vio_dbg2_offset; + u32 vio_dbg3_offset; u32 apc_con_offset; u32 vio_shift_sta_offset; u32 vio_shift_sel_offset; @@ -44,16 +56,20 @@ struct mtk_devapc_regs_ofs { }; struct mtk_devapc_data { - /* numbers of violation index */ - u32 vio_idx_num; + u32 version; + /* Default numbers of violation index */ + u32 default_vio_idx_num; const struct mtk_devapc_regs_ofs *regs_ofs; }; struct mtk_devapc_context { struct device *dev; - void __iomem *infra_base; + void __iomem *base; struct clk *infra_clk; const struct mtk_devapc_data *data; + + /* numbers of violation index */ + u32 vio_idx_num; }; static void clear_vio_status(struct mtk_devapc_context *ctx) @@ -61,12 +77,12 @@ static void clear_vio_status(struct mtk_devapc_context = *ctx) void __iomem *reg; int i; - reg =3D ctx->infra_base + ctx->data->regs_ofs->vio_sta_offset; + reg =3D ctx->base + ctx->data->regs_ofs->vio_sta_offset; - for (i =3D 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i= ++) + for (i =3D 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++) writel(GENMASK(31, 0), reg + 4 * i); - writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0), + writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1), 0), reg + 4 * i); } @@ -76,22 +92,22 @@ static void mask_module_irq(struct mtk_devapc_context *= ctx, bool mask) u32 val; int i; - reg =3D ctx->infra_base + ctx->data->regs_ofs->vio_mask_offset; + reg =3D ctx->base + ctx->data->regs_ofs->vio_mask_offset; if (mask) val =3D GENMASK(31, 0); else val =3D 0; - for (i =3D 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i= ++) + for (i =3D 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++) writel(val, reg + 4 * i); val =3D readl(reg + 4 * i); if (mask) - val |=3D GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num)= - 1, + val |=3D GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1), 0); else - val &=3D ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num= ) - 1, + val &=3D ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1), 0); writel(val, reg + 4 * i); @@ -118,11 +134,11 @@ static int devapc_sync_vio_dbg(struct mtk_devapc_cont= ext *ctx) int ret; u32 val; - pd_vio_shift_sta_reg =3D ctx->infra_base + + pd_vio_shift_sta_reg =3D ctx->base + ctx->data->regs_ofs->vio_shift_sta_offset; - pd_vio_shift_sel_reg =3D ctx->infra_base + + pd_vio_shift_sel_reg =3D ctx->base + ctx->data->regs_ofs->vio_shift_sel_offset; - pd_vio_shift_con_reg =3D ctx->infra_base + + pd_vio_shift_con_reg =3D ctx->base + ctx->data->regs_ofs->vio_shift_con_offset; /* Find the minimum shift group which has violation */ @@ -163,22 +179,52 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_= context *ctx) struct mtk_devapc_vio_dbgs vio_dbgs; void __iomem *vio_dbg0_reg; void __iomem *vio_dbg1_reg; + void __iomem *vio_dbg2_reg; + void __iomem *vio_dbg3_reg; + u32 vio_addr_l, vio_addr_h, bus_id, domain_id; + u32 vio_w, vio_r; + u64 vio_addr; - vio_dbg0_reg =3D ctx->infra_base + ctx->data->regs_ofs->vio_dbg0_of= fset; - vio_dbg1_reg =3D ctx->infra_base + ctx->data->regs_ofs->vio_dbg1_of= fset; + vio_dbg0_reg =3D ctx->base + ctx->data->regs_ofs->vio_dbg0_offset; + vio_dbg1_reg =3D ctx->base + ctx->data->regs_ofs->vio_dbg1_offset; + vio_dbg2_reg =3D ctx->base + ctx->data->regs_ofs->vio_dbg2_offset; + vio_dbg3_reg =3D ctx->base + ctx->data->regs_ofs->vio_dbg3_offset; vio_dbgs.vio_dbg0 =3D readl(vio_dbg0_reg); vio_dbgs.vio_dbg1 =3D readl(vio_dbg1_reg); + if (ctx->data->version >=3D 2U) + vio_dbgs.vio_dbg2 =3D readl(vio_dbg2_reg); + if (ctx->data->version =3D=3D 3U) + vio_dbgs.vio_dbg3 =3D readl(vio_dbg3_reg); + + if (ctx->data->version =3D=3D 1U) { + /* arch version 1 */ + bus_id =3D vio_dbgs.dbg0_bits.mstid; + vio_addr =3D vio_dbgs.vio_dbg1; + domain_id =3D vio_dbgs.dbg0_bits.dmnid; + vio_w =3D vio_dbgs.dbg0_bits.vio_w; + vio_r =3D vio_dbgs.dbg0_bits.vio_r; + } else { + /* arch version 2 & 3 */ + bus_id =3D vio_dbgs.vio_dbg1; + + vio_addr_l =3D vio_dbgs.vio_dbg2; + vio_addr_h =3D ctx->data->version =3D=3D 2U ? vio_dbgs.dbg0= _bits_ver2.addr_h : + vio_dbgs.vio_dbg3; + vio_addr =3D ((u64)vio_addr_h << 32) + vio_addr_l; + domain_id =3D vio_dbgs.dbg0_bits_ver2.dmnid; + vio_w =3D vio_dbgs.dbg0_bits_ver2.vio_w; + vio_r =3D vio_dbgs.dbg0_bits_ver2.vio_r; + } /* Print violation information */ - if (vio_dbgs.dbg0_bits.vio_w) + if (vio_w) dev_info(ctx->dev, "Write Violation\n"); - else if (vio_dbgs.dbg0_bits.vio_r) + else if (vio_r) dev_info(ctx->dev, "Read Violation\n"); - dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%x\n", - vio_dbgs.dbg0_bits.mstid, vio_dbgs.dbg0_bits.dmnid, - vio_dbgs.vio_dbg1); + dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%llx\n", + bus_id, domain_id, vio_addr); } /* @@ -203,7 +249,8 @@ static irqreturn_t devapc_violation_irq(int irq_number,= void *data) */ static void start_devapc(struct mtk_devapc_context *ctx) { - writel(BIT(31), ctx->infra_base + ctx->data->regs_ofs->apc_con_offs= et); + + writel(BIT(31), ctx->base + ctx->data->regs_ofs->apc_con_offset); mask_module_irq(ctx, false); } @@ -215,10 +262,10 @@ static void stop_devapc(struct mtk_devapc_context *ct= x) { mask_module_irq(ctx, true); - writel(BIT(2), ctx->infra_base + ctx->data->regs_ofs->apc_con_offse= t); + writel(BIT(2), ctx->base + ctx->data->regs_ofs->apc_con_offset); } -static const struct mtk_devapc_regs_ofs devapc_regs_ofs_mt6779 =3D { +static const struct mtk_devapc_regs_ofs devapc_regs_ofs_ver1 =3D { .vio_mask_offset =3D 0x0, .vio_sta_offset =3D 0x400, .vio_dbg0_offset =3D 0x900, @@ -229,14 +276,34 @@ static const struct mtk_devapc_regs_ofs devapc_regs_o= fs_mt6779 =3D { .vio_shift_con_offset =3D 0xF20, }; +static const struct mtk_devapc_regs_ofs devapc_regs_ofs_ver2 =3D { + .vio_mask_offset =3D 0x0, + .vio_sta_offset =3D 0x400, + .vio_dbg0_offset =3D 0x900, + .vio_dbg1_offset =3D 0x904, + .vio_dbg2_offset =3D 0x908, + .vio_dbg3_offset =3D 0x90c, + .apc_con_offset =3D 0xF00, + .vio_shift_sta_offset =3D 0xF20, + .vio_shift_sel_offset =3D 0xF30, + .vio_shift_con_offset =3D 0xF10, +}; + static const struct mtk_devapc_data devapc_mt6779 =3D { - .vio_idx_num =3D 511, - .regs_ofs =3D &devapc_regs_ofs_mt6779, + .version =3D 1, + .default_vio_idx_num =3D 511, + .regs_ofs =3D &devapc_regs_ofs_ver1, }; static const struct mtk_devapc_data devapc_mt8186 =3D { - .vio_idx_num =3D 519, - .regs_ofs =3D &devapc_regs_ofs_mt6779, + .version =3D 1, + .default_vio_idx_num =3D 519, + .regs_ofs =3D &devapc_regs_ofs_ver1, +}; + +static const struct mtk_devapc_data devapc_mt8189 =3D { + .version =3D 3, + .regs_ofs =3D &devapc_regs_ofs_ver2, }; static const struct of_device_id mtk_devapc_dt_match[] =3D { @@ -246,6 +313,9 @@ static const struct of_device_id mtk_devapc_dt_match[] = =3D { }, { .compatible =3D "mediatek,mt8186-devapc", .data =3D &devapc_mt8186, + }, { + .compatible =3D "mediatek,mt8189-devapc", + .data =3D &devapc_mt8189, }, { }, }; @@ -268,10 +338,21 @@ static int mtk_devapc_probe(struct platform_device *p= dev) ctx->data =3D of_device_get_match_data(&pdev->dev); ctx->dev =3D &pdev->dev; - ctx->infra_base =3D of_iomap(node, 0); - if (!ctx->infra_base) + ctx->base =3D of_iomap(node, 0); + if (!ctx->base) return -EINVAL; + /* + * Set effective vio_idx_num from default value. + * If vio_idx_num is 0, get the info from DT. + */ + ctx->vio_idx_num =3D ctx->data->default_vio_idx_num; + if (ctx->vio_idx_num =3D=3D 0) + if (of_property_read_u32(node, + "vio-idx-num", + &ctx->vio_idx_num)) + return -EINVAL; + devapc_irq =3D irq_of_parse_and_map(node, 0); if (!devapc_irq) { ret =3D -EINVAL; @@ -296,7 +377,7 @@ static int mtk_devapc_probe(struct platform_device *pde= v) return 0; err: - iounmap(ctx->infra_base); + iounmap(ctx->base); return ret; } @@ -305,12 +386,13 @@ static void mtk_devapc_remove(struct platform_device = *pdev) struct mtk_devapc_context *ctx =3D platform_get_drvdata(pdev); stop_devapc(ctx); - iounmap(ctx->infra_base); + + iounmap(ctx->base); } static struct platform_driver mtk_devapc_driver =3D { .probe =3D mtk_devapc_probe, - .remove =3D mtk_devapc_remove, + .remove_new =3D mtk_devapc_remove, .driver =3D { .name =3D "mtk-devapc", .of_match_table =3D mtk_devapc_dt_match, -- 2.45.2