From nobody Sun Feb 8 09:42:57 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0688428B3E7; Fri, 12 Dec 2025 02:06:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765505172; cv=none; b=N7eUG7a4uib+SOvYEt7rPUI84a3R6o5TxvYySNeVUYTZX+aCEX+L2ZhcQRj/inDEDupODvuCa1qd7Wc7IB/0TsM9ofnA+v6ZYriIqQMmh4QUw+ygWiI0m3jKZLGWt4GHGu8gnAJs7FoI9kviLjSY4BawMRmvrOiLu26cVuLMpg0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765505172; c=relaxed/simple; bh=zWYSYTi2Ehk5Tt/y3fdV2e1WlZ0xEil7gXV+7es5qx0=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=L6Q3on9F5PX7ofzumsA1i/tDBf04VxdqytmFgm8u+jjskcQs+TyeHgZqEtPVKYwsteomoPcZnePj9YECvKkuuHeUE0YYt4NTAuZ9mGNaAsVO8i4XPh3IuLrp+lx9/6OMeOkh2hDfyA3WZsBp0Bq4APe1ewhFZinEYzENl7JFoto= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GVWKU+4l; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GVWKU+4l" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765505170; x=1797041170; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=zWYSYTi2Ehk5Tt/y3fdV2e1WlZ0xEil7gXV+7es5qx0=; b=GVWKU+4lO9xgytUdtWCzjEmSbQgtWTdmq55K8WrHnoNGDKTWlWuAcCTn K7uOJm6JEucSfB3Oo16Lmpe03l1N14I7zufpxk28NBKaHC6NqUxhK0snM MvDrX9KqntUp/IIhR7UCBjtmANf/F6SMVFxLh13ohPCXJ/HaDu7rkLmBz 503CDO51xDSmzb9XrS16I/5cPpJF14OTK8H8ORuDxa1EmZsv6ELBW+lQb TC27XtKcvbfl4m2zhmT6uiWZm4ghLntwQUzljD1USV2cEZVGvK2UVQJkE Dqn/MTsePWcv26Jpc7JEZEKX+nQnTjGAFugfRUY56ZIJmJxagGiYbOLpg g==; X-CSE-ConnectionGUID: zEFudGiNRxCgFDj+pPzw0Q== X-CSE-MsgGUID: LhAE9XZyT2K4dtkq0PT/wA== X-IronPort-AV: E=McAfee;i="6800,10657,11635"; a="67426620" X-IronPort-AV: E=Sophos;i="6.20,256,1758610800"; d="scan'208";a="67426620" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2025 18:06:09 -0800 X-CSE-ConnectionGUID: N0HMPccjQ16B1lIH6itCpw== X-CSE-MsgGUID: +m5jObAeSVyE4l0jvy/4YQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,141,1763452800"; d="scan'208";a="197768043" Received: from ktian1-pkvm.sh.intel.com ([10.239.48.205]) by fmviesa010.fm.intel.com with ESMTP; 11 Dec 2025 18:06:06 -0800 From: Kevin Tian To: Alex Williamson , Ankit Agrawal Cc: Jason Gunthorpe , Yishai Hadas , Shameer Kolothum , Kevin Tian , Ramesh Thomas , Yunxiang Li , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Farrah Chen , stable@vger.kernel.org Subject: [PATCH] vfio/pci: Disable qword access to the PCI ROM bar Date: Fri, 12 Dec 2025 02:09:41 +0000 Message-ID: <20251212020941.338355-1-kevin.tian@intel.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 2b938e3db335 ("vfio/pci: Enable iowrite64 and ioread64 for vfio pci") enables qword access to the PCI bar resources. However certain devices (e.g. Intel X710) are observed with problem upon qword accesses to the rom bar, e.g. triggering PCI aer errors. Instead of trying to identify all broken devices, universally disable qword access to the rom bar i.e. going back to the old way which worked reliably for years. Reported-by: Farrah Chen Closes: https://bugzilla.kernel.org/show_bug.cgi?id=3D220740 Fixes: 2b938e3db335 ("vfio/pci: Enable iowrite64 and ioread64 for vfio pci") Cc: stable@vger.kernel.org Signed-off-by: Kevin Tian --- drivers/vfio/pci/nvgrace-gpu/main.c | 4 ++-- drivers/vfio/pci/vfio_pci_rdwr.c | 19 +++++++++++++++---- include/linux/vfio_pci_core.h | 2 +- 3 files changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace= -gpu/main.c index e346392b72f6..9b39184f76b7 100644 --- a/drivers/vfio/pci/nvgrace-gpu/main.c +++ b/drivers/vfio/pci/nvgrace-gpu/main.c @@ -491,7 +491,7 @@ nvgrace_gpu_map_and_read(struct nvgrace_gpu_pci_core_de= vice *nvdev, ret =3D vfio_pci_core_do_io_rw(&nvdev->core_device, false, nvdev->resmem.ioaddr, buf, offset, mem_count, - 0, 0, false); + 0, 0, false, true); } =20 return ret; @@ -609,7 +609,7 @@ nvgrace_gpu_map_and_write(struct nvgrace_gpu_pci_core_d= evice *nvdev, ret =3D vfio_pci_core_do_io_rw(&nvdev->core_device, false, nvdev->resmem.ioaddr, (char __user *)buf, pos, mem_count, - 0, 0, true); + 0, 0, true, true); } =20 return ret; diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_r= dwr.c index 6192788c8ba3..95dc7e04cb08 100644 --- a/drivers/vfio/pci/vfio_pci_rdwr.c +++ b/drivers/vfio/pci/vfio_pci_rdwr.c @@ -135,7 +135,7 @@ VFIO_IORDWR(64) ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool tes= t_mem, void __iomem *io, char __user *buf, loff_t off, size_t count, size_t x_start, - size_t x_end, bool iswrite) + size_t x_end, bool iswrite, bool allow_qword) { ssize_t done =3D 0; int ret; @@ -150,7 +150,7 @@ ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_dev= ice *vdev, bool test_mem, else fillable =3D 0; =20 - if (fillable >=3D 8 && !(off % 8)) { + if (allow_qword && fillable >=3D 8 && !(off % 8)) { ret =3D vfio_pci_iordwr64(vdev, iswrite, test_mem, io, buf, off, &filled); if (ret) @@ -234,6 +234,7 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vd= ev, char __user *buf, void __iomem *io; struct resource *res =3D &vdev->pdev->resource[bar]; ssize_t done; + bool allow_qword =3D true; =20 if (pci_resource_start(pdev, bar)) end =3D pci_resource_len(pdev, bar); @@ -262,6 +263,16 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *v= dev, char __user *buf, if (!io) return -ENOMEM; x_end =3D end; + + /* + * Certain devices (e.g. Intel X710) don't support qword + * access to the ROM bar. Otherwise PCI AER errors might be + * triggered. + * + * Disable qword access to the ROM bar universally, which + * worked reliably for years before qword access is enabled. + */ + allow_qword =3D false; } else { int ret =3D vfio_pci_core_setup_barmap(vdev, bar); if (ret) { @@ -278,7 +289,7 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vd= ev, char __user *buf, } =20 done =3D vfio_pci_core_do_io_rw(vdev, res->flags & IORESOURCE_MEM, io, bu= f, pos, - count, x_start, x_end, iswrite); + count, x_start, x_end, iswrite, allow_qword); =20 if (done >=3D 0) *ppos +=3D done; @@ -352,7 +363,7 @@ ssize_t vfio_pci_vga_rw(struct vfio_pci_core_device *vd= ev, char __user *buf, * to the memory enable bit in the command register. */ done =3D vfio_pci_core_do_io_rw(vdev, false, iomem, buf, off, count, - 0, 0, iswrite); + 0, 0, iswrite, true); =20 vga_put(vdev->pdev, rsrc); =20 diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index f541044e42a2..3a75b76eaed3 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -133,7 +133,7 @@ pci_ers_result_t vfio_pci_core_aer_err_detected(struct = pci_dev *pdev, ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool tes= t_mem, void __iomem *io, char __user *buf, loff_t off, size_t count, size_t x_start, - size_t x_end, bool iswrite); + size_t x_end, bool iswrite, bool allow_qword); bool vfio_pci_core_range_intersect_range(loff_t buf_start, size_t buf_cnt, loff_t reg_start, size_t reg_cnt, loff_t *buf_offset, --=20 2.43.0