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Fri, 12 Dec 2025 00:56:43 -0800 (PST) Received: from ipedrosa-thinkpadx1carbongen12.rmtes.csb ([89.7.8.79]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42fa8a09fbesm10501696f8f.0.2025.12.12.00.56.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Dec 2025 00:56:43 -0800 (PST) From: Iker Pedrosa Date: Fri, 12 Dec 2025 09:56:08 +0100 Subject: [PATCH v6 1/3] dt-bindings: display: sitronix,st7920: Add DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251212-st7920-v6-1-4d3067528072@gmail.com> References: <20251212-st7920-v6-0-4d3067528072@gmail.com> In-Reply-To: <20251212-st7920-v6-0-4d3067528072@gmail.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Javier Martinez Canillas , Iker Pedrosa Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 Add binding for Sitronix ST7920 display. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Iker Pedrosa --- .../bindings/display/sitronix,st7920.yaml | 58 ++++++++++++++++++= ++++ 1 file changed, 58 insertions(+) diff --git a/Documentation/devicetree/bindings/display/sitronix,st7920.yaml= b/Documentation/devicetree/bindings/display/sitronix,st7920.yaml new file mode 100644 index 0000000000000000000000000000000000000000..c4f006fc41e1f472939725bd82b= 86a649f9b3f56 --- /dev/null +++ b/Documentation/devicetree/bindings/display/sitronix,st7920.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/sitronix,st7920.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sitronix ST7920 LCD Display Controllers + +maintainers: + - Iker Pedrosa + +description: + The Sitronix ST7920 is a controller for monochrome dot-matrix graphical = LCDs, + most commonly used for 128x64 pixel displays. + +properties: + compatible: + const: sitronix,st7920 + + reg: + maxItems: 1 + + vdd-supply: + description: Regulator that provides 5V Vdd power supply + + reset-gpios: + maxItems: 1 + + spi-max-frequency: + maximum: 600000 + +required: + - compatible + - reg + - spi-max-frequency + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; 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This provides a standard framebuffer interface for these common monochrome LCDs. Signed-off-by: Iker Pedrosa Reviewed-by: Javier Martinez Canillas Reviewed-by: Thomas Zimmermann --- drivers/gpu/drm/sitronix/Kconfig | 10 + drivers/gpu/drm/sitronix/Makefile | 1 + drivers/gpu/drm/sitronix/st7920.c | 868 ++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 879 insertions(+) diff --git a/drivers/gpu/drm/sitronix/Kconfig b/drivers/gpu/drm/sitronix/Kc= onfig index 6de7d92d9b74c72746915b945869dba91f161d2b..f14115350069849b668d75188f6= d504d56fa3dda 100644 --- a/drivers/gpu/drm/sitronix/Kconfig +++ b/drivers/gpu/drm/sitronix/Kconfig @@ -40,3 +40,13 @@ config DRM_ST7735R =20 If M is selected the module will be called st7735r. =20 +config DRM_ST7920 + tristate "DRM support for Sitronix ST7920 LCD displays" + depends on DRM && SPI && MMU + select DRM_GEM_SHMEM_HELPER + select DRM_KMS_HELPER + select REGMAP_SPI + help + DRM driver for the ST7920 Sitronix LCD controllers. + + If M is selected the module will be called st7920. diff --git a/drivers/gpu/drm/sitronix/Makefile b/drivers/gpu/drm/sitronix/M= akefile index bd139e5a6995fa026cc635b3c29782473d1efad7..2f064a518121bfee3cca73acd42= 589e8c54cd4d7 100644 --- a/drivers/gpu/drm/sitronix/Makefile +++ b/drivers/gpu/drm/sitronix/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_DRM_ST7571_I2C) +=3D st7571-i2c.o obj-$(CONFIG_DRM_ST7586) +=3D st7586.o obj-$(CONFIG_DRM_ST7735R) +=3D st7735r.o +obj-$(CONFIG_DRM_ST7920)) +=3D st7920.o diff --git a/drivers/gpu/drm/sitronix/st7920.c b/drivers/gpu/drm/sitronix/s= t7920.c new file mode 100644 index 0000000000000000000000000000000000000000..c1e38beedcc660f6db96ec10cd8= 7b2d4e62ee05e --- /dev/null +++ b/drivers/gpu/drm/sitronix/st7920.c @@ -0,0 +1,868 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * DRM driver for Sitronix ST7920 LCD displays + * + * Copyright 2025 Iker Pedrosa + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "sitronix_st7920" +#define DRIVER_DESC "DRM driver for Sitronix ST7920 LCD displays" +#define DRIVER_DATE "20250723" +#define DRIVER_MAJOR 1 +#define DRIVER_MINOR 0 + +/* Display organization */ +#define ST7920_PITCH 16 +#define ST7920_SCANLINES 64 +#define BYTES_IN_DISPLAY (ST7920_PITCH * ST7920_SCANLINES) +#define BYTES_IN_SEGMENT 2 +#define PIXELS_PER_SEGMENT (BYTES_IN_SEGMENT * 8) +#define ST7920_DEFAULT_WIDTH 128 +#define ST7920_DEFAULT_HEIGHT 64 + +/* Sync sequence */ +#define SYNC_BITS 0xF8 +#define RW_HIGH 0x04 +#define RS_HIGH 0x02 + +/* Commands */ +#define SET_DISPLAY_ON 0x0C +#define SET_DISPLAY_OFF 0x08 +#define SET_DISPLAY_CLEAR 0x01 +#define SET_BASIC_INSTRUCTION_SET 0x30 +#define SET_EXT_INSTRUCTION_SET 0x34 +#define SET_GRAPHICS_DISPLAY 0x36 +#define SET_GDRAM_ADDRESS 0x80 +#define SET_GDRAM_DATA 0xFF /* Driver internal command */ + +/* Masks */ +#define HIGH_DATA_MASK 0xF0 +#define LOW_DATA_MASK 0x0F +#define TOP_VERTICAL_ADDRESS 0x80 +#define BOTTOM_VERTICAL_ADDRESS 0x60 +#define TOP_HORIZONTAL_ADDRESS 0x00 +#define BOTTOM_HORIZONTAL_ADDRESS 0x80 + +#define CMD_SIZE 35 + +struct spi7920_error { + int errno; +}; + +struct st7920_device { + struct drm_device drm; + struct drm_display_mode mode; + struct drm_plane primary_plane; + struct drm_crtc crtc; + struct drm_encoder encoder; + struct drm_connector connector; + struct spi_device *spi; + + struct regmap *regmap; + + struct gpio_desc *reset_gpio; + + u32 height; + u32 width; +}; + +struct st7920_plane_state { + struct drm_shadow_plane_state base; + /* Intermediate buffer to convert pixels from XRGB8888 to HW format */ + u8 *buffer; +}; + +struct st7920_crtc_state { + struct drm_crtc_state base; + /* Buffer to store pixels in HW format and written to the panel */ + u8 *data_array; +}; + +static inline struct st7920_plane_state *to_st7920_plane_state(struct drm_= plane_state *state) +{ + return container_of(state, struct st7920_plane_state, base.base); +} + +static inline struct st7920_crtc_state *to_st7920_crtc_state(struct drm_cr= tc_state *state) +{ + return container_of(state, struct st7920_crtc_state, base); +} + +static inline struct st7920_device *drm_to_st7920(struct drm_device *drm) +{ + return container_of(drm, struct st7920_device, drm); +} + +static int st7920_store_gdram_address(const void *data, u8 *reg) +{ + const u8 y_addr =3D *(const u8 *)data; + bool bottom_screen =3D (y_addr >=3D 32); + int i =3D 0; + + reg[i++] =3D SYNC_BITS; + /* Set vertical address */ + if (!bottom_screen) + reg[i++] =3D TOP_VERTICAL_ADDRESS + (*(uint8_t *)data & HIGH_DATA_MASK); + else + reg[i++] =3D BOTTOM_VERTICAL_ADDRESS + (*(uint8_t *)data & HIGH_DATA_MAS= K); + + reg[i++] =3D *(uint8_t *)data << 4; + /* Set horizontal address */ + reg[i++] =3D SET_GDRAM_ADDRESS; + if (!bottom_screen) + reg[i++] =3D TOP_HORIZONTAL_ADDRESS; + else + reg[i++] =3D BOTTOM_HORIZONTAL_ADDRESS; + + return i; +} + +static int st7920_store_gdram_data(const void *data, u8 *reg) +{ + const u8 *line_data =3D data; + int i =3D 0, j =3D 0; + + reg[i++] =3D SYNC_BITS | RS_HIGH; + + for (j =3D 0; j < 16; j++) { + reg[i++] =3D line_data[j] & 0xF0; + reg[i++] =3D (line_data[j] << 4) & 0xF0; + } + + return i; +} + +static int st7920_store_others(int cmd, const void *data, u8 *reg) +{ + int i =3D 0; + + reg[i++] =3D SYNC_BITS; + reg[i++] =3D cmd & HIGH_DATA_MASK; + reg[i++] =3D (cmd & LOW_DATA_MASK) << 4; + + return i; +} + +static void st7920_spi_write(struct spi_device *spi, int cmd, const void *= data, + int delay_us, struct spi7920_error *err) +{ + u8 reg[CMD_SIZE] =3D {0}; + int size =3D 0; + int ret; + + if (err->errno) + return; + + /* + * First the sync bits are sent: 11111WS0. + * Where W is the read/write (RW) bit and S is the register/data (RS) bit. + * Then, every 8 bits instruction/data will be separated into 2 groups. + * Higher 4 bits (DB7~DB4) will be placed in the first section followed by + * 4 '0's. And lower 4 bits (DB3~DB0) will be placed in the second section + * followed by 4 '0's. + */ + if (cmd =3D=3D SET_GDRAM_ADDRESS) + size =3D st7920_store_gdram_address(data, reg); + else if (cmd =3D=3D SET_GDRAM_DATA) + size =3D st7920_store_gdram_data(data, reg); + else + size =3D st7920_store_others(cmd, data, reg); + + ret =3D spi_write(spi, reg, size); + if (ret) { + err->errno =3D ret; + return; + } + + if (delay_us) + udelay(delay_us); +} + +static const struct regmap_config st7920_spi_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, +}; + +static const struct of_device_id st7920_of_match[] =3D { + /* st7920 family */ + { + .compatible =3D "sitronix,st7920", + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, st7920_of_match); + +/* + * The SPI core always reports a MODALIAS uevent of the form "spi:", = even + * if the device was registered via OF. This means that the module will no= t be + * auto loaded, unless it contains an alias that matches the MODALIAS repo= rted. + * + * To workaround this issue, add a SPI device ID table. Even when this sho= uld + * not be needed for this driver to match the registered SPI devices. + */ +static const struct spi_device_id st7920_spi_id[] =3D { + /* st7920 family */ + { "st7920", 0 }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(spi, st7920_spi_id); + +static void st7920_power_on(struct st7920_device *st7920, + struct spi7920_error *err) +{ + st7920_spi_write(st7920->spi, SET_DISPLAY_ON, NULL, 72, err); +} + +static void st7920_power_off(struct st7920_device *st7920, + struct spi7920_error *err) +{ + st7920_spi_write(st7920->spi, SET_DISPLAY_CLEAR, NULL, 1600, err); + st7920_spi_write(st7920->spi, SET_DISPLAY_OFF, NULL, 72, err); +} + +static void st7920_hw_reset(struct st7920_device *st7920) +{ + if (!st7920->reset_gpio) + return; + + gpiod_set_value_cansleep(st7920->reset_gpio, 1); + usleep_range(15, 20); + gpiod_set_value_cansleep(st7920->reset_gpio, 0); + msleep(40); +} + +static int st7920_init(struct st7920_device *st7920) +{ + struct spi7920_error err =3D {0}; + + st7920_spi_write(st7920->spi, SET_BASIC_INSTRUCTION_SET, NULL, 72, &err); + st7920_power_on(st7920, &err); + st7920_spi_write(st7920->spi, SET_GRAPHICS_DISPLAY, NULL, 72, &err); + st7920_spi_write(st7920->spi, SET_DISPLAY_CLEAR, NULL, 1600, &err); + + return err.errno; +} + +static int st7920_update_rect(struct st7920_device *st7920, + struct drm_rect *rect, u8 *buf, + u8 *data_array) +{ + struct spi7920_error err =3D {0}; + u32 array_idx =3D 0; + int i, j; + + /* + * The screen is divided in 64(Y)x8(X) segments and each segment is + * further divided in 2 bytes (D15~D0). + * + * Segment 0x0 is in the top-right corner, while segment 63x15 is in the + * bottom-left. They would be displayed in the screen in the following wa= y: + * 0x0 0x1 0x2 ... 0x15 + * 1x0 1x1 1x2 ... 1x15 + * ... + * 63x0 63x1 63x2 ... 63x15 + * + * The data in each byte is big endian. + */ + + for (i =3D 0; i < ST7920_SCANLINES; i++) { + u8 *line_start =3D buf + (i * ST7920_PITCH); + u8 line_buffer[ST7920_PITCH]; + + for (j =3D 0; j < ST7920_PITCH; j++) { + line_buffer[j] =3D bitrev8(line_start[j]); + data_array[array_idx++] =3D line_buffer[j]; + } + + st7920_spi_write(st7920->spi, SET_GDRAM_ADDRESS, &i, 72, &err); + st7920_spi_write(st7920->spi, SET_GDRAM_DATA, line_buffer, 72, &err); + } + + return err.errno; +} + +static void st7920_clear_screen(struct st7920_device *st7920, u8 *data_arr= ay) +{ + struct spi7920_error err =3D {0}; + + memset(data_array, 0, BYTES_IN_DISPLAY); + + st7920_spi_write(st7920->spi, SET_DISPLAY_CLEAR, NULL, 1600, &err); +} + +static int st7920_fb_blit_rect(struct drm_framebuffer *fb, + const struct iosys_map *vmap, + struct drm_rect *rect, + u8 *buf, u8 *data_array, + struct drm_format_conv_state *fmtcnv_state) +{ + struct st7920_device *st7920 =3D drm_to_st7920(fb->dev); + struct iosys_map dst; + unsigned int dst_pitch; + int ret; + + /* Align y to display page boundaries */ + rect->y1 =3D round_down(rect->y1, PIXELS_PER_SEGMENT); + rect->y2 =3D min_t(unsigned int, round_up(rect->y2, PIXELS_PER_SEGMENT), = st7920->height); + + dst_pitch =3D DIV_ROUND_UP(drm_rect_width(rect), 8); + + iosys_map_set_vaddr(&dst, buf); + drm_fb_xrgb8888_to_mono(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state); + + ret =3D st7920_update_rect(st7920, rect, buf, data_array); + + return ret; +} + +static int st7920_primary_plane_atomic_check(struct drm_plane *plane, + struct drm_atomic_state *state) +{ + struct drm_device *drm =3D plane->dev; + struct st7920_device *st7920 =3D drm_to_st7920(drm); + struct drm_plane_state *plane_state =3D drm_atomic_get_new_plane_state(st= ate, plane); + struct st7920_plane_state *st7920_state =3D to_st7920_plane_state(plane_s= tate); + struct drm_shadow_plane_state *shadow_plane_state =3D &st7920_state->base; + struct drm_crtc *crtc =3D plane_state->crtc; + struct drm_crtc_state *crtc_state =3D NULL; + const struct drm_format_info *fi; + unsigned int pitch; + int ret; + + if (crtc) + crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); + + ret =3D drm_atomic_helper_check_plane_state(plane_state, crtc_state, + DRM_PLANE_NO_SCALING, + DRM_PLANE_NO_SCALING, + false, false); + if (ret) + return ret; + else if (!plane_state->visible) + return 0; + + fi =3D drm_format_info(DRM_FORMAT_R1); + if (!fi) + return -EINVAL; + + pitch =3D drm_format_info_min_pitch(fi, 0, st7920->width); + + if (plane_state->fb->format !=3D fi) { + void *buf; + + /* format conversion necessary; reserve buffer */ + buf =3D drm_format_conv_state_reserve(&shadow_plane_state->fmtcnv_state, + pitch, GFP_KERNEL); + if (!buf) + return -ENOMEM; + } + + st7920_state->buffer =3D kcalloc(pitch, st7920->height, GFP_KERNEL); + if (!st7920_state->buffer) + return -ENOMEM; + + return 0; +} + +static void st7920_primary_plane_atomic_update(struct drm_plane *plane, + struct drm_atomic_state *state) +{ + struct drm_plane_state *plane_state =3D drm_atomic_get_new_plane_state(st= ate, plane); + struct drm_plane_state *old_plane_state =3D drm_atomic_get_old_plane_stat= e(state, plane); + struct drm_shadow_plane_state *shadow_plane_state =3D to_drm_shadow_plane= _state(plane_state); + struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(state= , plane_state->crtc); + struct st7920_crtc_state *st7920_crtc_state =3D to_st7920_crtc_state(crt= c_state); + struct st7920_plane_state *st7920_plane_state =3D to_st7920_plane_state(p= lane_state); + struct drm_framebuffer *fb =3D plane_state->fb; + struct drm_atomic_helper_damage_iter iter; + struct drm_device *drm =3D plane->dev; + struct drm_rect dst_clip; + struct drm_rect damage; + int idx; + int ret; + + if (!drm_dev_enter(drm, &idx)) + return; + + if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE) =3D=3D 0) { + drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); + drm_atomic_for_each_plane_damage(&iter, &damage) { + dst_clip =3D plane_state->dst; + + if (!drm_rect_intersect(&dst_clip, &damage)) + continue; + + ret =3D st7920_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip, + st7920_plane_state->buffer, + st7920_crtc_state->data_array, + &shadow_plane_state->fmtcnv_state); + if (ret) + drm_err_once(plane->dev, "Failed to write to device: %d.\n", ret); + } + + drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); + } + + drm_dev_exit(idx); +} + +static void st7920_primary_plane_atomic_disable(struct drm_plane *plane, + struct drm_atomic_state *state) +{ + struct drm_device *drm =3D plane->dev; + struct st7920_device *st7920 =3D drm_to_st7920(drm); + struct drm_plane_state *plane_state =3D drm_atomic_get_new_plane_state(st= ate, plane); + struct drm_crtc_state *crtc_state; + struct st7920_crtc_state *st7920_crtc_state; + int idx; + + if (!plane_state->crtc) + return; + + crtc_state =3D drm_atomic_get_new_crtc_state(state, plane_state->crtc); + st7920_crtc_state =3D to_st7920_crtc_state(crtc_state); + + if (!drm_dev_enter(drm, &idx)) + return; + + st7920_clear_screen(st7920, st7920_crtc_state->data_array); + + drm_dev_exit(idx); +} + +/* Called during init to allocate the plane's atomic state. */ +static void st7920_primary_plane_reset(struct drm_plane *plane) +{ + struct st7920_plane_state *st7920_state; + + drm_WARN_ON_ONCE(plane->dev, plane->state); + + st7920_state =3D kzalloc(sizeof(*st7920_state), GFP_KERNEL); + if (!st7920_state) + return; + + __drm_gem_reset_shadow_plane(plane, &st7920_state->base); +} + +static struct drm_plane_state *st7920_primary_plane_duplicate_state(struct= drm_plane *plane) +{ + struct drm_shadow_plane_state *new_shadow_plane_state; + struct st7920_plane_state *st7920_state; + + if (drm_WARN_ON_ONCE(plane->dev, !plane->state)) + return NULL; + + st7920_state =3D kzalloc(sizeof(*st7920_state), GFP_KERNEL); + if (!st7920_state) + return NULL; + + new_shadow_plane_state =3D &st7920_state->base; + + __drm_gem_duplicate_shadow_plane_state(plane, new_shadow_plane_state); + + return &new_shadow_plane_state->base; +} + +static void st7920_primary_plane_destroy_state(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct st7920_plane_state *st7920_state =3D to_st7920_plane_state(state); + + kfree(st7920_state->buffer); + + __drm_gem_destroy_shadow_plane_state(&st7920_state->base); + + kfree(st7920_state); +} + +static const struct drm_plane_helper_funcs st7920_primary_plane_helper_fun= cs =3D { + DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, + .atomic_check =3D st7920_primary_plane_atomic_check, + .atomic_update =3D st7920_primary_plane_atomic_update, + .atomic_disable =3D st7920_primary_plane_atomic_disable, +}; + +static const struct drm_plane_funcs st7920_primary_plane_funcs =3D { + .update_plane =3D drm_atomic_helper_update_plane, + .disable_plane =3D drm_atomic_helper_disable_plane, + .reset =3D st7920_primary_plane_reset, + .atomic_duplicate_state =3D st7920_primary_plane_duplicate_state, + .atomic_destroy_state =3D st7920_primary_plane_destroy_state, + .destroy =3D drm_plane_cleanup, +}; + +static enum drm_mode_status st7920_crtc_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) +{ + struct st7920_device *st7920 =3D drm_to_st7920(crtc->dev); + + return drm_crtc_helper_mode_valid_fixed(crtc, mode, &st7920->mode); +} + +static int st7920_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(state= , crtc); + struct st7920_crtc_state *st7920_state =3D to_st7920_crtc_state(crtc_stat= e); + int ret; + + ret =3D drm_crtc_helper_atomic_check(crtc, state); + if (ret) + return ret; + + st7920_state->data_array =3D kmalloc(BYTES_IN_DISPLAY, GFP_KERNEL); + if (!st7920_state->data_array) + return -ENOMEM; + + return 0; +} + +static void st7920_crtc_atomic_enable(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct drm_device *drm =3D crtc->dev; + struct st7920_device *st7920 =3D drm_to_st7920(drm); + int idx; + int ret; + + if (!drm_dev_enter(drm, &idx)) + return; + + st7920_hw_reset(st7920); + + ret =3D st7920_init(st7920); + if (ret) + drm_err(drm, "Failed to init hardware: %d\n", ret); + + drm_dev_exit(idx); +} + +static void st7920_crtc_atomic_disable(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct spi7920_error err =3D {0}; + struct drm_device *drm =3D crtc->dev; + struct st7920_device *st7920 =3D drm_to_st7920(drm); + int idx; + + drm_dev_enter(drm, &idx); + + st7920_power_off(st7920, &err); + + drm_dev_exit(idx); +} + +/* Called during init to allocate the CRTC's atomic state. */ +static void st7920_crtc_reset(struct drm_crtc *crtc) +{ + struct st7920_crtc_state *st7920_state; + + drm_WARN_ON_ONCE(crtc->dev, crtc->state); + + st7920_state =3D kzalloc(sizeof(*st7920_state), GFP_KERNEL); + if (!st7920_state) + return; + + __drm_atomic_helper_crtc_reset(crtc, &st7920_state->base); +} + +static struct drm_crtc_state *st7920_crtc_duplicate_state(struct drm_crtc = *crtc) +{ + struct st7920_crtc_state *st7920_state; + + if (drm_WARN_ON_ONCE(crtc->dev, !crtc->state)) + return NULL; + + st7920_state =3D kzalloc(sizeof(*st7920_state), GFP_KERNEL); + if (!st7920_state) + return NULL; + + __drm_atomic_helper_crtc_duplicate_state(crtc, &st7920_state->base); + + return &st7920_state->base; +} + +static void st7920_crtc_destroy_state(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct st7920_crtc_state *st7920_state =3D to_st7920_crtc_state(state); + + kfree(st7920_state->data_array); + + __drm_atomic_helper_crtc_destroy_state(state); + + kfree(st7920_state); +} + +/* + * The CRTC is always enabled. Screen updates are performed by + * the primary plane's atomic_update function. Disabling clears + * the screen in the primary plane's atomic_disable function. + */ +static const struct drm_crtc_helper_funcs st7920_crtc_helper_funcs =3D { + .mode_valid =3D st7920_crtc_mode_valid, + .atomic_check =3D st7920_crtc_atomic_check, + .atomic_enable =3D st7920_crtc_atomic_enable, + .atomic_disable =3D st7920_crtc_atomic_disable, +}; + +static const struct drm_crtc_funcs st7920_crtc_funcs =3D { + .reset =3D st7920_crtc_reset, + .destroy =3D drm_crtc_cleanup, + .set_config =3D drm_atomic_helper_set_config, + .page_flip =3D drm_atomic_helper_page_flip, + .atomic_duplicate_state =3D st7920_crtc_duplicate_state, + .atomic_destroy_state =3D st7920_crtc_destroy_state, +}; + +static const struct drm_encoder_funcs st7920_encoder_funcs =3D { + .destroy =3D drm_encoder_cleanup, +}; + +static int st7920_connector_get_modes(struct drm_connector *connector) +{ + struct st7920_device *st7920 =3D drm_to_st7920(connector->dev); + + return drm_connector_helper_get_modes_fixed(connector, &st7920->mode); +} + +static const struct drm_connector_helper_funcs st7920_connector_helper_fun= cs =3D { + .get_modes =3D st7920_connector_get_modes, +}; + +static const struct drm_connector_funcs st7920_connector_funcs =3D { + .reset =3D drm_atomic_helper_connector_reset, + .fill_modes =3D drm_helper_probe_single_connector_modes, + .destroy =3D drm_connector_cleanup, + .atomic_duplicate_state =3D drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_connector_destroy_state, +}; + +static const struct drm_mode_config_funcs st7920_mode_config_funcs =3D { + .fb_create =3D drm_gem_fb_create_with_dirty, + .atomic_check =3D drm_atomic_helper_check, + .atomic_commit =3D drm_atomic_helper_commit, +}; + +static const uint32_t st7920_formats[] =3D { + DRM_FORMAT_XRGB8888, +}; + +DEFINE_DRM_GEM_FOPS(st7920_fops); + +static const struct drm_driver st7920_drm_driver =3D { + DRM_GEM_SHMEM_DRIVER_OPS, + DRM_FBDEV_SHMEM_DRIVER_OPS, + .name =3D DRIVER_NAME, + .desc =3D DRIVER_DESC, + .date =3D DRIVER_DATE, + .major =3D DRIVER_MAJOR, + .minor =3D DRIVER_MINOR, + .driver_features =3D DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET, + .fops =3D &st7920_fops, +}; + +static int st7920_init_modeset(struct st7920_device *st7920) +{ + struct drm_display_mode *mode =3D &st7920->mode; + struct drm_device *drm =3D &st7920->drm; + unsigned long max_width, max_height; + struct drm_plane *primary_plane; + struct drm_crtc *crtc; + struct drm_encoder *encoder; + struct drm_connector *connector; + int ret; + + /* + * Modesetting + */ + + ret =3D drmm_mode_config_init(drm); + if (ret) { + drm_err(drm, "DRM mode config init failed: %d\n", ret); + return ret; + } + + mode->type =3D DRM_MODE_TYPE_DRIVER; + mode->clock =3D 30; + mode->hdisplay =3D st7920->width; + mode->htotal =3D st7920->width; + mode->hsync_start =3D st7920->width; + mode->hsync_end =3D st7920->width; + mode->vdisplay =3D st7920->height; + mode->vtotal =3D st7920->height; + mode->vsync_start =3D st7920->height; + mode->vsync_end =3D st7920->height; + mode->width_mm =3D 27; + mode->height_mm =3D 27; + + max_width =3D max_t(unsigned long, mode->hdisplay, DRM_SHADOW_PLANE_MAX_W= IDTH); + max_height =3D max_t(unsigned long, mode->vdisplay, DRM_SHADOW_PLANE_MAX_= HEIGHT); + + drm->mode_config.min_width =3D mode->hdisplay; + drm->mode_config.max_width =3D max_width; + drm->mode_config.min_height =3D mode->vdisplay; + drm->mode_config.max_height =3D max_height; + drm->mode_config.preferred_depth =3D 24; + drm->mode_config.funcs =3D &st7920_mode_config_funcs; + + /* Primary plane */ + + primary_plane =3D &st7920->primary_plane; + ret =3D drm_universal_plane_init(drm, primary_plane, 0, &st7920_primary_p= lane_funcs, + st7920_formats, ARRAY_SIZE(st7920_formats), + NULL, DRM_PLANE_TYPE_PRIMARY, NULL); + if (ret) { + drm_err(drm, "DRM primary plane init failed: %d\n", ret); + return ret; + } + + drm_plane_helper_add(primary_plane, &st7920_primary_plane_helper_funcs); + + drm_plane_enable_fb_damage_clips(primary_plane); + + /* CRTC */ + + crtc =3D &st7920->crtc; + ret =3D drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, + &st7920_crtc_funcs, NULL); + if (ret) { + drm_err(drm, "DRM crtc init failed: %d\n", ret); + return ret; + } + + drm_crtc_helper_add(crtc, &st7920_crtc_helper_funcs); + + /* Encoder */ + + encoder =3D &st7920->encoder; + ret =3D drm_encoder_init(drm, encoder, &st7920_encoder_funcs, + DRM_MODE_ENCODER_NONE, NULL); + if (ret) { + drm_err(drm, "DRM encoder init failed: %d\n", ret); + return ret; + } + + encoder->possible_crtcs =3D drm_crtc_mask(crtc); + + /* Connector */ + + connector =3D &st7920->connector; + ret =3D drm_connector_init(drm, connector, &st7920_connector_funcs, + DRM_MODE_CONNECTOR_Unknown); + if (ret) { + drm_err(drm, "DRM connector init failed: %d\n", ret); + return ret; + } + + drm_connector_helper_add(connector, &st7920_connector_helper_funcs); + + ret =3D drm_connector_attach_encoder(connector, encoder); + if (ret) { + drm_err(drm, "DRM attach connector to encoder failed: %d\n", ret); + return ret; + } + + drm_mode_config_reset(drm); + + return 0; +} + +static int st7920_probe(struct spi_device *spi) +{ + struct st7920_device *st7920; + struct regmap *regmap; + struct device *dev =3D &spi->dev; + struct drm_device *drm; + int ret; + + regmap =3D devm_regmap_init_spi(spi, &st7920_spi_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + st7920 =3D devm_drm_dev_alloc(dev, &st7920_drm_driver, + struct st7920_device, drm); + if (IS_ERR(st7920)) + return PTR_ERR(st7920); + + drm =3D &st7920->drm; + + st7920->drm.dev =3D dev; + st7920->regmap =3D regmap; + st7920->spi =3D spi; + st7920->width =3D ST7920_DEFAULT_WIDTH; + st7920->height =3D ST7920_DEFAULT_HEIGHT; + + st7920->reset_gpio =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LO= W); + if (IS_ERR(st7920->reset_gpio)) { + ret =3D PTR_ERR(st7920->reset_gpio); + return dev_err_probe(dev, ret, "Unable to retrieve reset GPIO\n"); + } + + spi_set_drvdata(spi, st7920); + + ret =3D st7920_init_modeset(st7920); + if (ret) + return ret; + + ret =3D drm_dev_register(drm, 0); + if (ret) + return dev_err_probe(dev, ret, "DRM device register failed\n"); + + drm_client_setup(drm, NULL); + + return 0; +} + +static void st7920_remove(struct spi_device *spi) +{ + struct st7920_device *st7920 =3D spi_get_drvdata(spi); + + drm_dev_unplug(&st7920->drm); + drm_atomic_helper_shutdown(&st7920->drm); +} + +static void st7920_shutdown(struct spi_device *spi) +{ + struct st7920_device *st7920 =3D spi_get_drvdata(spi); + + drm_atomic_helper_shutdown(&st7920->drm); +} + +static struct spi_driver st7920_spi_driver =3D { + .driver =3D { + .name =3D DRIVER_NAME, + .of_match_table =3D st7920_of_match, + }, + .id_table =3D st7920_spi_id, + .probe =3D st7920_probe, + .remove =3D st7920_remove, + .shutdown =3D st7920_shutdown, +}; +module_spi_driver(st7920_spi_driver); + +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_AUTHOR("Iker Pedrosa "); +MODULE_LICENSE("GPL v2"); --=20 2.52.0 From nobody Sun Feb 8 10:00:41 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65D9E3112DD for ; Fri, 12 Dec 2025 08:56:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 12 Dec 2025 00:56:46 -0800 (PST) Received: from ipedrosa-thinkpadx1carbongen12.rmtes.csb ([89.7.8.79]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42fa8a09fbesm10501696f8f.0.2025.12.12.00.56.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Dec 2025 00:56:46 -0800 (PST) From: Iker Pedrosa Date: Fri, 12 Dec 2025 09:56:10 +0100 Subject: [PATCH v6 3/3] MAINTAINERS: Add entry for Sitronix ST7920 driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251212-st7920-v6-3-4d3067528072@gmail.com> References: <20251212-st7920-v6-0-4d3067528072@gmail.com> In-Reply-To: <20251212-st7920-v6-0-4d3067528072@gmail.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Javier Martinez Canillas , Iker Pedrosa Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.2 Add Iker as ST7920 driver maintainer. Reviewed-by: Thomas Zimmermann Signed-off-by: Iker Pedrosa --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5ddf37f0acc960039422ef988cadfa7176972fc5..79b8a277e38b55ebcff05450d6c= 565c0d87c6b51 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7861,6 +7861,13 @@ T: git https://gitlab.freedesktop.org/drm/misc/kerne= l.git F: Documentation/devicetree/bindings/display/sitronix,st7735r.yaml F: drivers/gpu/drm/sitronix/st7735r.c =20 +DRM DRIVER FOR SITRONIX ST7920 LCD DISPLAYS +M: Iker Pedrosa +S: Maintained +T: git https://gitlab.freedesktop.org/drm/misc/kernel.git +F: Documentation/devicetree/bindings/display/sitronix,st7920.yaml +F: drivers/gpu/drm/sitronix/st7920.c + DRM DRIVER FOR SOLOMON SSD130X OLED DISPLAYS M: Javier Martinez Canillas S: Maintained --=20 2.52.0