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Thu, 11 Dec 2025 00:07:44 -0800 (PST) Received: from [10.213.102.126] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7f4c22848a7sm1706651b3a.3.2025.12.11.00.07.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Dec 2025 00:07:44 -0800 (PST) From: Sivareddy Surasani Date: Thu, 11 Dec 2025 13:37:33 +0530 Subject: [PATCH 01/11] bus: mhi: host: Add support to read MHI capabilities Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251211-siva_mhi_dp2-v1-1-d2895c4ec73a@oss.qualcomm.com> References: <20251211-siva_mhi_dp2-v1-0-d2895c4ec73a@oss.qualcomm.com> In-Reply-To: <20251211-siva_mhi_dp2-v1-0-d2895c4ec73a@oss.qualcomm.com> To: Manivannan Sadhasivam , Jonathan Corbet , Arnd Bergmann , Greg Kroah-Hartman Cc: mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Upal Kumar Saha , Himanshu Shukla , Sivareddy Surasani , Vivek Pernamitta , Krishna Chaitanya Chundru X-Mailer: b4 0.15-dev-47773 X-Authority-Analysis: v=2.4 cv=At7jHe9P c=1 sm=1 tr=0 ts=693a7bd2 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=8H38-GfiV2s7wLOohYcA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: OYhuNv-kh8k7JzfuV-pdivFzz7ttvOOt X-Proofpoint-GUID: OYhuNv-kh8k7JzfuV-pdivFzz7ttvOOt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjExMDA1OSBTYWx0ZWRfX7Lj133P6CVnZ xT5sDcb9I0ycZ2iekBkh1sSRCOKTDUaNGIHKqzRUYpqCCqwWlBlkHd5lTrQhFRJK6PBm/+RKtDH 3rewM+Tu5DhdQk6gGI57j0MK8muXpVoihrCDtUFQ+RQfxdTUsJJClGKwlluvcwpCtxdhSvrubiA J2G153nmgBG2yxs/xnt44WLbBlkeBPKHDM18Ns+GglmGOJyaRYFb07SEURWRCnEb8/dvChr2hLp 5kpMvLRcCpnwjLTtm7/AOr2kLvLZ059BnWM+4xSyhschHsRwBKs0L8ssDvnwXHEGGApWnOG1wZk 6s8I0pJo2I4eyCbow0tlw15du8YPmWWDewA+a12aPZtEbKYYPneKMyB39qfSDGVkMPTc88yn1Ce zKAG1DWeYWeBKAs0PqX4pyXp7Enc0g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-10_03,2025-12-09_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 phishscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512110059 From: Vivek Pernamitta As per MHI spec v1.2,sec 6.6, MHI has capability registers which are located after the ERDB array. The location of this group of registers is indicated by the MISCOFF register. Each capability has a capability ID to determine which functionality is supported and each capability will point to the next capability supported. Add a basic function to read those capabilities offsets. Signed-off-by: Vivek Pernamitta Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Sivareddy Surasani --- drivers/bus/mhi/common.h | 13 +++++++++++++ drivers/bus/mhi/host/init.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/drivers/bus/mhi/common.h b/drivers/bus/mhi/common.h index dda340aaed95..58f27c6ba63e 100644 --- a/drivers/bus/mhi/common.h +++ b/drivers/bus/mhi/common.h @@ -16,6 +16,7 @@ #define MHICFG 0x10 #define CHDBOFF 0x18 #define ERDBOFF 0x20 +#define MISCOFF 0x24 #define BHIOFF 0x28 #define BHIEOFF 0x2c #define DEBUGOFF 0x30 @@ -113,6 +114,9 @@ #define MHISTATUS_MHISTATE_MASK GENMASK(15, 8) #define MHISTATUS_SYSERR_MASK BIT(2) #define MHISTATUS_READY_MASK BIT(0) +#define MISC_CAP_MASK GENMASK(31, 0) +#define CAP_CAPID_MASK GENMASK(31, 24) +#define CAP_NEXT_CAP_MASK GENMASK(23, 12) =20 /* Command Ring Element macros */ /* No operation command */ @@ -204,6 +208,15 @@ #define MHI_RSCTRE_DATA_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \ MHI_PKT_TYPE_COALESCING)) =20 +enum mhi_capability_type { + MHI_CAP_ID_INTX =3D 0x1, + MHI_CAP_ID_TIME_SYNC =3D 0x2, + MHI_CAP_ID_BW_SCALE =3D 0x3, + MHI_CAP_ID_TSC_TIME_SYNC =3D 0x4, + MHI_CAP_ID_MAX_TRB_LEN =3D 0x5, + MHI_CAP_ID_MAX, +}; + enum mhi_pkt_type { MHI_PKT_TYPE_INVALID =3D 0x0, MHI_PKT_TYPE_NOOP_CMD =3D 0x1, diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index 099be8dd1900..4c092490c9fd 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -466,6 +466,38 @@ static int mhi_init_dev_ctxt(struct mhi_controller *mh= i_cntrl) return ret; } =20 +static int mhi_find_capability(struct mhi_controller *mhi_cntrl, u32 capab= ility, u32 *offset) +{ + u32 val, cur_cap, next_offset; + int ret; + + /* Get the first supported capability offset */ + ret =3D mhi_read_reg_field(mhi_cntrl, mhi_cntrl->regs, MISCOFF, MISC_CAP_= MASK, offset); + if (ret) + return ret; + + do { + if (*offset >=3D mhi_cntrl->reg_len) + return -ENXIO; + + ret =3D mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, *offset, &val); + if (ret) + return ret; + + cur_cap =3D FIELD_GET(CAP_CAPID_MASK, val); + next_offset =3D FIELD_GET(CAP_NEXT_CAP_MASK, val); + if (cur_cap >=3D MHI_CAP_ID_MAX) + return -ENXIO; + + if (cur_cap =3D=3D capability) + return 0; + + *offset =3D next_offset; + } while (next_offset); + + return -ENXIO; +} + int mhi_init_mmio(struct mhi_controller *mhi_cntrl) { u32 val; --=20 2.34.1