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If the IRQ is currently active, it will write to the register, otherwise it will only set the struct member. There's no locking done to guarantee exclusion with the other two functions that touch the IRQ mask, and it should only be called from a context where the circumstances guarantee no concurrent access is performed. Signed-off-by: Nicolas Frattaroli --- drivers/gpu/drm/panthor/panthor_device.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/pan= thor/panthor_device.h index f35e52b9546a..894d28b3eb02 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -470,6 +470,13 @@ static int panthor_request_ ## __name ## _irq(struct p= anthor_device *ptdev, \ panthor_ ## __name ## _irq_threaded_handler, \ IRQF_SHARED, KBUILD_MODNAME "-" # __name, \ pirq); \ +} \ + \ +static inline void panthor_ ## __name ## _irq_mask_set(struct panthor_irq = *pirq, u32 mask) \ +{ \ + pirq->mask =3D mask; \ + if (!atomic_read(&pirq->suspended)) \ + gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, mask); \ } =20 extern struct workqueue_struct *panthor_cleanup_wq; --=20 2.52.0 From nobody Sun Dec 14 05:56:50 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6701623D2B4 for ; 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mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1765469767; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=Hn7aS3+HyU0krccF78kWJlhZMSmmmlsw2dEITrJqX44=; b=ii+7de0k7uC3BzBt0sceXdcIfpf6lRyBH6uSDzQY38uKtMHAqUhaIrr5jCwETTM+ b8p9NkiDippBQUm217/yTm+EjF1Eb1wRJa9EiCrg6U6DHT403CTVGuQvNCqDlINwnNH obf6bH4S5DPE2tHI8kSPi/LeiJy/lYYJbWXlh9D0= Received: by mx.zohomail.com with SMTPS id 1765469766117994.8573753397689; Thu, 11 Dec 2025 08:16:06 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 11 Dec 2025 17:15:36 +0100 Subject: [PATCH v3 2/3] drm/panthor: Add tracepoint for hardware utilisation changes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251211-panthor-tracepoints-v3-2-924c9d356a5c@collabora.com> References: <20251211-panthor-tracepoints-v3-0-924c9d356a5c@collabora.com> In-Reply-To: <20251211-panthor-tracepoints-v3-0-924c9d356a5c@collabora.com> To: Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chia-I Wu , Karunika Choo Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Mali GPUs have three registers that indicate which parts of the hardware are powered at any moment. These take the form of bitmaps. In the case of SHADER_READY for example, a high bit indicates that the shader core corresponding to that bit index is powered on. These bitmaps aren't solely contiguous bits, as it's common to have holes in the sequence of shader core indices, and the actual set of which cores are present is defined by the "shader present" register. When the GPU finishes a power state transition, it fires a GPU_IRQ_POWER_CHANGED_ALL interrupt. After such an interrupt is received, the _READY registers will contain new interesting data. During power transitions, the GPU_IRQ_POWER_CHANGED interrupt will fire, and the registers will likewise contain potentially changed data. This is not to be confused with the PWR_IRQ_POWER_CHANGED_ALL interrupt, which is something related to Mali v14+'s power control logic. The _READY registers and corresponding interrupts are already available in v9 and onwards. Expose the data as a tracepoint to userspace. This allows users to debug various scenarios and gather interesting information, such as: knowing how much hardware is lit up at any given time, correlating graphics corruption with a specific powered shader core, measuring when hardware is allowed to go to a powered off state again, and so on. The registration/unregistration functions for the tracepoint go through a wrapper in panthor_hw.c, so that v14+ can implement the same tracepoint by adding its hardware specific IRQ on/off callbacks to the panthor_hw.ops member. Signed-off-by: Nicolas Frattaroli Reviewed-by: Karunika Choo --- drivers/gpu/drm/panthor/panthor_gpu.c | 38 ++++++++++++++++++-- drivers/gpu/drm/panthor/panthor_gpu.h | 2 ++ drivers/gpu/drm/panthor/panthor_hw.c | 62 +++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/panthor/panthor_hw.h | 8 +++++ drivers/gpu/drm/panthor/panthor_trace.h | 59 +++++++++++++++++++++++++++++= ++ 5 files changed, 167 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/pantho= r/panthor_gpu.c index 057e167468d0..67572b607b55 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -22,6 +22,9 @@ #include "panthor_hw.h" #include "panthor_regs.h" =20 +#define CREATE_TRACE_POINTS +#include "panthor_trace.h" + /** * struct panthor_gpu - GPU block management data. */ @@ -29,6 +32,9 @@ struct panthor_gpu { /** @irq: GPU irq. */ struct panthor_irq irq; =20 + /** @irq_mask: GPU irq mask. */ + u32 irq_mask; + /** @reqs_lock: Lock protecting access to pending_reqs. */ spinlock_t reqs_lock; =20 @@ -48,6 +54,9 @@ struct panthor_gpu { GPU_IRQ_RESET_COMPLETED | \ GPU_IRQ_CLEAN_CACHES_COMPLETED) =20 +#define GPU_POWER_INTERRUPTS_MASK \ + (GPU_IRQ_POWER_CHANGED | GPU_IRQ_POWER_CHANGED_ALL) + static void panthor_gpu_coherency_set(struct panthor_device *ptdev) { gpu_write(ptdev, GPU_COHERENCY_PROTOCOL, @@ -80,6 +89,12 @@ static void panthor_gpu_irq_handler(struct panthor_devic= e *ptdev, u32 status) { gpu_write(ptdev, GPU_INT_CLEAR, status); =20 + if (tracepoint_enabled(gpu_power_status) && (status & GPU_POWER_INTERRUPT= S_MASK)) + trace_gpu_power_status(ptdev->base.dev, + gpu_read64(ptdev, SHADER_READY), + gpu_read64(ptdev, TILER_READY), + gpu_read64(ptdev, L2_READY)); + if (status & GPU_IRQ_FAULT) { u32 fault_status =3D gpu_read(ptdev, GPU_FAULT_STATUS); u64 address =3D gpu_read64(ptdev, GPU_FAULT_ADDR); @@ -139,6 +154,7 @@ int panthor_gpu_init(struct panthor_device *ptdev) init_waitqueue_head(&gpu->reqs_acked); mutex_init(&gpu->cache_flush_lock); ptdev->gpu =3D gpu; + gpu->irq_mask =3D GPU_INTERRUPTS_MASK; =20 dma_set_max_seg_size(ptdev->base.dev, UINT_MAX); pa_bits =3D GPU_MMU_FEATURES_PA_BITS(ptdev->gpu_info.mmu_features); @@ -150,13 +166,31 @@ int panthor_gpu_init(struct panthor_device *ptdev) if (irq < 0) return irq; =20 - ret =3D panthor_request_gpu_irq(ptdev, &ptdev->gpu->irq, irq, GPU_INTERRU= PTS_MASK); + ret =3D panthor_request_gpu_irq(ptdev, &ptdev->gpu->irq, irq, gpu->irq_ma= sk); if (ret) return ret; =20 return 0; } =20 +int panthor_gpu_power_changed_on(struct panthor_device *ptdev) +{ + guard(pm_runtime_active)(ptdev->base.dev); + + ptdev->gpu->irq_mask |=3D GPU_POWER_INTERRUPTS_MASK; + panthor_gpu_irq_mask_set(&ptdev->gpu->irq, ptdev->gpu->irq_mask); + + return 0; +} + +void panthor_gpu_power_changed_off(struct panthor_device *ptdev) +{ + guard(pm_runtime_active)(ptdev->base.dev); + + ptdev->gpu->irq_mask &=3D ~GPU_POWER_INTERRUPTS_MASK; + panthor_gpu_irq_mask_set(&ptdev->gpu->irq, ptdev->gpu->irq_mask); +} + /** * panthor_gpu_block_power_off() - Power-off a specific block of the GPU * @ptdev: Device. @@ -395,7 +429,7 @@ void panthor_gpu_suspend(struct panthor_device *ptdev) */ void panthor_gpu_resume(struct panthor_device *ptdev) { - panthor_gpu_irq_resume(&ptdev->gpu->irq, GPU_INTERRUPTS_MASK); + panthor_gpu_irq_resume(&ptdev->gpu->irq, ptdev->gpu->irq_mask); panthor_hw_l2_power_on(ptdev); } =20 diff --git a/drivers/gpu/drm/panthor/panthor_gpu.h b/drivers/gpu/drm/pantho= r/panthor_gpu.h index 12e66f48ced1..12c263a39928 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.h +++ b/drivers/gpu/drm/panthor/panthor_gpu.h @@ -51,5 +51,7 @@ int panthor_gpu_l2_power_on(struct panthor_device *ptdev); int panthor_gpu_flush_caches(struct panthor_device *ptdev, u32 l2, u32 lsc, u32 other); int panthor_gpu_soft_reset(struct panthor_device *ptdev); +void panthor_gpu_power_changed_off(struct panthor_device *ptdev); +int panthor_gpu_power_changed_on(struct panthor_device *ptdev); =20 #endif diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor= /panthor_hw.c index 87ebb7ae42c4..ae3320d0e251 100644 --- a/drivers/gpu/drm/panthor/panthor_hw.c +++ b/drivers/gpu/drm/panthor/panthor_hw.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 or MIT /* Copyright 2025 ARM Limited. All rights reserved. */ =20 +#include + #include =20 #include "panthor_device.h" @@ -29,6 +31,8 @@ static struct panthor_hw panthor_hw_arch_v10 =3D { .soft_reset =3D panthor_gpu_soft_reset, .l2_power_off =3D panthor_gpu_l2_power_off, .l2_power_on =3D panthor_gpu_l2_power_on, + .power_changed_off =3D panthor_gpu_power_changed_off, + .power_changed_on =3D panthor_gpu_power_changed_on, }, }; =20 @@ -53,6 +57,64 @@ static struct panthor_hw_entry panthor_hw_match[] =3D { }, }; =20 +static int panthor_hw_set_power_tracing(struct device *dev, void *data) +{ + struct panthor_device *ptdev =3D dev_get_drvdata(dev); + + if (!ptdev) + return -ENODEV; + + if (!ptdev->hw) + return 0; + + if (data) { + if (ptdev->hw->ops.power_changed_on) + return ptdev->hw->ops.power_changed_on(ptdev); + } else { + if (ptdev->hw->ops.power_changed_off) + ptdev->hw->ops.power_changed_off(ptdev); + } + + return 0; +} + +int panthor_hw_power_status_register(void) +{ + struct device_driver *drv; + int ret; + + drv =3D driver_find("panthor", &platform_bus_type); + if (!drv) + return -ENODEV; + + ret =3D driver_for_each_device(drv, NULL, (void *)true, + panthor_hw_set_power_tracing); + + return ret; +} + +void panthor_hw_power_status_unregister(void) +{ + struct device_driver *drv; + int ret; + + drv =3D driver_find("panthor", &platform_bus_type); + if (!drv) + return; + + ret =3D driver_for_each_device(drv, NULL, NULL, panthor_hw_set_power_trac= ing); + + /* + * Ideally, it'd be possible to ask driver_for_each_device to hand us + * another "start" to keep going after the failing device, but it + * doesn't do that. Minor inconvenience in what is probably a bad day + * on the computer already though. + */ + if (ret) + pr_warn("Couldn't mask power IRQ for at least one device: %pe\n", + ERR_PTR(ret)); +} + static char *get_gpu_model_name(struct panthor_device *ptdev) { const u32 gpu_id =3D ptdev->gpu_info.gpu_id; diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor= /panthor_hw.h index 56c68c1e9c26..2c28aea82841 100644 --- a/drivers/gpu/drm/panthor/panthor_hw.h +++ b/drivers/gpu/drm/panthor/panthor_hw.h @@ -19,6 +19,12 @@ struct panthor_hw_ops { =20 /** @l2_power_on: L2 power on function pointer */ int (*l2_power_on)(struct panthor_device *ptdev); + + /** @power_changed_on: Start listening to power change IRQs */ + int (*power_changed_on)(struct panthor_device *ptdev); + + /** @power_changed_off: Stop listening to power change IRQs */ + void (*power_changed_off)(struct panthor_device *ptdev); }; =20 /** @@ -32,6 +38,8 @@ struct panthor_hw { }; =20 int panthor_hw_init(struct panthor_device *ptdev); +int panthor_hw_power_status_register(void); +void panthor_hw_power_status_unregister(void); =20 static inline int panthor_hw_soft_reset(struct panthor_device *ptdev) { diff --git a/drivers/gpu/drm/panthor/panthor_trace.h b/drivers/gpu/drm/pant= hor/panthor_trace.h new file mode 100644 index 000000000000..2b59d7f156b6 --- /dev/null +++ b/drivers/gpu/drm/panthor/panthor_trace.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 or MIT */ +/* Copyright 2025 Collabora ltd. */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM panthor + +#if !defined(__PANTHOR_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ) +#define __PANTHOR_TRACE_H__ + +#include +#include + +int panthor_hw_power_status_register(void); +void panthor_hw_power_status_unregister(void); + +/** + * gpu_power_status - called whenever parts of GPU hardware are turned on = or off + * @dev: pointer to the &struct device, for printing the device name + * @shader_bitmap: bitmap where a high bit indicates the shader core at a = given + * bit index is on, and a low bit indicates a shader core = is + * either powered off or absent + * @tiler_bitmap: bitmap where a high bit indicates the tiler unit at a gi= ven + * bit index is on, and a low bit indicates a tiler unit is + * either powered off or absent + * @l2_bitmap: bitmap where a high bit indicates the L2 cache at a given b= it + * index is on, and a low bit indicates the L2 cache is either + * powered off or absent + */ +TRACE_EVENT_FN(gpu_power_status, + TP_PROTO(const struct device *dev, u64 shader_bitmap, u64 tiler_bitmap, + u64 l2_bitmap), + TP_ARGS(dev, shader_bitmap, tiler_bitmap, l2_bitmap), + TP_STRUCT__entry( + __string(dev_name, dev_name(dev)) + __field(u64, shader_bitmap) + __field(u64, tiler_bitmap) + __field(u64, l2_bitmap) + ), + TP_fast_assign( + __assign_str(dev_name); + __entry->shader_bitmap =3D shader_bitmap; + __entry->tiler_bitmap =3D tiler_bitmap; + __entry->l2_bitmap =3D l2_bitmap; + ), + TP_printk("%s: shader_bitmap=3D0x%llx tiler_bitmap=3D0x%llx l2_bitmap=3D0= x%llx", + __get_str(dev_name), __entry->shader_bitmap, __entry->tiler_bitmap, + __entry->l2_bitmap + ), + panthor_hw_power_status_register, panthor_hw_power_status_unregister +); + +#endif /* __PANTHOR_TRACE_H__ */ + +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE panthor_trace + +#include --=20 2.52.0 From nobody Sun Dec 14 05:56:50 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE42B278E5D for ; Thu, 11 Dec 2025 16:16:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; 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mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1765469771; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=OK+XHpFOCj1744Yxv/t8AvQknfYUAV6wkrEF0BfB+/k=; b=PepJYih3v5JecQ+SbthXl6S/iJXhfG0hx/JxYLTzRUvl23lEcTSRe1Sb15UQsKX5 uciM6ITMIfkHOHqqshzn2WyM46+bZDq9ezV/ZBROExwSDKWbWiWQrAxS/pPcvWw6xiH v6xfwlZzDODpuZWgu0bZWpfloUPw5o6Bccc3A53c= Received: by mx.zohomail.com with SMTPS id 1765469769716995.2075302051617; Thu, 11 Dec 2025 08:16:09 -0800 (PST) From: Nicolas Frattaroli Date: Thu, 11 Dec 2025 17:15:37 +0100 Subject: [PATCH v3 3/3] drm/panthor: Add gpu_job_irq tracepoint Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251211-panthor-tracepoints-v3-3-924c9d356a5c@collabora.com> References: <20251211-panthor-tracepoints-v3-0-924c9d356a5c@collabora.com> In-Reply-To: <20251211-panthor-tracepoints-v3-0-924c9d356a5c@collabora.com> To: Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chia-I Wu , Karunika Choo Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Mali's CSF firmware triggers the job IRQ whenever there's new firmware events for processing. While this can be a global event (BIT(31) of the status register), it's usually an event relating to a command stream group (the other bit indices). Panthor throws these events onto a workqueue for processing outside the IRQ handler. It's therefore useful to have an instrumented tracepoint that goes beyond the generic IRQ tracepoint for this specific case, as it can be augmented with additional data, namely the events bit mask. This can then be used to debug problems relating to GPU jobs events not being processed quickly enough. The duration_ns field can be used to work backwards from when the tracepoint fires (at the end of the IRQ handler) to figure out when the interrupt itself landed, providing not just information on how long the work queueing took, but also when the actual interrupt itself arrived. With this information in hand, the IRQ handler itself being slow can be excluded as a possible source of problems, and attention can be directed to the workqueue processing instead. Signed-off-by: Nicolas Frattaroli --- drivers/gpu/drm/panthor/panthor_fw.c | 13 +++++++++++++ drivers/gpu/drm/panthor/panthor_trace.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor= /panthor_fw.c index 4beaa589ba66..1823d7ba5c78 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.c +++ b/drivers/gpu/drm/panthor/panthor_fw.c @@ -26,6 +26,7 @@ #include "panthor_mmu.h" #include "panthor_regs.h" #include "panthor_sched.h" +#include "panthor_trace.h" =20 #define CSF_FW_NAME "mali_csffw.bin" =20 @@ -1060,6 +1061,12 @@ static void panthor_fw_init_global_iface(struct pant= hor_device *ptdev) =20 static void panthor_job_irq_handler(struct panthor_device *ptdev, u32 stat= us) { + u32 duration; + u64 start; + + if (tracepoint_enabled(gpu_job_irq)) + start =3D ktime_get_ns(); + gpu_write(ptdev, JOB_INT_CLEAR, status); =20 if (!ptdev->fw->booted && (status & JOB_INT_GLOBAL_IF)) @@ -1072,6 +1079,12 @@ static void panthor_job_irq_handler(struct panthor_d= evice *ptdev, u32 status) return; =20 panthor_sched_report_fw_events(ptdev, status); + + if (tracepoint_enabled(gpu_job_irq)) { + if (check_sub_overflow(ktime_get_ns(), start, &duration)) + duration =3D U32_MAX; + trace_gpu_job_irq(ptdev->base.dev, status, duration); + } } PANTHOR_IRQ_HANDLER(job, JOB, panthor_job_irq_handler); =20 diff --git a/drivers/gpu/drm/panthor/panthor_trace.h b/drivers/gpu/drm/pant= hor/panthor_trace.h index 2b59d7f156b6..1efd07861590 100644 --- a/drivers/gpu/drm/panthor/panthor_trace.h +++ b/drivers/gpu/drm/panthor/panthor_trace.h @@ -49,6 +49,34 @@ TRACE_EVENT_FN(gpu_power_status, panthor_hw_power_status_register, panthor_hw_power_status_unregister ); =20 +/** + * gpu_job_irq - called after a job interrupt from firmware completes + * @dev: pointer to the &struct device, for printing the device name + * @events: bitmask of BIT(CSG id) | BIT(31) for a global event + * @duration_ns: Nanoseconds between job IRQ handler entry and exit + * + * The panthor_job_irq_handler() function instrumented by this tracepoint = exits + * once it has queued the firmware interrupts for processing, not when the + * firmware interrupts are fully processed. This tracepoint allows for deb= ugging + * issues with delays in the workqueue's processing of events. + */ +TRACE_EVENT(gpu_job_irq, + TP_PROTO(const struct device *dev, u32 events, u32 duration_ns), + TP_ARGS(dev, events, duration_ns), + TP_STRUCT__entry( + __string(dev_name, dev_name(dev)) + __field(u32, events) + __field(u32, duration_ns) + ), + TP_fast_assign( + __assign_str(dev_name); + __entry->events =3D events; + __entry->duration_ns =3D duration_ns; + ), + TP_printk("%s: events=3D0x%x duration_ns=3D%d", __get_str(dev_name), + __entry->events, __entry->duration_ns) +); + #endif /* __PANTHOR_TRACE_H__ */ =20 #undef TRACE_INCLUDE_PATH --=20 2.52.0