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Support for them in the DPU driver is mature enough, so it's no longer sensible to keep them enabled in the MDP5 driver. Not to mention that MSM8998 never used an MDP5 compatible string. Drop support for the MDP5 3.x genration inside the MDP5 driver and migrate those to the DPU driver only. Note: this will break if one uses the DT generated before v6.3 as they had only the generic, "qcom,mdp5" compatible string for SDM630 and SDM660. However granted that we had two LTS releases inbetween I don't think it is an issue. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 314 ---------------------------= ---- drivers/gpu/drm/msm/msm_drv.c | 16 +- 2 files changed, 13 insertions(+), 317 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm= /disp/mdp5/mdp5_cfg.c index df464f7c05bf..69fef034d0df 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -1097,310 +1097,6 @@ static const struct mdp5_cfg_hw msm8937_config =3D { .max_clk =3D 320000000, }; =20 -static const struct mdp5_cfg_hw msm8998_config =3D { - .name =3D "msm8998", - .mdp =3D { - .count =3D 1, - .caps =3D MDP_CAP_DSC | - MDP_CAP_CDM | - MDP_CAP_SRC_SPLIT | - 0, - }, - .ctl =3D { - .count =3D 5, - .base =3D { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, - .flush_hw_mask =3D 0xf7ffffff, - }, - .pipe_vig =3D { - .count =3D 4, - .base =3D { 0x04000, 0x06000, 0x08000, 0x0a000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_CSC | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_rgb =3D { - .count =3D 4, - .base =3D { 0x14000, 0x16000, 0x18000, 0x1a000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_dma =3D { - .count =3D 2, /* driver supports max of 2 currently */ - .base =3D { 0x24000, 0x26000, 0x28000, 0x2a000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_cursor =3D { - .count =3D 2, - .base =3D { 0x34000, 0x36000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - MDP_PIPE_CAP_CURSOR | - 0, - }, - - .lm =3D { - .count =3D 6, - .base =3D { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 }, - .instances =3D { - { .id =3D 0, .pp =3D 0, .dspp =3D 0, - .caps =3D MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id =3D 1, .pp =3D 1, .dspp =3D 1, - .caps =3D MDP_LM_CAP_DISPLAY, }, - { .id =3D 2, .pp =3D 2, .dspp =3D -1, - .caps =3D MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id =3D 3, .pp =3D -1, .dspp =3D -1, - .caps =3D MDP_LM_CAP_WB, }, - { .id =3D 4, .pp =3D -1, .dspp =3D -1, - .caps =3D MDP_LM_CAP_WB, }, - { .id =3D 5, .pp =3D 3, .dspp =3D -1, - .caps =3D MDP_LM_CAP_DISPLAY, }, - }, - .nb_stages =3D 8, - .max_width =3D 2560, - .max_height =3D 0xFFFF, - }, - .dspp =3D { - .count =3D 2, - .base =3D { 0x54000, 0x56000 }, - }, - .ad =3D { - .count =3D 3, - .base =3D { 0x78000, 0x78800, 0x79000 }, - }, - .pp =3D { - .count =3D 4, - .base =3D { 0x70000, 0x70800, 0x71000, 0x71800 }, - }, - .cdm =3D { - .count =3D 1, - .base =3D { 0x79200 }, - }, - .dsc =3D { - .count =3D 2, - .base =3D { 0x80000, 0x80400 }, - }, - .intf =3D { - .base =3D { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 }, - .connect =3D { - [0] =3D INTF_eDP, - [1] =3D INTF_DSI, - [2] =3D INTF_DSI, - [3] =3D INTF_HDMI, - }, - }, - .max_clk =3D 412500000, -}; - -static const struct mdp5_cfg_hw sdm630_config =3D { - .name =3D "sdm630", - .mdp =3D { - .count =3D 1, - .caps =3D MDP_CAP_CDM | - MDP_CAP_SRC_SPLIT | - 0, - }, - .ctl =3D { - .count =3D 5, - .base =3D { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, - .flush_hw_mask =3D 0xf4ffffff, - }, - .pipe_vig =3D { - .count =3D 1, - .base =3D { 0x04000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_CSC | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_rgb =3D { - .count =3D 4, - .base =3D { 0x14000, 0x16000, 0x18000, 0x1a000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_dma =3D { - .count =3D 2, /* driver supports max of 2 currently */ - .base =3D { 0x24000, 0x26000, 0x28000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_cursor =3D { - .count =3D 1, - .base =3D { 0x34000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - MDP_PIPE_CAP_CURSOR | - 0, - }, - - .lm =3D { - .count =3D 2, - .base =3D { 0x44000, 0x46000 }, - .instances =3D { - { .id =3D 0, .pp =3D 0, .dspp =3D 0, - .caps =3D MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id =3D 1, .pp =3D 1, .dspp =3D -1, - .caps =3D MDP_LM_CAP_WB, }, - }, - .nb_stages =3D 8, - .max_width =3D 2048, - .max_height =3D 0xFFFF, - }, - .dspp =3D { - .count =3D 1, - .base =3D { 0x54000 }, - }, - .ad =3D { - .count =3D 2, - .base =3D { 0x78000, 0x78800 }, - }, - .pp =3D { - .count =3D 3, - .base =3D { 0x70000, 0x71000, 0x72000 }, - }, - .cdm =3D { - .count =3D 1, - .base =3D { 0x79200 }, - }, - .intf =3D { - .base =3D { 0x6a000, 0x6a800 }, - .connect =3D { - [0] =3D INTF_DISABLED, - [1] =3D INTF_DSI, - }, - }, - .max_clk =3D 412500000, -}; - -static const struct mdp5_cfg_hw sdm660_config =3D { - .name =3D "sdm660", - .mdp =3D { - .count =3D 1, - .caps =3D MDP_CAP_DSC | - MDP_CAP_CDM | - MDP_CAP_SRC_SPLIT | - 0, - }, - .ctl =3D { - .count =3D 5, - .base =3D { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, - .flush_hw_mask =3D 0xf4ffffff, - }, - .pipe_vig =3D { - .count =3D 2, - .base =3D { 0x04000, 0x6000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_CSC | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_rgb =3D { - .count =3D 4, - .base =3D { 0x14000, 0x16000, 0x18000, 0x1a000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | - MDP_PIPE_CAP_DECIMATION | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_dma =3D { - .count =3D 2, /* driver supports max of 2 currently */ - .base =3D { 0x24000, 0x26000, 0x28000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - 0, - }, - .pipe_cursor =3D { - .count =3D 1, - .base =3D { 0x34000 }, - .caps =3D MDP_PIPE_CAP_HFLIP | - MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SW_PIX_EXT | - MDP_PIPE_CAP_CURSOR | - 0, - }, - - .lm =3D { - .count =3D 4, - .base =3D { 0x44000, 0x45000, 0x46000, 0x49000 }, - .instances =3D { - { .id =3D 0, .pp =3D 0, .dspp =3D 0, - .caps =3D MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id =3D 1, .pp =3D 1, .dspp =3D 1, - .caps =3D MDP_LM_CAP_DISPLAY, }, - { .id =3D 2, .pp =3D 2, .dspp =3D -1, - .caps =3D MDP_LM_CAP_DISPLAY | - MDP_LM_CAP_PAIR, }, - { .id =3D 3, .pp =3D 3, .dspp =3D -1, - .caps =3D MDP_LM_CAP_WB, }, - }, - .nb_stages =3D 8, - .max_width =3D 2560, - .max_height =3D 0xFFFF, - }, - .dspp =3D { - .count =3D 2, - .base =3D { 0x54000, 0x56000 }, - }, - .ad =3D { - .count =3D 2, - .base =3D { 0x78000, 0x78800 }, - }, - .pp =3D { - .count =3D 5, - .base =3D { 0x70000, 0x70800, 0x71000, 0x71800, 0x72000 }, - }, - .cdm =3D { - .count =3D 1, - .base =3D { 0x79200 }, - }, - .dsc =3D { - .count =3D 2, - .base =3D { 0x80000, 0x80400 }, - }, - .intf =3D { - .base =3D { 0x6a000, 0x6a800, 0x6b000, 0x6b800 }, - .connect =3D { - [0] =3D INTF_DISABLED, - [1] =3D INTF_DSI, - [2] =3D INTF_DSI, - [3] =3D INTF_HDMI, - }, - }, - .max_clk =3D 412500000, -}; - static const struct mdp5_cfg_handler cfg_handlers_v1[] =3D { { .revision =3D 0, .config =3D { .hw =3D &msm8x74v1_config } }, { .revision =3D 1, .config =3D { .hw =3D &msm8x26_config } }, @@ -1416,12 +1112,6 @@ static const struct mdp5_cfg_handler cfg_handlers_v1= [] =3D { { .revision =3D 16, .config =3D { .hw =3D &msm8x53_config } }, }; =20 -static const struct mdp5_cfg_handler cfg_handlers_v3[] =3D { - { .revision =3D 0, .config =3D { .hw =3D &msm8998_config } }, - { .revision =3D 2, .config =3D { .hw =3D &sdm660_config } }, - { .revision =3D 3, .config =3D { .hw =3D &sdm630_config } }, -}; - const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *= cfg_handler) { return cfg_handler->config.hw; @@ -1455,10 +1145,6 @@ struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_k= ms *mdp5_kms, cfg_handlers =3D cfg_handlers_v1; num_handlers =3D ARRAY_SIZE(cfg_handlers_v1); break; - case 3: - cfg_handlers =3D cfg_handlers_v3; - num_handlers =3D ARRAY_SIZE(cfg_handlers_v3); - break; default: DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n", major, minor); diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 7e977fec4100..abee7149a9e8 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -960,23 +960,33 @@ static bool prefer_mdp5 =3D true; MODULE_PARM_DESC(prefer_mdp5, "Select whether MDP5 or DPU driver should be= preferred"); module_param(prefer_mdp5, bool, 0444); =20 +/* list all platforms that have been migrated from mdp5 to dpu driver */ +static const char *const msm_mdp5_dpu_migrated[] =3D { + /* there never was qcom,msm8998-mdp5 */ + "qcom,sdm630-mdp5", + "qcom,sdm660-mdp5", + NULL +}; + /* list all platforms supported by both mdp5 and dpu drivers */ static const char *const msm_mdp5_dpu_migration[] =3D { "qcom,msm8917-mdp5", "qcom,msm8937-mdp5", "qcom,msm8953-mdp5", "qcom,msm8996-mdp5", - "qcom,sdm630-mdp5", - "qcom,sdm660-mdp5", NULL, }; =20 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver) { - /* If it is not an MDP5 device, do not try MDP5 driver */ + /* If it is not an MDP5 device, use DPU */ if (!of_device_is_compatible(dev->of_node, "qcom,mdp5")) return dpu_driver; =20 + /* If it is no longer supported by MDP5, use DPU */ + if (of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migrated)) + return dpu_driver; + /* If it is not in the migration list, use MDP5 */ if (!of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migration)) return !dpu_driver; --- base-commit: f2d03d96ebe8f6948cea9a47d11728f42d62d0f9 change-id: 20250926-mdp5-drop-dpu3-38bc04d44103 Best regards, --=20 With best wishes Dmitry