From nobody Tue Dec 16 20:32:27 2025 Received: from smtp.gentoo.org (woodpecker.gentoo.org [140.211.166.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E62C426D4F9; Thu, 11 Dec 2025 01:20:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=140.211.166.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765416066; cv=none; b=JONnPdaSrcXoZww3tv0HKoUUcDUfKYtW06UL9QFNaF3Kj7fVvkB6z1DLb9flqJDiXKHcndP6jhFto+jsfb5/nCZgqIG7ZMaRY2V8N9zaGy1voOkz7prokxB6NUJsdCvCllCvG3AR+QoWMrmfugRztUt/Xlm7w1PoHBD/2nFTnro= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765416066; c=relaxed/simple; bh=w4Cl85pajDu4fEzFy8PeC/kq5k5g5vzkpBBf3fmtdZ4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IwnRE0nbaMkAMZbWae3V//yxLkObYxtrw9Wm2beCHjwyg4d7aOec185F4c9SlzuXYf8eCPG/kHnZIcoGz7pNU6orvlZw5Mq1cxnHGZtCi0SuQH9mUcJqAgoqP2MqOFOUg2JIAHaKX0gTmgcAAUpp4fowajxN/hI+4fUuwu0joqg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gentoo.org; spf=pass smtp.mailfrom=gentoo.org; arc=none smtp.client-ip=140.211.166.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gentoo.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gentoo.org Received: from [127.0.0.1] (unknown [116.232.18.222]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dlan) by smtp.gentoo.org (Postfix) with ESMTPSA id C43F3340C39; Thu, 11 Dec 2025 01:20:51 +0000 (UTC) From: Yixun Lan Date: Thu, 11 Dec 2025 09:19:44 +0800 Subject: [PATCH RFC 4/4] clk: spacemit: k3: add the clock tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251211-k3-clk-v1-4-8ee47c70c5bc@gentoo.org> References: <20251211-k3-clk-v1-0-8ee47c70c5bc@gentoo.org> In-Reply-To: <20251211-k3-clk-v1-0-8ee47c70c5bc@gentoo.org> To: Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Haylen Chu , Inochi Amaoto , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=87116; i=dlan@gentoo.org; h=from:subject:message-id; bh=w4Cl85pajDu4fEzFy8PeC/kq5k5g5vzkpBBf3fmtdZ4=; b=owEB6QIW/ZANAwAKATGq6kdZTbvtAcsmYgBpOhxedi+1YZkLge25wsEng9216B96idC35Xbti 8PE1QyOJJWJAq8EAAEKAJkWIQS1urjJwxtxFWcCI9wxqupHWU277QUCaTocXhsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMSwyLDJfFIAAAAAALgAoaXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5 maWZ0aGhvcnNlbWFuLm5ldEI1QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRU QACgkQMarqR1lNu+3/+w//W1zxeKftN0sWfNjzYkzMTWq5J1PEatevdImEZoA6KOm3j34bJRQVC jIYdBahgLlSS6yF7Ns0lPV1G5a45xkwySgd9x9VFAuk4m5fFUpjOzhBPj9sfTfEaSyl7vxVRv/X EhYudNxpJeMuYa0Tmfku5/SRC83ygX83Prk1ya31kdahJIxF+nXSUYir8pd5G36E2q4N/Mo04+y oiZKTAaenOYvnLkKuuB5uSbUXuE9+i/xi9ScKdgJXO9QIfHr8nWOystB/JUSIkwtuJ7H6VZQkzH cxRM1jTA7ZruGi25gQ3P5m3F9yc0i6LnPcL+T4G0W971M2CJtmHyUIoBfPrXksU+RIA1QrwjU8J LajjnBC5pPMdeZRFBea5F0gAJiq82s6Vjdg9xwb8LOoZ0JyfiLEb/XsWTp0nsrgDHy0x+BlFrTb HQUCkN2VTOBs3E07trIo21TyFQEB2VW9qJ1uBX9mLyvGP+F1f9wdIumSw8KQ5yFv2OFEwTaaHc/ ZRxDuHPUXRD3ivmY+MEP5xdPjsJaq0yxq7WXzZUWtFvnCjISac3uK7hLm2R7OIso7NUrPGom0kG N0GlbgvNv6+gcdPIC30fmEGPb4NYfZLicAEZRomYt5fK7uyr5o2JwjI96WKxaD7QjQIWkhHPmvj DQCi6FtOv6U7IAT4OYWMeR9V+I0tMk= X-Developer-Key: i=dlan@gentoo.org; a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 Add clock support to SpacemiT K3 SoC, the clock tree consist of several blocks which are APBC, APBS, APMU, DCIU, MPUM. Signed-off-by: Yixun Lan --- drivers/clk/spacemit/Kconfig | 6 + drivers/clk/spacemit/Makefile | 11 +- drivers/clk/spacemit/ccu-k3.c | 1641 ++++++++++++++++++++++++++++++++++= ++++ include/soc/spacemit/ccu.h | 18 + include/soc/spacemit/k1-syscon.h | 12 +- include/soc/spacemit/k3-syscon.h | 273 +++++++ 6 files changed, 1947 insertions(+), 14 deletions(-) diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig index 3854f6ae6d0e..9d0b89f41ee4 100644 --- a/drivers/clk/spacemit/Kconfig +++ b/drivers/clk/spacemit/Kconfig @@ -16,4 +16,10 @@ config SPACEMIT_K1_CCU help Support for clock controller unit in SpacemiT K1 SoC. =20 +config SPACEMIT_K3_CCU + tristate "Support for SpacemiT K3 SoC" + depends on ARCH_SPACEMIT || COMPILE_TEST + help + Support for clock controller unit in SpacemiT K3 SoC. + endif diff --git a/drivers/clk/spacemit/Makefile b/drivers/clk/spacemit/Makefile index 5ec6da61db98..6e1724c0447d 100644 --- a/drivers/clk/spacemit/Makefile +++ b/drivers/clk/spacemit/Makefile @@ -1,5 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 =20 -obj-$(CONFIG_SPACEMIT_K1_CCU) =3D spacemit-ccu-k1.o -spacemit-ccu-k1-y =3D ccu_pll.o ccu_mix.o ccu_ddn.o -spacemit-ccu-k1-y +=3D ccu-k1.o +obj-$(CONFIG_SPACEMIT_CCU) +=3D spacemit-ccu.o +spacemit-ccu-objs :=3D ccu_pll.o ccu_mix.o ccu_ddn.o + +obj-$(CONFIG_SPACEMIT_K1_CCU) +=3D spacemit-ccu-k1.o +spacemit-ccu-k1-y :=3D ccu-k1.o + +obj-$(CONFIG_SPACEMIT_K3_CCU) +=3D spacemit-ccu-k3.o +spacemit-ccu-k3-y :=3D ccu-k3.o diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c new file mode 100644 index 000000000000..948889e8ca8c --- /dev/null +++ b/drivers/clk/spacemit/ccu-k3.c @@ -0,0 +1,1641 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 SpacemiT Technology Co. Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ccu_common.h" +#include "ccu_pll.h" +#include "ccu_mix.h" +#include "ccu_ddn.h" + +#include + +struct spacemit_ccu_data { + const char *reset_name; + struct clk_hw **hws; + size_t num; +}; + +/* APBS clocks start, APBS region contains and only contains all PLL clock= s */ + +/* + * PLL{1,2} must run at fixed frequencies to provide clocks in correct rat= es for + * peripherals. + */ +static const struct ccu_pll_rate_tbl pll1_rate_tbl[] =3D { + CCU_PLLA_RATE(2457600000UL, 0x0b330ccc, 0x0000cd00, 0xa0558989), +}; + +static const struct ccu_pll_rate_tbl pll2_rate_tbl[] =3D { + CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c), +}; + +static const struct ccu_pll_rate_tbl pll3_rate_tbl[] =3D { + CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), +}; + +static const struct ccu_pll_rate_tbl pll4_rate_tbl[] =3D { + CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), +}; + +static const struct ccu_pll_rate_tbl pll5_rate_tbl[] =3D { + CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), +}; + +static const struct ccu_pll_rate_tbl pll6_rate_tbl[] =3D { + CCU_PLLA_RATE(3200000000UL, 0x0b422aaa, 0x0000ab00, 0xa0558e8e), +}; + +static const struct ccu_pll_rate_tbl pll7_rate_tbl[] =3D { + CCU_PLLA_RATE(2800000000UL, 0x0b3a1555, 0x00005500, 0xa0558b8b), +}; + +static const struct ccu_pll_rate_tbl pll8_rate_tbl[] =3D { + CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), +}; + +CCU_PLLA_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR2, APB= S_PLL1_SWCR3, + MPMU_POSR, POSR_PLL1_LOCK, CLK_SET_RATE_GATE); +CCU_PLLA_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR2, APB= S_PLL2_SWCR3, + MPMU_POSR, POSR_PLL2_LOCK, CLK_SET_RATE_GATE); +CCU_PLLA_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR2, APB= S_PLL3_SWCR3, + MPMU_POSR, POSR_PLL3_LOCK, CLK_SET_RATE_GATE); +CCU_PLLA_DEFINE(pll4, pll4_rate_tbl, APBS_PLL4_SWCR1, APBS_PLL4_SWCR2, APB= S_PLL4_SWCR3, + MPMU_POSR, POSR_PLL4_LOCK, CLK_SET_RATE_GATE); +CCU_PLLA_DEFINE(pll5, pll5_rate_tbl, APBS_PLL5_SWCR1, APBS_PLL5_SWCR2, APB= S_PLL5_SWCR3, + MPMU_POSR, POSR_PLL5_LOCK, CLK_SET_RATE_GATE); +CCU_PLLA_DEFINE(pll6, pll6_rate_tbl, APBS_PLL6_SWCR1, APBS_PLL6_SWCR2, APB= S_PLL6_SWCR3, + MPMU_POSR, POSR_PLL6_LOCK, CLK_SET_RATE_GATE); +CCU_PLLA_DEFINE(pll7, pll7_rate_tbl, APBS_PLL7_SWCR1, APBS_PLL7_SWCR2, APB= S_PLL7_SWCR3, + MPMU_POSR, POSR_PLL7_LOCK, CLK_SET_RATE_GATE); +CCU_PLLA_DEFINE(pll8, pll8_rate_tbl, APBS_PLL8_SWCR1, APBS_PLL8_SWCR2, APB= S_PLL8_SWCR3, + MPMU_POSR, POSR_PLL8_LOCK, CLK_SET_RATE_GATE); + +CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(= 1), 2, 1); +CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(= 2), 3, 1); +CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(= 3), 4, 1); +CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(= 4), 5, 1); +CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(= 5), 6, 1); +CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(= 6), 7, 1); +CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2= , BIT(7), 8, 1, + CLK_IS_CRITICAL); +CCU_DIV_GATE_DEFINE(pll1_dx, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, 23, 5, = BIT(22), 0); +CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2= , BIT(31), 64, 1); +CCU_FACTOR_GATE_DEFINE(pll1_aud_245p7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR= 2, BIT(21), 10, 1); +CCU_FACTOR_DEFINE(pll1_aud_24p5, CCU_PARENT_HW(pll1_aud_245p7), 10, 1); + +CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(= 0), 1, 1); +CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(= 1), 2, 1); +CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(= 2), 3, 1); +CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(= 3), 4, 1); +CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(= 4), 5, 1); +CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(= 5), 6, 1); +CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(= 6), 7, 1); +CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(= 7), 8, 1); +CCU_FACTOR_DEFINE(pll2_66, CCU_PARENT_HW(pll2_d5), 9, 1); +CCU_FACTOR_DEFINE(pll2_33, CCU_PARENT_HW(pll2_66), 2, 1); +CCU_FACTOR_DEFINE(pll2_50, CCU_PARENT_HW(pll2_d5), 12, 1); +CCU_FACTOR_DEFINE(pll2_25, CCU_PARENT_HW(pll2_50), 2, 1); +CCU_FACTOR_DEFINE(pll2_20, CCU_PARENT_HW(pll2_d5), 30, 1); +CCU_FACTOR_DEFINE(pll2_d24_125, CCU_PARENT_HW(pll2_d3), 8, 1); +CCU_FACTOR_DEFINE(pll2_d120_25, CCU_PARENT_HW(pll2_d3), 40, 1); + +CCU_FACTOR_GATE_DEFINE(pll3_d1, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(= 0), 1, 1); +CCU_FACTOR_GATE_DEFINE(pll3_d2, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(= 1), 2, 1); +CCU_FACTOR_GATE_DEFINE(pll3_d3, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(= 2), 3, 1); +CCU_FACTOR_GATE_DEFINE(pll3_d4, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(= 3), 4, 1); +CCU_FACTOR_GATE_DEFINE(pll3_d5, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(= 4), 5, 1); +CCU_FACTOR_GATE_DEFINE(pll3_d6, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(= 5), 6, 1); +CCU_FACTOR_GATE_DEFINE(pll3_d7, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(= 6), 7, 1); +CCU_FACTOR_GATE_DEFINE(pll3_d8, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(= 7), 8, 1); + +CCU_FACTOR_GATE_DEFINE(pll4_d1, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(= 0), 1, 1); +CCU_FACTOR_GATE_DEFINE(pll4_d2, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(= 1), 2, 1); +CCU_FACTOR_GATE_DEFINE(pll4_d3, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(= 2), 3, 1); +CCU_FACTOR_GATE_DEFINE(pll4_d4, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(= 3), 4, 1); +CCU_FACTOR_GATE_DEFINE(pll4_d5, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(= 4), 5, 1); +CCU_FACTOR_GATE_DEFINE(pll4_d6, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(= 5), 6, 1); +CCU_FACTOR_GATE_DEFINE(pll4_d7, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(= 6), 7, 1); +CCU_FACTOR_GATE_DEFINE(pll4_d8, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(= 7), 8, 1); + +CCU_FACTOR_GATE_DEFINE(pll5_d1, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(= 0), 1, 1); +CCU_FACTOR_GATE_DEFINE(pll5_d2, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(= 1), 2, 1); +CCU_FACTOR_GATE_DEFINE(pll5_d3, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(= 2), 3, 1); +CCU_FACTOR_GATE_DEFINE(pll5_d4, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(= 3), 4, 1); +CCU_FACTOR_GATE_DEFINE(pll5_d5, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(= 4), 5, 1); +CCU_FACTOR_GATE_DEFINE(pll5_d6, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(= 5), 6, 1); +CCU_FACTOR_GATE_DEFINE(pll5_d7, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(= 6), 7, 1); +CCU_FACTOR_GATE_DEFINE(pll5_d8, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(= 7), 8, 1); + +CCU_FACTOR_GATE_DEFINE(pll6_d1, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(= 0), 1, 1); +CCU_FACTOR_GATE_DEFINE(pll6_d2, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(= 1), 2, 1); +CCU_FACTOR_GATE_DEFINE(pll6_d3, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(= 2), 3, 1); +CCU_FACTOR_GATE_DEFINE(pll6_d4, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(= 3), 4, 1); +CCU_FACTOR_GATE_DEFINE(pll6_d5, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(= 4), 5, 1); +CCU_FACTOR_GATE_DEFINE(pll6_d6, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(= 5), 6, 1); +CCU_FACTOR_GATE_DEFINE(pll6_d7, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(= 6), 7, 1); +CCU_FACTOR_GATE_DEFINE(pll6_d8, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(= 7), 8, 1); +CCU_FACTOR_DEFINE(pll6_80, CCU_PARENT_HW(pll6_d5), 8, 1); +CCU_FACTOR_DEFINE(pll6_40, CCU_PARENT_HW(pll6_d5), 16, 1); +CCU_FACTOR_DEFINE(pll6_20, CCU_PARENT_HW(pll6_d5), 32, 1); + +CCU_FACTOR_GATE_DEFINE(pll7_d1, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(= 0), 1, 1); +CCU_FACTOR_GATE_DEFINE(pll7_d2, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(= 1), 2, 1); +CCU_FACTOR_GATE_DEFINE(pll7_d3, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(= 2), 3, 1); +CCU_FACTOR_GATE_DEFINE(pll7_d4, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(= 3), 4, 1); +CCU_FACTOR_GATE_DEFINE(pll7_d5, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(= 4), 5, 1); +CCU_FACTOR_GATE_DEFINE(pll7_d6, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(= 5), 6, 1); +CCU_FACTOR_GATE_DEFINE(pll7_d7, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(= 6), 7, 1); +CCU_FACTOR_GATE_DEFINE(pll7_d8, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(= 7), 8, 1); + +CCU_FACTOR_GATE_DEFINE(pll8_d1, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(= 0), 1, 1); +CCU_FACTOR_GATE_DEFINE(pll8_d2, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(= 1), 2, 1); +CCU_FACTOR_GATE_DEFINE(pll8_d3, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(= 2), 3, 1); +CCU_FACTOR_GATE_DEFINE(pll8_d4, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(= 3), 4, 1); +CCU_FACTOR_GATE_DEFINE(pll8_d5, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(= 4), 5, 1); +CCU_FACTOR_GATE_DEFINE(pll8_d6, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(= 5), 6, 1); +CCU_FACTOR_GATE_DEFINE(pll8_d7, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(= 6), 7, 1); +CCU_FACTOR_GATE_DEFINE(pll8_d8, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(= 7), 8, 1); +/* APBS clocks end */ + +/* MPMU clocks start */ +CCU_GATE_DEFINE(pll1_d8_307p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(13),= 0); +CCU_FACTOR_DEFINE(pll1_d32_76p8, CCU_PARENT_HW(pll1_d8_307p2), 4, 1); +CCU_FACTOR_DEFINE(pll1_d40_61p44, CCU_PARENT_HW(pll1_d8_307p2), 5, 1); +CCU_FACTOR_DEFINE(pll1_d16_153p6, CCU_PARENT_HW(pll1_d8), 2, 1); +CCU_FACTOR_GATE_DEFINE(pll1_d24_102p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, = BIT(12), 3, 1); +CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, B= IT(7), 6, 1); +CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2_ap, CCU_PARENT_HW(pll1_d8), MPMU_ACGR= , BIT(11), 6, 1); +CCU_FACTOR_GATE_DEFINE(pll1_m3d128_57p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR= , BIT(8), 16, 3); +CCU_FACTOR_GATE_DEFINE(pll1_d96_25p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, B= IT(4), 12, 1); +CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, = BIT(3), 24, 1); +CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8_wdt, CCU_PARENT_HW(pll1_d8), MPMU_AC= GR, BIT(19), 24, 1); +CCU_FACTOR_GATE_DEFINE(pll1_d384_6p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, B= IT(2), 48, 1); + +CCU_FACTOR_DEFINE(pll1_d768_3p2, CCU_PARENT_HW(pll1_d384_6p4), 2, 1); +CCU_FACTOR_DEFINE(pll1_d1536_1p6, CCU_PARENT_HW(pll1_d384_6p4), 4, 1); +CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1); + +CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), = 0); +CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, = BIT(5), 2, 1); + +CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21)= , 0); +CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR,= BIT(18), 2, 1); + +CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15),= 0); +CCU_FACTOR_GATE_DEFINE(pll1_d52_47p26, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, = BIT(10), 13, 1); +CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, B= IT(6), 39, 2); + +CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14),= 0); + +CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16)= , 0); + +static const struct clk_parent_data apb_parents[] =3D { + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d24_102p4), +}; +CCU_MUX_DEFINE(apb_clk, apb_parents, MPMU_APBCSCR, 0, 2, 0); + +CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc_32k), MPMU_ACGR, BIT(1), CL= K_IGNORE_UNUSED); +CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13= , 2, 0); +CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, = 2, 0); + +CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1)= , 0); +CCU_GATE_DEFINE(wdt_bus_clk, CCU_PARENT_HW(apb_clk), MPMU_WDTPCR, BIT(0), = 0); + +CCU_GATE_DEFINE(r_ipc_clk, CCU_PARENT_HW(apb_clk), MPMU_RIPCCR, BIT(0), 0); + +CCU_FACTOR_DEFINE(i2s_153p6, CCU_PARENT_HW(pll1_d8_307p2), 2, 1); + +static const struct clk_parent_data i2s_153p6_base_parents[] =3D { + CCU_PARENT_HW(i2s_153p6), + CCU_PARENT_HW(pll1_d8_307p2), +}; +CCU_MUX_DEFINE(i2s_153p6_base, i2s_153p6_base_parents, MPMU_FCCR, 29, 1, 0= ); + +static const struct clk_parent_data i2s_sysclk_src_parents[] =3D { + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(i2s_153p6_base), +}; +CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30= , 1, BIT(31), 0); + +CCU_DDN_DEFINE(i2s1_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, = 0); + +CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s1_sysclk), MPMU_ISCCR, 27, = 2, BIT(29), 0); + +static const struct clk_parent_data i2s_sysclk_parents[] =3D { + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_NAME(vctcxo_24m), + CCU_PARENT_HW(pll2_d5), + CCU_PARENT_NAME(vctcxo_24m), +}; +CCU_MUX_DEFINE(i2s0_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, = 0, 2, 0); +CCU_MUX_DEFINE(i2s2_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, = 4, 2, 0); +CCU_MUX_DEFINE(i2s3_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, = 12, 2, 0); +CCU_MUX_DEFINE(i2s4_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, = 16, 2, 0); +CCU_MUX_DEFINE(i2s5_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, = 20, 2, 0); + +CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, = 16, 16, 1, 0); +CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, = 16, 16, 1, 0); +CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, = 16, 16, 1, 0); +CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, = 16, 16, 1, 0); +CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, = 16, 16, 1, 0); + +static const struct clk_parent_data i2s2_sysclk_parents[] =3D { + CCU_PARENT_HW(i2s1_sysclk), + CCU_PARENT_HW(i2s2_sysclk_div), +}; +CCU_GATE_DEFINE(i2s0_sysclk, CCU_PARENT_HW(i2s0_sysclk_div), MPMU_I2S_SYSC= LK_CTRL, BIT(2), 0); +CCU_MUX_GATE_DEFINE(i2s2_sysclk, i2s2_sysclk_parents, MPMU_I2S_SYSCLK_CTRL= , 8, 1, BIT(6), 0); +CCU_GATE_DEFINE(i2s3_sysclk, CCU_PARENT_HW(i2s3_sysclk_div), MPMU_I2S_SYSC= LK_CTRL, BIT(14), 0); +CCU_GATE_DEFINE(i2s4_sysclk, CCU_PARENT_HW(i2s4_sysclk_div), MPMU_I2S_SYSC= LK_CTRL, BIT(18), 0); +CCU_GATE_DEFINE(i2s5_sysclk, CCU_PARENT_HW(i2s5_sysclk_div), MPMU_I2S_SYSC= LK_CTRL, BIT(22), 0); +/* MPMU clocks end */ + +/* APBC clocks start */ +static const struct clk_parent_data uart_clk_parents[] =3D { + CCU_PARENT_HW(pll1_m3d128_57p6), + CCU_PARENT_HW(slow_uart1_14p74), + CCU_PARENT_HW(slow_uart2_48), +}; +CCU_MUX_GATE_DEFINE(uart0_clk, uart_clk_parents, APBC_UART0_CLK_RST, 4, 3,= BIT(1), 0); +CCU_MUX_GATE_DEFINE(uart2_clk, uart_clk_parents, APBC_UART2_CLK_RST, 4, 3,= BIT(1), 0); +CCU_MUX_GATE_DEFINE(uart3_clk, uart_clk_parents, APBC_UART3_CLK_RST, 4, 3,= BIT(1), 0); +CCU_MUX_GATE_DEFINE(uart4_clk, uart_clk_parents, APBC_UART4_CLK_RST, 4, 3,= BIT(1), 0); +CCU_MUX_GATE_DEFINE(uart5_clk, uart_clk_parents, APBC_UART5_CLK_RST, 4, 3,= BIT(1), 0); +CCU_MUX_GATE_DEFINE(uart6_clk, uart_clk_parents, APBC_UART6_CLK_RST, 4, 3,= BIT(1), 0); +CCU_MUX_GATE_DEFINE(uart7_clk, uart_clk_parents, APBC_UART7_CLK_RST, 4, 3,= BIT(1), 0); +CCU_MUX_GATE_DEFINE(uart8_clk, uart_clk_parents, APBC_UART8_CLK_RST, 4, 3,= BIT(1), 0); +CCU_MUX_GATE_DEFINE(uart9_clk, uart_clk_parents, APBC_UART9_CLK_RST, 4, 3,= BIT(1), 0); +CCU_MUX_GATE_DEFINE(uart10_clk, uart_clk_parents, APBC_UART10_CLK_RST, 4, = 3, BIT(1), 0); + +CCU_GATE_DEFINE(uart0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART0_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(uart2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART2_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(uart3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART3_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(uart4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART4_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(uart5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART5_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(uart6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART6_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(uart7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART7_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(uart8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART8_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(uart9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART9_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(uart10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART10_CLK_RS= T, BIT(0), 0); + +CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, = BIT(1), 0); +CCU_GATE_DEFINE(gpio_bus_clk, CCU_PARENT_HW(apb_clk), APBC_GPIO_CLK_RST, B= IT(0), 0); + +static const struct clk_parent_data pwm_parents[] =3D { + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_NAME(osc_32k), +}; +CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(pwm9_clk, pwm_parents, APBC_PWM9_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(pwm10_clk, pwm_parents, APBC_PWM10_CLK_RST, 4, 3, BIT(= 1), 0); +CCU_MUX_GATE_DEFINE(pwm11_clk, pwm_parents, APBC_PWM11_CLK_RST, 4, 3, BIT(= 1), 0); +CCU_MUX_GATE_DEFINE(pwm12_clk, pwm_parents, APBC_PWM12_CLK_RST, 4, 3, BIT(= 1), 0); +CCU_MUX_GATE_DEFINE(pwm13_clk, pwm_parents, APBC_PWM13_CLK_RST, 4, 3, BIT(= 1), 0); +CCU_MUX_GATE_DEFINE(pwm14_clk, pwm_parents, APBC_PWM14_CLK_RST, 4, 3, BIT(= 1), 0); +CCU_MUX_GATE_DEFINE(pwm15_clk, pwm_parents, APBC_PWM15_CLK_RST, 4, 3, BIT(= 1), 0); +CCU_MUX_GATE_DEFINE(pwm16_clk, pwm_parents, APBC_PWM16_CLK_RST, 4, 3, BIT(= 1), 0); +CCU_MUX_GATE_DEFINE(pwm17_clk, pwm_parents, APBC_PWM17_CLK_RST, 4, 3, BIT(= 1), 0); +CCU_MUX_GATE_DEFINE(pwm18_clk, pwm_parents, APBC_PWM18_CLK_RST, 4, 3, BIT(= 1), 0); +CCU_MUX_GATE_DEFINE(pwm19_clk, pwm_parents, APBC_PWM19_CLK_RST, 4, 3, BIT(= 1), 0); + +CCU_GATE_DEFINE(pwm0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM0_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(pwm1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM1_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(pwm2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM2_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(pwm3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM3_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(pwm4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM4_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(pwm5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM5_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(pwm6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM6_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(pwm7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM7_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(pwm8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM8_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(pwm9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM9_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(pwm10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM10_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(pwm11_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM11_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(pwm12_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM12_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(pwm13_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM13_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(pwm14_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM14_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(pwm15_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM15_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(pwm16_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM16_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(pwm17_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM17_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(pwm18_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM18_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(pwm19_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM19_CLK_RST,= BIT(0), 0); + +static const struct clk_parent_data i2s_bclk_parents[] =3D { + CCU_PARENT_NAME(vctcxo_1m), + CCU_PARENT_HW(i2s_bclk), +}; +CCU_MUX_DEFINE(spi0_i2s_bclk, i2s_bclk_parents, APBC_SSP0_CLK_RST, 3, 1, 0= ); +CCU_MUX_DEFINE(spi1_i2s_bclk, i2s_bclk_parents, APBC_SSP1_CLK_RST, 3, 1, 0= ); +CCU_MUX_DEFINE(spi3_i2s_bclk, i2s_bclk_parents, APBC_SSP3_CLK_RST, 3, 1, 0= ); + +static const struct clk_parent_data spi0_parents[] =3D { + CCU_PARENT_HW(pll1_d384_6p4), + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d768_3p2), + CCU_PARENT_HW(pll1_d1536_1p6), + CCU_PARENT_HW(pll1_d3072_0p8), + CCU_PARENT_HW(spi0_i2s_bclk), +}; +CCU_MUX_GATE_DEFINE(spi0_clk, spi0_parents, APBC_SSP0_CLK_RST, 4, 3, BIT(1= ), 0); + +static const struct clk_parent_data spi1_parents[] =3D { + CCU_PARENT_HW(pll1_d384_6p4), + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d768_3p2), + CCU_PARENT_HW(pll1_d1536_1p6), + CCU_PARENT_HW(pll1_d3072_0p8), + CCU_PARENT_HW(spi1_i2s_bclk), +}; +CCU_MUX_GATE_DEFINE(spi1_clk, spi1_parents, APBC_SSP1_CLK_RST, 4, 3, BIT(1= ), 0); + +static const struct clk_parent_data spi3_parents[] =3D { + CCU_PARENT_HW(pll1_d384_6p4), + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d768_3p2), + CCU_PARENT_HW(pll1_d1536_1p6), + CCU_PARENT_HW(pll1_d3072_0p8), + CCU_PARENT_HW(spi3_i2s_bclk), +}; +CCU_MUX_GATE_DEFINE(spi3_clk, spi3_parents, APBC_SSP3_CLK_RST, 4, 3, BIT(1= ), 0); + +CCU_GATE_DEFINE(spi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP0_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(spi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP1_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(spi3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP3_CLK_RST, B= IT(0), 0); + + +CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc_32k), APBC_RTC_CLK_RST, + BIT(7) | BIT(1), 0); +CCU_GATE_DEFINE(rtc_bus_clk, CCU_PARENT_HW(apb_clk), APBC_RTC_CLK_RST, BIT= (0), 0); + +static const struct clk_parent_data twsi_parents[] =3D { + CCU_PARENT_HW(pll1_d78_31p5), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d40_61p44), +}; +CCU_MUX_GATE_DEFINE(twsi0_clk, twsi_parents, APBC_TWSI0_CLK_RST, 4, 3, BIT= (1), 0); +CCU_MUX_GATE_DEFINE(twsi1_clk, twsi_parents, APBC_TWSI1_CLK_RST, 4, 3, BIT= (1), 0); +CCU_MUX_GATE_DEFINE(twsi2_clk, twsi_parents, APBC_TWSI2_CLK_RST, 4, 3, BIT= (1), 0); +CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT= (1), 0); +CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT= (1), 0); +CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT= (1), 0); +CCU_MUX_GATE_DEFINE(twsi8_clk, twsi_parents, APBC_TWSI8_CLK_RST, 4, 3, BIT= (1), 0); + +CCU_GATE_DEFINE(twsi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI0_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(twsi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI1_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(twsi2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI2_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST,= BIT(0), 0); +CCU_GATE_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI8_CLK_RST,= BIT(0), 0); + +static const struct clk_parent_data timer_parents[] =3D { + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_NAME(osc_32k), + CCU_PARENT_HW(pll1_d384_6p4), + CCU_PARENT_NAME(vctcxo_3m), + CCU_PARENT_NAME(vctcxo_1m), +}; +CCU_MUX_GATE_DEFINE(timers0_clk, timer_parents, APBC_TIMERS0_CLK_RST, 4, 3= , BIT(1), 0); +CCU_MUX_GATE_DEFINE(timers1_clk, timer_parents, APBC_TIMERS1_CLK_RST, 4, 3= , BIT(1), 0); +CCU_MUX_GATE_DEFINE(timers2_clk, timer_parents, APBC_TIMERS2_CLK_RST, 4, 3= , BIT(1), 0); +CCU_MUX_GATE_DEFINE(timers3_clk, timer_parents, APBC_TIMERS3_CLK_RST, 4, 3= , BIT(1), 0); +CCU_MUX_GATE_DEFINE(timers4_clk, timer_parents, APBC_TIMERS4_CLK_RST, 4, 3= , BIT(1), 0); +CCU_MUX_GATE_DEFINE(timers5_clk, timer_parents, APBC_TIMERS5_CLK_RST, 4, 3= , BIT(1), 0); +CCU_MUX_GATE_DEFINE(timers6_clk, timer_parents, APBC_TIMERS6_CLK_RST, 4, 3= , BIT(1), 0); +CCU_MUX_GATE_DEFINE(timers7_clk, timer_parents, APBC_TIMERS7_CLK_RST, 4, 3= , BIT(1), 0); + +CCU_GATE_DEFINE(timers0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS0_CLK_= RST, BIT(0), 0); +CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_= RST, BIT(0), 0); +CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_= RST, BIT(0), 0); +CCU_GATE_DEFINE(timers3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS3_CLK_= RST, BIT(0), 0); +CCU_GATE_DEFINE(timers4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS4_CLK_= RST, BIT(0), 0); +CCU_GATE_DEFINE(timers5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS5_CLK_= RST, BIT(0), 0); +CCU_GATE_DEFINE(timers6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS6_CLK_= RST, BIT(0), 0); +CCU_GATE_DEFINE(timers7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS7_CLK_= RST, BIT(0), 0); + +CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BI= T(1), 0); +CCU_GATE_DEFINE(aib_bus_clk, CCU_PARENT_HW(apb_clk), APBC_AIB_CLK_RST, BIT= (0), 0); + +CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK= _RST, BIT(1), 0); +CCU_GATE_DEFINE(onewire_bus_clk, CCU_PARENT_HW(apb_clk), APBC_ONEWIRE_CLK_= RST, BIT(0), 0); + +/* + * When i2s_bclk is selected as the parent clock of sspa, + * the hardware requires bit3 to be set + */ + +CCU_MUX_DEFINE(i2s0_i2s_bclk, i2s_bclk_parents, APBC_SSPA0_CLK_RST, 3, 1, = 0); +CCU_MUX_DEFINE(i2s1_i2s_bclk, i2s_bclk_parents, APBC_SSPA1_CLK_RST, 3, 1, = 0); +CCU_MUX_DEFINE(i2s2_i2s_bclk, i2s_bclk_parents, APBC_SSPA2_CLK_RST, 3, 1, = 0); +CCU_MUX_DEFINE(i2s3_i2s_bclk, i2s_bclk_parents, APBC_SSPA3_CLK_RST, 3, 1, = 0); +CCU_MUX_DEFINE(i2s4_i2s_bclk, i2s_bclk_parents, APBC_SSPA4_CLK_RST, 3, 1, = 0); +CCU_MUX_DEFINE(i2s5_i2s_bclk, i2s_bclk_parents, APBC_SSPA5_CLK_RST, 3, 1, = 0); + +static const struct clk_parent_data i2s0_parents[] =3D { + CCU_PARENT_HW(pll1_d384_6p4), + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d768_3p2), + CCU_PARENT_HW(pll1_d1536_1p6), + CCU_PARENT_HW(pll1_d3072_0p8), + CCU_PARENT_HW(i2s0_i2s_bclk), +}; +CCU_MUX_GATE_DEFINE(i2s0_clk, i2s0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(= 1), 0); + +static const struct clk_parent_data i2s1_parents[] =3D { + CCU_PARENT_HW(pll1_d384_6p4), + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d768_3p2), + CCU_PARENT_HW(pll1_d1536_1p6), + CCU_PARENT_HW(pll1_d3072_0p8), + CCU_PARENT_HW(i2s1_i2s_bclk), +}; +CCU_MUX_GATE_DEFINE(i2s1_clk, i2s1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(= 1), 0); + +static const struct clk_parent_data i2s2_parents[] =3D { + CCU_PARENT_HW(pll1_d384_6p4), + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d768_3p2), + CCU_PARENT_HW(pll1_d1536_1p6), + CCU_PARENT_HW(pll1_d3072_0p8), + CCU_PARENT_HW(i2s2_i2s_bclk), +}; +CCU_MUX_GATE_DEFINE(i2s2_clk, i2s2_parents, APBC_SSPA2_CLK_RST, 4, 3, BIT(= 1), 0); + +static const struct clk_parent_data i2s3_parents[] =3D { + CCU_PARENT_HW(pll1_d384_6p4), + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d768_3p2), + CCU_PARENT_HW(pll1_d1536_1p6), + CCU_PARENT_HW(pll1_d3072_0p8), + CCU_PARENT_HW(i2s3_i2s_bclk), +}; +CCU_MUX_GATE_DEFINE(i2s3_clk, i2s3_parents, APBC_SSPA3_CLK_RST, 4, 3, BIT(= 1), 0); + +static const struct clk_parent_data i2s4_parents[] =3D { + CCU_PARENT_HW(pll1_d384_6p4), + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d768_3p2), + CCU_PARENT_HW(pll1_d1536_1p6), + CCU_PARENT_HW(pll1_d3072_0p8), + CCU_PARENT_HW(i2s4_i2s_bclk), +}; +CCU_MUX_GATE_DEFINE(i2s4_clk, i2s4_parents, APBC_SSPA4_CLK_RST, 4, 3, BIT(= 1), 0); + +static const struct clk_parent_data i2s5_parents[] =3D { + CCU_PARENT_HW(pll1_d384_6p4), + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d768_3p2), + CCU_PARENT_HW(pll1_d1536_1p6), + CCU_PARENT_HW(pll1_d3072_0p8), + CCU_PARENT_HW(i2s5_i2s_bclk), +}; +CCU_MUX_GATE_DEFINE(i2s5_clk, i2s5_parents, APBC_SSPA5_CLK_RST, 4, 3, BIT(= 1), 0); + +CCU_GATE_DEFINE(i2s0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA0_CLK_RST, = BIT(0), 0); +CCU_GATE_DEFINE(i2s1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA1_CLK_RST, = BIT(0), 0); +CCU_GATE_DEFINE(i2s2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA2_CLK_RST, = BIT(0), 0); +CCU_GATE_DEFINE(i2s3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA3_CLK_RST, = BIT(0), 0); +CCU_GATE_DEFINE(i2s4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA4_CLK_RST, = BIT(0), 0); +CCU_GATE_DEFINE(i2s5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA5_CLK_RST, = BIT(0), 0); + +CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1),= 0); +CCU_GATE_DEFINE(ir0_clk, CCU_PARENT_HW(apb_clk), APBC_IR0_CLK_RST, BIT(1),= 0); +CCU_GATE_DEFINE(ir1_clk, CCU_PARENT_HW(apb_clk), APBC_IR1_CLK_RST, BIT(1),= 0); + +CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1= ), 0); +CCU_GATE_DEFINE(tsen_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, B= IT(0), 0); + +CCU_GATE_DEFINE(ipc_ap2rcpu_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_C= LK_RST, BIT(1), 0); +CCU_GATE_DEFINE(ipc_ap2rcpu_bus_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2A= UD_CLK_RST, BIT(0), 0); + +static const struct clk_parent_data can_parents[] =3D { + CCU_PARENT_HW(pll6_20), + CCU_PARENT_HW(pll6_40), + CCU_PARENT_HW(pll6_80), +}; +CCU_MUX_GATE_DEFINE(can0_clk, can_parents, APBC_CAN0_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(can1_clk, can_parents, APBC_CAN1_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(can2_clk, can_parents, APBC_CAN2_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(can3_clk, can_parents, APBC_CAN3_CLK_RST, 4, 3, BIT(1)= , 0); +CCU_MUX_GATE_DEFINE(can4_clk, can_parents, APBC_CAN4_CLK_RST, 4, 3, BIT(1)= , 0); + +CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN0_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(can1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN1_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(can2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN2_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(can3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN3_CLK_RST, B= IT(0), 0); +CCU_GATE_DEFINE(can4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN4_CLK_RST, B= IT(0), 0); +/* APBC clocks end */ + +/* APMU clocks start */ +static const struct clk_parent_data axi_clk_parents[] =3D { + CCU_PARENT_HW(pll1_d8_307p2), + CCU_PARENT_HW(pll1_d6_409p6), +}; +CCU_MUX_DIV_FC_DEFINE(axi_clk, axi_clk_parents, APMU_ACLK_CLK_CTRL, 1, 2, = BIT(4), 0, 1, 0); + +static const struct clk_parent_data cci550_clk_parents[] =3D { + CCU_PARENT_HW(pll1_d10_245p76), + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d3_819p2), + CCU_PARENT_HW(pll7_d3), + CCU_PARENT_HW(pll2_d3), + CCU_PARENT_HW(pll1_d2_1228p8), + CCU_PARENT_HW(pll7_d2), +}; +CCU_MUX_DIV_FC_DEFINE(cci550_clk, cci550_clk_parents, APMU_CCI550_CLK_CTRL= , 8, 2, BIT(12), 0, 3, + CLK_IS_CRITICAL); + +static const struct clk_parent_data cpu_c0_clk_parents[] =3D { + CCU_PARENT_HW(pll1_d3_819p2), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll2_d3), + CCU_PARENT_HW(pll3_d2), + CCU_PARENT_HW(pll1_d2_1228p8), + CCU_PARENT_HW(pll2_d2), + CCU_PARENT_HW(pll3_d1), +}; +CCU_MUX_DIV_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK= _CTRL, + 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); + +static const struct clk_parent_data cpu_c1_clk_parents[] =3D { + CCU_PARENT_HW(pll1_d3_819p2), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll2_d3), + CCU_PARENT_HW(pll4_d2), + CCU_PARENT_HW(pll1_d2_1228p8), + CCU_PARENT_HW(pll2_d2), + CCU_PARENT_HW(pll4_d1), +}; +CCU_MUX_DIV_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK= _CTRL, + 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); + +static const struct clk_parent_data cpu_c2_clk_parents[] =3D { + CCU_PARENT_HW(pll1_d3_819p2), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll2_d3), + CCU_PARENT_HW(pll5_d2), + CCU_PARENT_HW(pll1_d2_1228p8), + CCU_PARENT_HW(pll2_d2), + CCU_PARENT_HW(pll5_d1), +}; +CCU_MUX_DIV_FC_DEFINE(cpu_c2_core_clk, cpu_c2_clk_parents, APMU_CPU_C2_CLK= _CTRL, + 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); + +static const struct clk_parent_data cpu_c3_clk_parents[] =3D { + CCU_PARENT_HW(pll1_d3_819p2), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll2_d3), + CCU_PARENT_HW(pll8_d2), + CCU_PARENT_HW(pll1_d2_1228p8), + CCU_PARENT_HW(pll2_d2), + CCU_PARENT_HW(pll8_d1), +}; +CCU_MUX_DIV_FC_DEFINE(cpu_c3_core_clk, cpu_c3_clk_parents, APMU_CPU_C3_CLK= _CTRL, + 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); + +static const struct clk_parent_data ccic2phy_parents[] =3D { + CCU_PARENT_HW(pll1_d24_102p4), + CCU_PARENT_HW(pll1_d48_51p2_ap), +}; +CCU_MUX_GATE_DEFINE(ccic2phy_clk, ccic2phy_parents, APMU_CSI_CCIC2_CLK_RES= _CTRL, 7, 1, BIT(5), 0); + +static const struct clk_parent_data ccic3phy_parents[] =3D { + CCU_PARENT_HW(pll1_d24_102p4), + CCU_PARENT_HW(pll1_d48_51p2_ap), +}; +CCU_MUX_GATE_DEFINE(ccic3phy_clk, ccic3phy_parents, APMU_CSI_CCIC2_CLK_RES= _CTRL, 31, 1, BIT(30), 0); + +static const struct clk_parent_data csi_parents[] =3D { + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d3_819p2), + CCU_PARENT_HW(pll2_d2), + CCU_PARENT_HW(pll2_d3), + CCU_PARENT_HW(pll2_d4), + CCU_PARENT_HW(pll1_d2_1228p8), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(csi_clk, csi_parents, APMU_CSI_CCIC2_CLK_RES_CT= RL, 20, 3, BIT(15), + 16, 3, BIT(4), 0); + +static const struct clk_parent_data isp_bus_parents[] =3D { + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d10_245p76), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(isp_bus_clk, isp_bus_parents, APMU_ISP_CLK_RES_= CTRL, 18, 3, BIT(23), + 21, 2, BIT(17), 0); + +CCU_GATE_DEFINE(d1p_1228p8, CCU_PARENT_HW(pll1_d2_1228p8), APMU_PMU_CLK_GA= TE_CTRL, BIT(31), 0); +CCU_GATE_DEFINE(d1p_819p2, CCU_PARENT_HW(pll1_d3_819p2), APMU_PMU_CLK_GATE= _CTRL, BIT(30), 0); +CCU_GATE_DEFINE(d1p_614p4, CCU_PARENT_HW(pll1_d4_614p4), APMU_PMU_CLK_GATE= _CTRL, BIT(29), 0); +CCU_GATE_DEFINE(d1p_491p52, CCU_PARENT_HW(pll1_d5_491p52), APMU_PMU_CLK_GA= TE_CTRL, BIT(28), 0); +CCU_GATE_DEFINE(d1p_409p6, CCU_PARENT_HW(pll1_d6_409p6), APMU_PMU_CLK_GATE= _CTRL, BIT(27), 0); +CCU_GATE_DEFINE(d1p_307p2, CCU_PARENT_HW(pll1_d8_307p2), APMU_PMU_CLK_GATE= _CTRL, BIT(26), 0); +CCU_GATE_DEFINE(d1p_245p76, CCU_PARENT_HW(pll1_d10_245p76), APMU_PMU_CLK_G= ATE_CTRL, BIT(22), 0); + +static const struct clk_parent_data v2d_parents[] =3D { + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll2_d4), + CCU_PARENT_HW(pll1_d8_307p2), + CCU_PARENT_HW(pll1_d4_614p4), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(v2d_clk, v2d_parents, APMU_LCD_CLK_RES_CTRL1, 9= , 3, BIT(28), 12, 2, + BIT(8), 0); + +static const struct clk_parent_data dsiesc_parents[] =3D { + CCU_PARENT_HW(pll1_d48_51p2_ap), + CCU_PARENT_HW(pll1_d52_47p26), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d32_76p8), +}; +CCU_MUX_GATE_DEFINE(dsi_esc_clk, dsiesc_parents, APMU_LCD_CLK_RES_CTRL1, 0= , 2, BIT(2), 0); + +CCU_GATE_DEFINE(lcd_hclk, CCU_PARENT_HW(axi_clk), APMU_LCD_CLK_RES_CTRL1, = BIT(5), 0); + +static const struct clk_parent_data lcd_dsc_parents[] =3D { + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d10_245p76), + CCU_PARENT_HW(pll7_d5), + CCU_PARENT_HW(pll2_d7), + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d48_51p2_ap), + CCU_PARENT_HW(pll2_d8), +}; +CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_dsc_clk, lcd_dsc_parents, APMU_LCD_CL= K_RES_CTRL2, + APMU_LCD_CLK_RES_CTRL1, 25, 3, BIT(26), 29, 3, BIT(14), 0); + +static const struct clk_parent_data lcdpx_parents[] =3D { + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d10_245p76), + CCU_PARENT_HW(pll7_d5), + CCU_PARENT_HW(pll2_d7), + CCU_PARENT_HW(pll2_d4), + CCU_PARENT_HW(pll1_d48_51p2_ap), + CCU_PARENT_HW(pll2_d8), +}; +CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_pxclk, lcdpx_parents, APMU_LCD_CLK_RE= S_CTRL2, + APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(30), 21, 3, BIT(16), 0); + +static const struct clk_parent_data lcdmclk_parents[] =3D { + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d8_307p2), +}; +CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_mclk, lcdmclk_parents, APMU_LCD_CLK_R= ES_CTRL2, + APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29), 5, 3, BIT(0), 0); + +static const struct clk_parent_data ccic_4x_parents[] =3D { + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d3_819p2), + CCU_PARENT_HW(pll2_d2), + CCU_PARENT_HW(pll2_d3), + CCU_PARENT_HW(pll2_d4), + CCU_PARENT_HW(pll1_d2_1228p8), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(ccic_4x_clk, ccic_4x_parents, APMU_CCIC_CLK_RES= _CTRL, 18, 3, + BIT(15), 23, 2, BIT(4), 0); + +static const struct clk_parent_data ccic1phy_parents[] =3D { + CCU_PARENT_HW(pll1_d24_102p4), + CCU_PARENT_HW(pll1_d48_51p2_ap), +}; +CCU_MUX_GATE_DEFINE(ccic1phy_clk, ccic1phy_parents, APMU_CCIC_CLK_RES_CTRL= , 7, 1, BIT(5), 0); + + +static const struct clk_parent_data sc2hclk_parents[] =3D { + CCU_PARENT_HW(pll1_d8_307p2), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll2_d4), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(sc2_hclk, sc2hclk_parents, APMU_CCIC_CLK_RES_CT= RL, 10, 3, + BIT(16), 8, 2, BIT(3), 0); + +CCU_GATE_DEFINE(sdh_axi_aclk, CCU_PARENT_HW(axi_clk), APMU_SDH0_CLK_RES_CT= RL, BIT(3), 0); +static const struct clk_parent_data sdh01_parents[] =3D { + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll2_d8), + CCU_PARENT_HW(pll2_d5), + CCU_PARENT_NAME(reserved_clk), + CCU_PARENT_NAME(reserved_clk), + CCU_PARENT_HW(pll1_dx), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(sdh0_clk, sdh01_parents, APMU_SDH0_CLK_RES_CTRL= , 8, 3, + BIT(11), 5, 3, BIT(4), 0); +CCU_MUX_DIV_GATE_FC_DEFINE(sdh1_clk, sdh01_parents, APMU_SDH1_CLK_RES_CTRL= , 8, 3, + BIT(11), 5, 3, BIT(4), 0); +static const struct clk_parent_data sdh2_parents[] =3D { + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll2_d8), + CCU_PARENT_HW(pll1_d3_819p2), + CCU_PARENT_NAME(reserved_clk), + CCU_PARENT_NAME(reserved_clk), + CCU_PARENT_HW(pll1_dx), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL,= 8, 3, + BIT(11), 5, 3, BIT(4), 0); + +CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTR= L, BIT(0), 0); +CCU_GATE_DEFINE(usb3_porta_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_R= ES_CTRL, BIT(4), 0); +CCU_GATE_DEFINE(usb3_portb_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_R= ES_CTRL, BIT(8), 0); +CCU_GATE_DEFINE(usb3_portc_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_R= ES_CTRL, BIT(12), 0); +CCU_GATE_DEFINE(usb3_portd_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_R= ES_CTRL, BIT(16), 0); + +static const struct clk_parent_data qspi_parents[] =3D { + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll2_d8), + CCU_PARENT_HW(pll1_d8_307p2), + CCU_PARENT_HW(pll1_d10_245p76), + CCU_PARENT_NAME(reserved_clk), + CCU_PARENT_HW(pll1_dx), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_NAME(reserved_clk), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(qspi_clk, qspi_parents, APMU_QSPI_CLK_RES_CTRL,= 9, 3, + BIT(12), 6, 3, BIT(4), 0); +CCU_GATE_DEFINE(qspi_bus_clk, CCU_PARENT_HW(axi_clk), APMU_QSPI_CLK_RES_CT= RL, BIT(3), 0); + +CCU_GATE_DEFINE(dma_clk, CCU_PARENT_HW(axi_clk), APMU_DMA_CLK_RES_CTRL, BI= T(3), 0); + +static const struct clk_parent_data aes_wtm_parents[] =3D { + CCU_PARENT_HW(pll1_d12_204p8), + CCU_PARENT_HW(pll1_d24_102p4), +}; +CCU_MUX_GATE_DEFINE(aes_wtm_clk, aes_wtm_parents, APMU_AES_CLK_RES_CTRL, 6= , 1, BIT(5), 0); + +static const struct clk_parent_data vpu_parents[] =3D { + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d3_819p2), + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d2_1228p8), + CCU_PARENT_HW(pll2_d3), + CCU_PARENT_HW(pll2_d4), + CCU_PARENT_HW(pll2_d5), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(vpu_clk, vpu_parents, APMU_VPU_CLK_RES_CTRL, 13= , 3, + BIT(21), 10, 3, BIT(3), 0); + +CCU_GATE_DEFINE(dtc_clk, CCU_PARENT_HW(axi_clk), APMU_DTC_CLK_RES_CTRL, BI= T(3), 0); + +static const struct clk_parent_data gpu_parents[] =3D { + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d3_819p2), + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d2_1228p8), + CCU_PARENT_HW(pll2_d3), + CCU_PARENT_HW(pll2_d4), + CCU_PARENT_HW(pll2_d5), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(gpu_clk, gpu_parents, APMU_GPU_CLK_RES_CTRL, 12= , 3, + BIT(15), 18, 3, BIT(4), 0); + +CCU_GATE_DEFINE(mc_ahb_clk, CCU_PARENT_HW(axi_clk), APMU_PMUA_MC_CTRL, BIT= (1), 0); + +static const struct clk_parent_data top_parents[] =3D { + CCU_PARENT_HW(pll1_d8_307p2), + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll3_d4), + CCU_PARENT_HW(pll6_d5), + CCU_PARENT_HW(pll7_d4), + CCU_PARENT_HW(pll6_d4), + CCU_PARENT_HW(pll7_d3), + CCU_PARENT_HW(pll6_d3), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(top_dclk, top_parents, APMU_TOP_DCLK_CTRL, 5, 3, + BIT(8), 2, 3, BIT(1), 0); + +static const struct clk_parent_data ucie_parents[] =3D { + CCU_PARENT_HW(pll1_d8_307p2), + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll3_d4), + CCU_PARENT_HW(pll6_d5), + CCU_PARENT_HW(pll7_d4), + CCU_PARENT_HW(pll6_d4), +}; +CCU_MUX_GATE_DEFINE(ucie_clk, ucie_parents, APMU_UCIE_CTRL, 4, 3, BIT(0), = 0); +CCU_GATE_DEFINE(ucie_sbclk, CCU_PARENT_HW(axi_clk), APMU_UCIE_CTRL, BIT(8)= , 0); + +static const struct clk_parent_data rcpu_clk_parents[] =3D { + CCU_PARENT_HW(pll1_aud_245p7), + CCU_PARENT_HW(pll1_d8_307p2), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d6_409p6), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_C= TRL, + 4, 3, BIT(15), 7, 3, BIT(12), 0); + +static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] =3D { + CCU_PARENT_HW(pll1_d48_51p2_ap), + CCU_PARENT_HW(pll1_d52_47p26), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d32_76p8), +}; +CCU_MUX_GATE_DEFINE(dsi4ln2_dsi_esc_clk, dsi4ln2_dsi_esc_parents, APMU_LCD= _CLK_RES_CTRL3, + 0, 1, BIT(2), 0); + +static const struct clk_parent_data dsi4ln2_lcd_dsc_parents[] =3D { + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll7_d5), + CCU_PARENT_HW(pll6_d6), + CCU_PARENT_HW(pll2_d7), + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d48_51p2_ap), +}; +CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_dsc_clk, dsi4ln2_lcd_dsc_pare= nts, + APMU_LCD_CLK_RES_CTRL4, APMU_LCD_CLK_RES_CTRL3, + 25, 3, BIT(26), 29, 3, BIT(14), 0); + +static const struct clk_parent_data dsi4ln2_lcdpx_parents[] =3D { + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll7_d5), + CCU_PARENT_HW(pll6_d6), + CCU_PARENT_HW(pll2_d7), + CCU_PARENT_HW(pll2_d4), + CCU_PARENT_HW(pll1_d48_51p2_ap), + CCU_PARENT_HW(pll2_d8), +}; +CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_pxclk, dsi4ln2_lcdpx_parents,= APMU_LCD_CLK_RES_CTRL4, + APMU_LCD_CLK_RES_CTRL3, 17, 3, BIT(30), 21, 3, BIT(16), 0); + +static const struct clk_parent_data dsi4ln2_lcd_mclk_parents[] =3D { + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d8_307p2), +}; +CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_mclk, dsi4ln2_lcd_mclk_parent= s, APMU_LCD_CLK_RES_CTRL4, + APMU_LCD_CLK_RES_CTRL3, 1, 4, BIT(29), 5, 3, BIT(0), 0); + +static const struct clk_parent_data dpu_aclk_parents[] =3D { + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d8_307p2), + CCU_PARENT_HW(pll2_d4), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(dsi4ln2_dpu_aclk, dpu_aclk_parents, APMU_LCD_CL= K_RES_CTRL5, + 2, 3, BIT(30), 5, 3, BIT(1), 0); + +CCU_MUX_DIV_GATE_FC_DEFINE(dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CT= RL5, 17, 3, BIT(31), + 20, 3, BIT(16), 0); + +static const struct clk_parent_data ufs_aclk_parents[] =3D { + CCU_PARENT_HW(pll1_d6_409p6), + CCU_PARENT_HW(pll1_d5_491p52), + CCU_PARENT_HW(pll1_d4_614p4), + CCU_PARENT_HW(pll1_d8_307p2), + CCU_PARENT_HW(pll2_d4), +}; +CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CT= RL, 5, 3, BIT(8), + 2, 3, BIT(1), 0); + +static const struct clk_parent_data edp0_pclk_parents[] =3D { + CCU_PARENT_HW(lcd_pxclk), + CCU_PARENT_NAME(external_clk), +}; +CCU_MUX_GATE_DEFINE(edp0_pxclk, edp0_pclk_parents, APMU_LCD_EDP_CTRL, 2, 1= , BIT(1), 0); + +static const struct clk_parent_data edp1_pclk_parents[] =3D { + CCU_PARENT_HW(dsi4ln2_lcd_pxclk), + CCU_PARENT_NAME(external_clk), +}; +CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, = 1, BIT(17), 0); + +CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_A, BIT(2), 0); +CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_A, BIT(1), 0); +CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_B, BIT(2), 0); +CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_B, BIT(1), 0); +CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_C, BIT(2), 0); +CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_C, BIT(1), 0); +CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_D, BIT(2), 0); +CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_D, BIT(1), 0); +CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_= CTRL_E, BIT(2), 0); +CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_C= TRL_E, BIT(1), 0); + +static const struct clk_parent_data emac_1588_parents[] =3D { + CCU_PARENT_NAME(vctcxo_24m), + CCU_PARENT_HW(pll2_d24_125), +}; + +CCU_GATE_DEFINE(emac0_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC0_CLK_RES_= CTRL, BIT(0), 0); +CCU_GATE_FLAGS_DEFINE(emac0_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMA= C0_CLK_RES_CTRL, + BIT(14), true, 0); +CCU_MUX_DEFINE(emac0_1588_clk, emac_1588_parents, APMU_EMAC0_CLK_RES_CTRL,= 15, 1, 0); +CCU_GATE_DEFINE(emac0_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC= 0_CLK_RES_CTRL, + BIT(8), 0); +CCU_GATE_DEFINE(emac1_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC1_CLK_RES_= CTRL, BIT(0), 0); +CCU_GATE_FLAGS_DEFINE(emac1_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMA= C1_CLK_RES_CTRL, + BIT(14), true, 0); +CCU_MUX_DEFINE(emac1_1588_clk, emac_1588_parents, APMU_EMAC1_CLK_RES_CTRL,= 15, 1, 0); +CCU_GATE_DEFINE(emac1_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC= 1_CLK_RES_CTRL, + BIT(8), 0); +CCU_GATE_DEFINE(emac2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC2_CLK_RES_= CTRL, BIT(0), 0); +CCU_GATE_FLAGS_DEFINE(emac2_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMA= C2_CLK_RES_CTRL, + BIT(14), true, 0); +CCU_MUX_DEFINE(emac2_1588_clk, emac_1588_parents, APMU_EMAC2_CLK_RES_CTRL,= 15, 1, 0); +CCU_GATE_DEFINE(emac2_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC= 2_CLK_RES_CTRL, + BIT(8), 0); + +static const struct clk_parent_data espi_sclk_src_parents[] =3D { + CCU_PARENT_HW(pll2_20), + CCU_PARENT_HW(pll2_25), + CCU_PARENT_HW(pll2_33), + CCU_PARENT_HW(pll2_50), + CCU_PARENT_HW(pll2_66), +}; +CCU_MUX_DEFINE(espi_sclk_src, espi_sclk_src_parents, APMU_ESPI_CLK_RES_CTR= L, 4, 3, 0); + +static const struct clk_parent_data espi_sclk_parents[] =3D { + CCU_PARENT_NAME(external_clk), + CCU_PARENT_HW(espi_sclk_src), +}; +CCU_MUX_GATE_DEFINE(espi_sclk, espi_sclk_parents, APMU_ESPI_CLK_RES_CTRL, = 7, 1, BIT(3), 0); + +CCU_GATE_DEFINE(espi_mclk, CCU_PARENT_HW(axi_clk), APMU_ESPI_CLK_RES_CTRL,= BIT(1), 0); + +CCU_FACTOR_DEFINE(cam_src1_clk, CCU_PARENT_HW(pll1_d6_409p6), 15, 1); +CCU_FACTOR_DEFINE(cam_src2_clk, CCU_PARENT_HW(pll2_d5), 25, 1); +CCU_FACTOR_DEFINE(cam_src3_clk, CCU_PARENT_HW(pll2_d6), 20, 1); +CCU_FACTOR_DEFINE(cam_src4_clk, CCU_PARENT_HW(pll1_d6_409p6), 16, 1); + +static const struct clk_parent_data isim_vclk_parents[] =3D { + CCU_PARENT_HW(cam_src1_clk), + CCU_PARENT_HW(cam_src2_clk), + CCU_PARENT_HW(cam_src3_clk), + CCU_PARENT_HW(cam_src4_clk), +}; +CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out0, isim_vclk_parents, APMU_SNR_ISIM_V= CLK_CTRL, 3, 4, + 1, 2, BIT(0), 0); +CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out1, isim_vclk_parents, APMU_SNR_ISIM_V= CLK_CTRL, 11, 4, + 9, 2, BIT(8), 0); +CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out2, isim_vclk_parents, APMU_SNR_ISIM_V= CLK_CTRL, 19, 4, + 17, 2, BIT(16), 0); +CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_V= CLK_CTRL, 27, 4, + 25, 2, BIT(24), 0); +/* APMU clocks end */ + +/* DCIU clocks start */ +CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(= 0), 0); +CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_E= N, BIT(0), 0); +CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_= CLK, BIT(0), 0); +CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_= CLK, BIT(0), 0); +/* DCIU clocks end */ + +static struct clk_hw *k3_ccu_pll_hws[] =3D { + [CLK_PLL1] =3D &pll1.common.hw, + [CLK_PLL2] =3D &pll2.common.hw, + [CLK_PLL3] =3D &pll3.common.hw, + [CLK_PLL4] =3D &pll4.common.hw, + [CLK_PLL5] =3D &pll5.common.hw, + [CLK_PLL6] =3D &pll6.common.hw, + [CLK_PLL7] =3D &pll7.common.hw, + [CLK_PLL8] =3D &pll8.common.hw, + [CLK_PLL1_D2] =3D &pll1_d2.common.hw, + [CLK_PLL1_D3] =3D &pll1_d3.common.hw, + [CLK_PLL1_D4] =3D &pll1_d4.common.hw, + [CLK_PLL1_D5] =3D &pll1_d5.common.hw, + [CLK_PLL1_D6] =3D &pll1_d6.common.hw, + [CLK_PLL1_D7] =3D &pll1_d7.common.hw, + [CLK_PLL1_D8] =3D &pll1_d8.common.hw, + [CLK_PLL1_DX] =3D &pll1_dx.common.hw, + [CLK_PLL1_D64] =3D &pll1_d64_38p4.common.hw, + [CLK_PLL1_D10_AUD] =3D &pll1_aud_245p7.common.hw, + [CLK_PLL1_D100_AUD] =3D &pll1_aud_24p5.common.hw, + [CLK_PLL2_D1] =3D &pll2_d1.common.hw, + [CLK_PLL2_D2] =3D &pll2_d2.common.hw, + [CLK_PLL2_D3] =3D &pll2_d3.common.hw, + [CLK_PLL2_D4] =3D &pll2_d4.common.hw, + [CLK_PLL2_D5] =3D &pll2_d5.common.hw, + [CLK_PLL2_D6] =3D &pll2_d6.common.hw, + [CLK_PLL2_D7] =3D &pll2_d7.common.hw, + [CLK_PLL2_D8] =3D &pll2_d8.common.hw, + [CLK_PLL2_66] =3D &pll2_66.common.hw, + [CLK_PLL2_33] =3D &pll2_33.common.hw, + [CLK_PLL2_50] =3D &pll2_50.common.hw, + [CLK_PLL2_25] =3D &pll2_25.common.hw, + [CLK_PLL2_20] =3D &pll2_20.common.hw, + [CLK_PLL2_D24_125] =3D &pll2_d24_125.common.hw, + [CLK_PLL2_D120_25] =3D &pll2_d120_25.common.hw, + [CLK_PLL3_D1] =3D &pll3_d1.common.hw, + [CLK_PLL3_D2] =3D &pll3_d2.common.hw, + [CLK_PLL3_D3] =3D &pll3_d3.common.hw, + [CLK_PLL3_D4] =3D &pll3_d4.common.hw, + [CLK_PLL3_D5] =3D &pll3_d5.common.hw, + [CLK_PLL3_D6] =3D &pll3_d6.common.hw, + [CLK_PLL3_D7] =3D &pll3_d7.common.hw, + [CLK_PLL3_D8] =3D &pll3_d8.common.hw, + [CLK_PLL4_D1] =3D &pll4_d1.common.hw, + [CLK_PLL4_D2] =3D &pll4_d2.common.hw, + [CLK_PLL4_D3] =3D &pll4_d3.common.hw, + [CLK_PLL4_D4] =3D &pll4_d4.common.hw, + [CLK_PLL4_D5] =3D &pll4_d5.common.hw, + [CLK_PLL4_D6] =3D &pll4_d6.common.hw, + [CLK_PLL4_D7] =3D &pll4_d7.common.hw, + [CLK_PLL4_D8] =3D &pll4_d8.common.hw, + [CLK_PLL5_D1] =3D &pll5_d1.common.hw, + [CLK_PLL5_D2] =3D &pll5_d2.common.hw, + [CLK_PLL5_D3] =3D &pll5_d3.common.hw, + [CLK_PLL5_D4] =3D &pll5_d4.common.hw, + [CLK_PLL5_D5] =3D &pll5_d5.common.hw, + [CLK_PLL5_D6] =3D &pll5_d6.common.hw, + [CLK_PLL5_D7] =3D &pll5_d7.common.hw, + [CLK_PLL5_D8] =3D &pll5_d8.common.hw, + [CLK_PLL6_D1] =3D &pll6_d1.common.hw, + [CLK_PLL6_D2] =3D &pll6_d2.common.hw, + [CLK_PLL6_D3] =3D &pll6_d3.common.hw, + [CLK_PLL6_D4] =3D &pll6_d4.common.hw, + [CLK_PLL6_D5] =3D &pll6_d5.common.hw, + [CLK_PLL6_D6] =3D &pll6_d6.common.hw, + [CLK_PLL6_D7] =3D &pll6_d7.common.hw, + [CLK_PLL6_D8] =3D &pll6_d8.common.hw, + [CLK_PLL6_80] =3D &pll6_80.common.hw, + [CLK_PLL6_40] =3D &pll6_40.common.hw, + [CLK_PLL6_20] =3D &pll6_20.common.hw, + [CLK_PLL7_D1] =3D &pll7_d1.common.hw, + [CLK_PLL7_D2] =3D &pll7_d2.common.hw, + [CLK_PLL7_D3] =3D &pll7_d3.common.hw, + [CLK_PLL7_D4] =3D &pll7_d4.common.hw, + [CLK_PLL7_D5] =3D &pll7_d5.common.hw, + [CLK_PLL7_D6] =3D &pll7_d6.common.hw, + [CLK_PLL7_D7] =3D &pll7_d7.common.hw, + [CLK_PLL7_D8] =3D &pll7_d8.common.hw, + [CLK_PLL8_D1] =3D &pll8_d1.common.hw, + [CLK_PLL8_D2] =3D &pll8_d2.common.hw, + [CLK_PLL8_D3] =3D &pll8_d3.common.hw, + [CLK_PLL8_D4] =3D &pll8_d4.common.hw, + [CLK_PLL8_D5] =3D &pll8_d5.common.hw, + [CLK_PLL8_D6] =3D &pll8_d6.common.hw, + [CLK_PLL8_D7] =3D &pll8_d7.common.hw, + [CLK_PLL8_D8] =3D &pll8_d8.common.hw, +}; + +static const struct spacemit_ccu_data k3_ccu_pll_data =3D { + /* The APBS CCU implements PLLs, but no resets */ + .hws =3D k3_ccu_pll_hws, + .num =3D ARRAY_SIZE(k3_ccu_pll_hws), +}; + +static struct clk_hw *k3_ccu_mpmu_hws[] =3D { + [CLK_MPMU_PLL1_307P2] =3D &pll1_d8_307p2.common.hw, + [CLK_MPMU_PLL1_76P8] =3D &pll1_d32_76p8.common.hw, + [CLK_MPMU_PLL1_61P44] =3D &pll1_d40_61p44.common.hw, + [CLK_MPMU_PLL1_153P6] =3D &pll1_d16_153p6.common.hw, + [CLK_MPMU_PLL1_102P4] =3D &pll1_d24_102p4.common.hw, + [CLK_MPMU_PLL1_51P2] =3D &pll1_d48_51p2.common.hw, + [CLK_MPMU_PLL1_51P2_AP] =3D &pll1_d48_51p2_ap.common.hw, + [CLK_MPMU_PLL1_57P6] =3D &pll1_m3d128_57p6.common.hw, + [CLK_MPMU_PLL1_25P6] =3D &pll1_d96_25p6.common.hw, + [CLK_MPMU_PLL1_12P8] =3D &pll1_d192_12p8.common.hw, + [CLK_MPMU_PLL1_12P8_WDT] =3D &pll1_d192_12p8_wdt.common.hw, + [CLK_MPMU_PLL1_6P4] =3D &pll1_d384_6p4.common.hw, + [CLK_MPMU_PLL1_3P2] =3D &pll1_d768_3p2.common.hw, + [CLK_MPMU_PLL1_1P6] =3D &pll1_d1536_1p6.common.hw, + [CLK_MPMU_PLL1_0P8] =3D &pll1_d3072_0p8.common.hw, + [CLK_MPMU_PLL1_409P6] =3D &pll1_d6_409p6.common.hw, + [CLK_MPMU_PLL1_204P8] =3D &pll1_d12_204p8.common.hw, + [CLK_MPMU_PLL1_491] =3D &pll1_d5_491p52.common.hw, + [CLK_MPMU_PLL1_245P76] =3D &pll1_d10_245p76.common.hw, + [CLK_MPMU_PLL1_614] =3D &pll1_d4_614p4.common.hw, + [CLK_MPMU_PLL1_47P26] =3D &pll1_d52_47p26.common.hw, + [CLK_MPMU_PLL1_31P5] =3D &pll1_d78_31p5.common.hw, + [CLK_MPMU_PLL1_819] =3D &pll1_d3_819p2.common.hw, + [CLK_MPMU_PLL1_1228] =3D &pll1_d2_1228p8.common.hw, + [CLK_MPMU_APB] =3D &apb_clk.common.hw, + [CLK_MPMU_SLOW_UART] =3D &slow_uart.common.hw, + [CLK_MPMU_SLOW_UART1] =3D &slow_uart1_14p74.common.hw, + [CLK_MPMU_SLOW_UART2] =3D &slow_uart2_48.common.hw, + [CLK_MPMU_WDT] =3D &wdt_clk.common.hw, + [CLK_MPMU_WDT_BUS] =3D &wdt_bus_clk.common.hw, + [CLK_MPMU_RIPC] =3D &r_ipc_clk.common.hw, + [CLK_MPMU_I2S_153P6] =3D &i2s_153p6.common.hw, + [CLK_MPMU_I2S_153P6_BASE] =3D &i2s_153p6_base.common.hw, + [CLK_MPMU_I2S_SYSCLK_SRC] =3D &i2s_sysclk_src.common.hw, + [CLK_MPMU_I2S1_SYSCLK] =3D &i2s1_sysclk.common.hw, + [CLK_MPMU_I2S_BCLK] =3D &i2s_bclk.common.hw, + [CLK_MPMU_I2S0_SYSCLK_SEL] =3D &i2s0_sysclk_sel.common.hw, + [CLK_MPMU_I2S2_SYSCLK_SEL] =3D &i2s2_sysclk_sel.common.hw, + [CLK_MPMU_I2S3_SYSCLK_SEL] =3D &i2s3_sysclk_sel.common.hw, + [CLK_MPMU_I2S4_SYSCLK_SEL] =3D &i2s4_sysclk_sel.common.hw, + [CLK_MPMU_I2S5_SYSCLK_SEL] =3D &i2s5_sysclk_sel.common.hw, + [CLK_MPMU_I2S0_SYSCLK_DIV] =3D &i2s0_sysclk_div.common.hw, + [CLK_MPMU_I2S2_SYSCLK_DIV] =3D &i2s2_sysclk_div.common.hw, + [CLK_MPMU_I2S3_SYSCLK_DIV] =3D &i2s3_sysclk_div.common.hw, + [CLK_MPMU_I2S4_SYSCLK_DIV] =3D &i2s4_sysclk_div.common.hw, + [CLK_MPMU_I2S5_SYSCLK_DIV] =3D &i2s5_sysclk_div.common.hw, + [CLK_MPMU_I2S0_SYSCLK] =3D &i2s0_sysclk.common.hw, + [CLK_MPMU_I2S2_SYSCLK] =3D &i2s2_sysclk.common.hw, + [CLK_MPMU_I2S3_SYSCLK] =3D &i2s3_sysclk.common.hw, + [CLK_MPMU_I2S4_SYSCLK] =3D &i2s4_sysclk.common.hw, + [CLK_MPMU_I2S5_SYSCLK] =3D &i2s5_sysclk.common.hw, +}; + +static const struct spacemit_ccu_data k3_ccu_mpmu_data =3D { + .reset_name =3D "mpmu-reset", + .hws =3D k3_ccu_mpmu_hws, + .num =3D ARRAY_SIZE(k3_ccu_mpmu_hws), +}; + +static struct clk_hw *k3_ccu_apbc_hws[] =3D { + [CLK_APBC_UART0] =3D &uart0_clk.common.hw, + [CLK_APBC_UART2] =3D &uart2_clk.common.hw, + [CLK_APBC_UART3] =3D &uart3_clk.common.hw, + [CLK_APBC_UART4] =3D &uart4_clk.common.hw, + [CLK_APBC_UART5] =3D &uart5_clk.common.hw, + [CLK_APBC_UART6] =3D &uart6_clk.common.hw, + [CLK_APBC_UART7] =3D &uart7_clk.common.hw, + [CLK_APBC_UART8] =3D &uart8_clk.common.hw, + [CLK_APBC_UART9] =3D &uart9_clk.common.hw, + [CLK_APBC_UART10] =3D &uart10_clk.common.hw, + [CLK_APBC_UART0_BUS] =3D &uart0_bus_clk.common.hw, + [CLK_APBC_UART2_BUS] =3D &uart2_bus_clk.common.hw, + [CLK_APBC_UART3_BUS] =3D &uart3_bus_clk.common.hw, + [CLK_APBC_UART4_BUS] =3D &uart4_bus_clk.common.hw, + [CLK_APBC_UART5_BUS] =3D &uart5_bus_clk.common.hw, + [CLK_APBC_UART6_BUS] =3D &uart6_bus_clk.common.hw, + [CLK_APBC_UART7_BUS] =3D &uart7_bus_clk.common.hw, + [CLK_APBC_UART8_BUS] =3D &uart8_bus_clk.common.hw, + [CLK_APBC_UART9_BUS] =3D &uart9_bus_clk.common.hw, + [CLK_APBC_UART10_BUS] =3D &uart10_bus_clk.common.hw, + [CLK_APBC_GPIO] =3D &gpio_clk.common.hw, + [CLK_APBC_GPIO_BUS] =3D &gpio_bus_clk.common.hw, + [CLK_APBC_PWM0] =3D &pwm0_clk.common.hw, + [CLK_APBC_PWM1] =3D &pwm1_clk.common.hw, + [CLK_APBC_PWM2] =3D &pwm2_clk.common.hw, + [CLK_APBC_PWM3] =3D &pwm3_clk.common.hw, + [CLK_APBC_PWM4] =3D &pwm4_clk.common.hw, + [CLK_APBC_PWM5] =3D &pwm5_clk.common.hw, + [CLK_APBC_PWM6] =3D &pwm6_clk.common.hw, + [CLK_APBC_PWM7] =3D &pwm7_clk.common.hw, + [CLK_APBC_PWM8] =3D &pwm8_clk.common.hw, + [CLK_APBC_PWM9] =3D &pwm9_clk.common.hw, + [CLK_APBC_PWM10] =3D &pwm10_clk.common.hw, + [CLK_APBC_PWM11] =3D &pwm11_clk.common.hw, + [CLK_APBC_PWM12] =3D &pwm12_clk.common.hw, + [CLK_APBC_PWM13] =3D &pwm13_clk.common.hw, + [CLK_APBC_PWM14] =3D &pwm14_clk.common.hw, + [CLK_APBC_PWM15] =3D &pwm15_clk.common.hw, + [CLK_APBC_PWM16] =3D &pwm16_clk.common.hw, + [CLK_APBC_PWM17] =3D &pwm17_clk.common.hw, + [CLK_APBC_PWM18] =3D &pwm18_clk.common.hw, + [CLK_APBC_PWM19] =3D &pwm19_clk.common.hw, + [CLK_APBC_PWM0_BUS] =3D &pwm0_bus_clk.common.hw, + [CLK_APBC_PWM1_BUS] =3D &pwm1_bus_clk.common.hw, + [CLK_APBC_PWM2_BUS] =3D &pwm2_bus_clk.common.hw, + [CLK_APBC_PWM3_BUS] =3D &pwm3_bus_clk.common.hw, + [CLK_APBC_PWM4_BUS] =3D &pwm4_bus_clk.common.hw, + [CLK_APBC_PWM5_BUS] =3D &pwm5_bus_clk.common.hw, + [CLK_APBC_PWM6_BUS] =3D &pwm6_bus_clk.common.hw, + [CLK_APBC_PWM7_BUS] =3D &pwm7_bus_clk.common.hw, + [CLK_APBC_PWM8_BUS] =3D &pwm8_bus_clk.common.hw, + [CLK_APBC_PWM9_BUS] =3D &pwm9_bus_clk.common.hw, + [CLK_APBC_PWM10_BUS] =3D &pwm10_bus_clk.common.hw, + [CLK_APBC_PWM11_BUS] =3D &pwm11_bus_clk.common.hw, + [CLK_APBC_PWM12_BUS] =3D &pwm12_bus_clk.common.hw, + [CLK_APBC_PWM13_BUS] =3D &pwm13_bus_clk.common.hw, + [CLK_APBC_PWM14_BUS] =3D &pwm14_bus_clk.common.hw, + [CLK_APBC_PWM15_BUS] =3D &pwm15_bus_clk.common.hw, + [CLK_APBC_PWM16_BUS] =3D &pwm16_bus_clk.common.hw, + [CLK_APBC_PWM17_BUS] =3D &pwm17_bus_clk.common.hw, + [CLK_APBC_PWM18_BUS] =3D &pwm18_bus_clk.common.hw, + [CLK_APBC_PWM19_BUS] =3D &pwm19_bus_clk.common.hw, + [CLK_APBC_SPI0_I2S_BCLK] =3D &spi0_i2s_bclk.common.hw, + [CLK_APBC_SPI1_I2S_BCLK] =3D &spi1_i2s_bclk.common.hw, + [CLK_APBC_SPI3_I2S_BCLK] =3D &spi3_i2s_bclk.common.hw, + [CLK_APBC_SPI0] =3D &spi0_clk.common.hw, + [CLK_APBC_SPI1] =3D &spi1_clk.common.hw, + [CLK_APBC_SPI3] =3D &spi3_clk.common.hw, + [CLK_APBC_SPI0_BUS] =3D &spi0_bus_clk.common.hw, + [CLK_APBC_SPI1_BUS] =3D &spi1_bus_clk.common.hw, + [CLK_APBC_SPI3_BUS] =3D &spi3_bus_clk.common.hw, + [CLK_APBC_RTC] =3D &rtc_clk.common.hw, + [CLK_APBC_RTC_BUS] =3D &rtc_bus_clk.common.hw, + [CLK_APBC_TWSI0] =3D &twsi0_clk.common.hw, + [CLK_APBC_TWSI1] =3D &twsi1_clk.common.hw, + [CLK_APBC_TWSI2] =3D &twsi2_clk.common.hw, + [CLK_APBC_TWSI4] =3D &twsi4_clk.common.hw, + [CLK_APBC_TWSI5] =3D &twsi5_clk.common.hw, + [CLK_APBC_TWSI6] =3D &twsi6_clk.common.hw, + [CLK_APBC_TWSI8] =3D &twsi8_clk.common.hw, + [CLK_APBC_TWSI0_BUS] =3D &twsi0_bus_clk.common.hw, + [CLK_APBC_TWSI1_BUS] =3D &twsi1_bus_clk.common.hw, + [CLK_APBC_TWSI2_BUS] =3D &twsi2_bus_clk.common.hw, + [CLK_APBC_TWSI4_BUS] =3D &twsi4_bus_clk.common.hw, + [CLK_APBC_TWSI5_BUS] =3D &twsi5_bus_clk.common.hw, + [CLK_APBC_TWSI6_BUS] =3D &twsi6_bus_clk.common.hw, + [CLK_APBC_TWSI8_BUS] =3D &twsi8_bus_clk.common.hw, + [CLK_APBC_TIMERS0] =3D &timers0_clk.common.hw, + [CLK_APBC_TIMERS1] =3D &timers1_clk.common.hw, + [CLK_APBC_TIMERS2] =3D &timers2_clk.common.hw, + [CLK_APBC_TIMERS3] =3D &timers3_clk.common.hw, + [CLK_APBC_TIMERS4] =3D &timers4_clk.common.hw, + [CLK_APBC_TIMERS5] =3D &timers5_clk.common.hw, + [CLK_APBC_TIMERS6] =3D &timers6_clk.common.hw, + [CLK_APBC_TIMERS7] =3D &timers7_clk.common.hw, + [CLK_APBC_TIMERS0_BUS] =3D &timers0_bus_clk.common.hw, + [CLK_APBC_TIMERS1_BUS] =3D &timers1_bus_clk.common.hw, + [CLK_APBC_TIMERS2_BUS] =3D &timers2_bus_clk.common.hw, + [CLK_APBC_TIMERS3_BUS] =3D &timers3_bus_clk.common.hw, + [CLK_APBC_TIMERS4_BUS] =3D &timers4_bus_clk.common.hw, + [CLK_APBC_TIMERS5_BUS] =3D &timers5_bus_clk.common.hw, + [CLK_APBC_TIMERS6_BUS] =3D &timers6_bus_clk.common.hw, + [CLK_APBC_TIMERS7_BUS] =3D &timers7_bus_clk.common.hw, + [CLK_APBC_AIB] =3D &aib_clk.common.hw, + [CLK_APBC_AIB_BUS] =3D &aib_bus_clk.common.hw, + [CLK_APBC_ONEWIRE] =3D &onewire_clk.common.hw, + [CLK_APBC_ONEWIRE_BUS] =3D &onewire_bus_clk.common.hw, + [CLK_APBC_I2S0_BCLK] =3D &i2s0_i2s_bclk.common.hw, + [CLK_APBC_I2S1_BCLK] =3D &i2s1_i2s_bclk.common.hw, + [CLK_APBC_I2S2_BCLK] =3D &i2s2_i2s_bclk.common.hw, + [CLK_APBC_I2S3_BCLK] =3D &i2s3_i2s_bclk.common.hw, + [CLK_APBC_I2S4_BCLK] =3D &i2s4_i2s_bclk.common.hw, + [CLK_APBC_I2S5_BCLK] =3D &i2s5_i2s_bclk.common.hw, + [CLK_APBC_I2S0] =3D &i2s0_clk.common.hw, + [CLK_APBC_I2S1] =3D &i2s1_clk.common.hw, + [CLK_APBC_I2S2] =3D &i2s2_clk.common.hw, + [CLK_APBC_I2S3] =3D &i2s3_clk.common.hw, + [CLK_APBC_I2S4] =3D &i2s4_clk.common.hw, + [CLK_APBC_I2S5] =3D &i2s5_clk.common.hw, + [CLK_APBC_I2S0_BUS] =3D &i2s0_bus_clk.common.hw, + [CLK_APBC_I2S1_BUS] =3D &i2s1_bus_clk.common.hw, + [CLK_APBC_I2S2_BUS] =3D &i2s2_bus_clk.common.hw, + [CLK_APBC_I2S3_BUS] =3D &i2s3_bus_clk.common.hw, + [CLK_APBC_I2S4_BUS] =3D &i2s4_bus_clk.common.hw, + [CLK_APBC_I2S5_BUS] =3D &i2s5_bus_clk.common.hw, + [CLK_APBC_DRO] =3D &dro_clk.common.hw, + [CLK_APBC_IR0] =3D &ir0_clk.common.hw, + [CLK_APBC_IR1] =3D &ir1_clk.common.hw, + [CLK_APBC_TSEN] =3D &tsen_clk.common.hw, + [CLK_APBC_TSEN_BUS] =3D &tsen_bus_clk.common.hw, + [CLK_APBC_IPC_AP2RCPU] =3D &ipc_ap2rcpu_clk.common.hw, + [CLK_APBC_IPC_AP2RCPU_BUS] =3D &ipc_ap2rcpu_bus_clk.common.hw, + [CLK_APBC_CAN0] =3D &can0_clk.common.hw, + [CLK_APBC_CAN1] =3D &can1_clk.common.hw, + [CLK_APBC_CAN2] =3D &can2_clk.common.hw, + [CLK_APBC_CAN3] =3D &can3_clk.common.hw, + [CLK_APBC_CAN4] =3D &can4_clk.common.hw, + [CLK_APBC_CAN0_BUS] =3D &can0_bus_clk.common.hw, + [CLK_APBC_CAN1_BUS] =3D &can1_bus_clk.common.hw, + [CLK_APBC_CAN2_BUS] =3D &can2_bus_clk.common.hw, + [CLK_APBC_CAN3_BUS] =3D &can3_bus_clk.common.hw, + [CLK_APBC_CAN4_BUS] =3D &can4_bus_clk.common.hw, +}; + +static const struct spacemit_ccu_data k3_ccu_apbc_data =3D { + .reset_name =3D "apbc-reset", + .hws =3D k3_ccu_apbc_hws, + .num =3D ARRAY_SIZE(k3_ccu_apbc_hws), +}; + +static struct clk_hw *k3_ccu_apmu_hws[] =3D { + [CLK_APMU_AXICLK] =3D &axi_clk.common.hw, + [CLK_APMU_CCI550] =3D &cci550_clk.common.hw, + [CLK_APMU_CPU_C0_CORE] =3D &cpu_c0_core_clk.common.hw, + [CLK_APMU_CPU_C1_CORE] =3D &cpu_c1_core_clk.common.hw, + [CLK_APMU_CPU_C2_CORE] =3D &cpu_c2_core_clk.common.hw, + [CLK_APMU_CPU_C3_CORE] =3D &cpu_c3_core_clk.common.hw, + [CLK_APMU_CCIC2PHY] =3D &ccic2phy_clk.common.hw, + [CLK_APMU_CCIC3PHY] =3D &ccic3phy_clk.common.hw, + [CLK_APMU_CSI] =3D &csi_clk.common.hw, + [CLK_APMU_ISP_BUS] =3D &isp_bus_clk.common.hw, + [CLK_APMU_D1P_1228P8] =3D &d1p_1228p8.common.hw, + [CLK_APMU_D1P_819P2] =3D &d1p_819p2.common.hw, + [CLK_APMU_D1P_614P4] =3D &d1p_614p4.common.hw, + [CLK_APMU_D1P_491P52] =3D &d1p_491p52.common.hw, + [CLK_APMU_D1P_409P6] =3D &d1p_409p6.common.hw, + [CLK_APMU_D1P_307P2] =3D &d1p_307p2.common.hw, + [CLK_APMU_D1P_245P76] =3D &d1p_245p76.common.hw, + [CLK_APMU_V2D] =3D &v2d_clk.common.hw, + [CLK_APMU_DSI_ESC] =3D &dsi_esc_clk.common.hw, + [CLK_APMU_LCD_HCLK] =3D &lcd_hclk.common.hw, + [CLK_APMU_LCD_DSC] =3D &lcd_dsc_clk.common.hw, + [CLK_APMU_LCD_PXCLK] =3D &lcd_pxclk.common.hw, + [CLK_APMU_LCD_MCLK] =3D &lcd_mclk.common.hw, + [CLK_APMU_CCIC_4X] =3D &ccic_4x_clk.common.hw, + [CLK_APMU_CCIC1PHY] =3D &ccic1phy_clk.common.hw, + [CLK_APMU_SC2_HCLK] =3D &sc2_hclk.common.hw, + [CLK_APMU_SDH_AXI] =3D &sdh_axi_aclk.common.hw, + [CLK_APMU_SDH0] =3D &sdh0_clk.common.hw, + [CLK_APMU_SDH1] =3D &sdh1_clk.common.hw, + [CLK_APMU_SDH2] =3D &sdh2_clk.common.hw, + [CLK_APMU_USB2_BUS] =3D &usb2_bus_clk.common.hw, + [CLK_APMU_USB3_PORTA_BUS] =3D &usb3_porta_bus_clk.common.hw, + [CLK_APMU_USB3_PORTB_BUS] =3D &usb3_portb_bus_clk.common.hw, + [CLK_APMU_USB3_PORTC_BUS] =3D &usb3_portc_bus_clk.common.hw, + [CLK_APMU_USB3_PORTD_BUS] =3D &usb3_portd_bus_clk.common.hw, + [CLK_APMU_QSPI] =3D &qspi_clk.common.hw, + [CLK_APMU_QSPI_BUS] =3D &qspi_bus_clk.common.hw, + [CLK_APMU_DMA] =3D &dma_clk.common.hw, + [CLK_APMU_AES_WTM] =3D &aes_wtm_clk.common.hw, + [CLK_APMU_VPU] =3D &vpu_clk.common.hw, + [CLK_APMU_DTC] =3D &dtc_clk.common.hw, + [CLK_APMU_GPU] =3D &gpu_clk.common.hw, + [CLK_APMU_MC_AHB] =3D &mc_ahb_clk.common.hw, + [CLK_APMU_TOP_DCLK] =3D &top_dclk.common.hw, + [CLK_APMU_UCIE] =3D &ucie_clk.common.hw, + [CLK_APMU_UCIE_SBCLK] =3D &ucie_sbclk.common.hw, + [CLK_APMU_RCPU] =3D &rcpu_clk.common.hw, + [CLK_APMU_DSI4LN2_DSI_ESC] =3D &dsi4ln2_dsi_esc_clk.common.hw, + [CLK_APMU_DSI4LN2_LCD_DSC] =3D &dsi4ln2_lcd_dsc_clk.common.hw, + [CLK_APMU_DSI4LN2_LCD_PXCLK] =3D &dsi4ln2_lcd_pxclk.common.hw, + [CLK_APMU_DSI4LN2_LCD_MCLK] =3D &dsi4ln2_lcd_mclk.common.hw, + [CLK_APMU_DSI4LN2_DPU_ACLK] =3D &dsi4ln2_dpu_aclk.common.hw, + [CLK_APMU_DPU_ACLK] =3D &dpu_aclk.common.hw, + [CLK_APMU_UFS_ACLK] =3D &ufs_aclk.common.hw, + [CLK_APMU_EDP0_PXCLK] =3D &edp0_pxclk.common.hw, + [CLK_APMU_EDP1_PXCLK] =3D &edp1_pxclk.common.hw, + [CLK_APMU_PCIE_PORTA_MSTE] =3D &pciea_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTA_SLV] =3D &pciea_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTB_MSTE] =3D &pcieb_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTB_SLV] =3D &pcieb_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTC_MSTE] =3D &pciec_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTC_SLV] =3D &pciec_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTD_MSTE] =3D &pcied_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTD_SLV] =3D &pcied_slv_clk.common.hw, + [CLK_APMU_PCIE_PORTE_MSTE] =3D &pciee_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTE_SLV] =3D &pciee_slv_clk.common.hw, + [CLK_APMU_EMAC0_BUS] =3D &emac0_bus_clk.common.hw, + [CLK_APMU_EMAC0_REF] =3D &emac0_ref_clk.common.hw, + [CLK_APMU_EMAC0_1588] =3D &emac0_1588_clk.common.hw, + [CLK_APMU_EMAC0_RGMII_TX] =3D &emac0_rgmii_tx_clk.common.hw, + [CLK_APMU_EMAC1_BUS] =3D &emac1_bus_clk.common.hw, + [CLK_APMU_EMAC1_REF] =3D &emac1_ref_clk.common.hw, + [CLK_APMU_EMAC1_1588] =3D &emac1_1588_clk.common.hw, + [CLK_APMU_EMAC1_RGMII_TX] =3D &emac1_rgmii_tx_clk.common.hw, + [CLK_APMU_EMAC2_BUS] =3D &emac2_bus_clk.common.hw, + [CLK_APMU_EMAC2_REF] =3D &emac2_ref_clk.common.hw, + [CLK_APMU_EMAC2_1588] =3D &emac2_1588_clk.common.hw, + [CLK_APMU_EMAC2_RGMII_TX] =3D &emac2_rgmii_tx_clk.common.hw, + [CLK_APMU_ESPI_SCLK_SRC] =3D &espi_sclk_src.common.hw, + [CLK_APMU_ESPI_SCLK] =3D &espi_sclk.common.hw, + [CLK_APMU_ESPI_MCLK] =3D &espi_mclk.common.hw, + [CLK_APMU_CAM_SRC1] =3D &cam_src1_clk.common.hw, + [CLK_APMU_CAM_SRC2] =3D &cam_src2_clk.common.hw, + [CLK_APMU_CAM_SRC3] =3D &cam_src3_clk.common.hw, + [CLK_APMU_CAM_SRC4] =3D &cam_src4_clk.common.hw, + [CLK_APMU_ISIM_VCLK0] =3D &isim_vclk_out0.common.hw, + [CLK_APMU_ISIM_VCLK1] =3D &isim_vclk_out1.common.hw, + [CLK_APMU_ISIM_VCLK2] =3D &isim_vclk_out2.common.hw, + [CLK_APMU_ISIM_VCLK3] =3D &isim_vclk_out3.common.hw, +}; + +static const struct spacemit_ccu_data k3_ccu_apmu_data =3D { + .reset_name =3D "apmu-reset", + .hws =3D k3_ccu_apmu_hws, + .num =3D ARRAY_SIZE(k3_ccu_apmu_hws), +}; + +static struct clk_hw *k3_ccu_dciu_hws[] =3D { + [CLK_DCIU_HDMA] =3D &hdma_clk.common.hw, + [CLK_DCIU_DMA350] =3D &dma350_clk.common.hw, + [CLK_DCIU_C2_TCM_PIPE] =3D &c2_tcm_pipe_clk.common.hw, + [CLK_DCIU_C3_TCM_PIPE] =3D &c3_tcm_pipe_clk.common.hw, +}; + +static const struct spacemit_ccu_data k3_ccu_dciu_data =3D { + .reset_name =3D "dciu-reset", + .hws =3D k3_ccu_dciu_hws, + .num =3D ARRAY_SIZE(k3_ccu_dciu_hws), +}; + +static int spacemit_ccu_register(struct device *dev, + struct regmap *regmap, + struct regmap *lock_regmap, + const struct spacemit_ccu_data *data) +{ + struct clk_hw_onecell_data *clk_data; + int i, ret; + + /* Nothing to do if the CCU does not implement any clocks */ + if (!data->hws) + return 0; + + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, data->num), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + for (i =3D 0; i < data->num; i++) { + struct clk_hw *hw =3D data->hws[i]; + struct ccu_common *common; + const char *name; + + if (!hw) { + clk_data->hws[i] =3D ERR_PTR(-ENOENT); + continue; + } + + name =3D hw->init->name; + + common =3D hw_to_ccu_common(hw); + common->regmap =3D regmap; + common->lock_regmap =3D lock_regmap; + + ret =3D devm_clk_hw_register(dev, hw); + if (ret) { + dev_err(dev, "Cannot register clock %d - %s\n", + i, name); + return ret; + } + + clk_data->hws[i] =3D hw; + } + + clk_data->num =3D data->num; + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret) + dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); + + return ret; +} + +static void spacemit_cadev_release(struct device *dev) +{ + struct auxiliary_device *adev =3D to_auxiliary_dev(dev); + + kfree(to_spacemit_ccu_adev(adev)); +} + +static void spacemit_adev_unregister(void *data) +{ + struct auxiliary_device *adev =3D data; + + auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); +} + +static int spacemit_ccu_reset_register(struct device *dev, + struct regmap *regmap, + const char *reset_name) +{ + struct spacemit_ccu_adev *cadev; + struct auxiliary_device *adev; + static u32 next_id; + int ret; + + /* Nothing to do if the CCU does not implement a reset controller */ + if (!reset_name) + return 0; + + cadev =3D devm_kzalloc(dev, sizeof(*cadev), GFP_KERNEL); + if (!cadev) + return -ENOMEM; + cadev->regmap =3D regmap; + + adev =3D &cadev->adev; + adev->name =3D reset_name; + adev->dev.parent =3D dev; + adev->dev.release =3D spacemit_cadev_release; + adev->dev.of_node =3D dev->of_node; + adev->id =3D next_id++; + + ret =3D auxiliary_device_init(adev); + if (ret) + return ret; + + ret =3D auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; + } + + return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); +} + +static int k3_ccu_probe(struct platform_device *pdev) +{ + struct regmap *base_regmap, *lock_regmap =3D NULL; + const struct spacemit_ccu_data *data; + struct device *dev =3D &pdev->dev; + int ret; + + base_regmap =3D device_node_to_regmap(dev->of_node); + if (IS_ERR(base_regmap)) + return dev_err_probe(dev, PTR_ERR(base_regmap), + "failed to get regmap\n"); + /* + * The lock status of PLLs locate in MPMU region, while PLLs themselves + * are in APBS region. Reference to MPMU syscon is required to check PLL + * status. + */ + if (of_device_is_compatible(dev->of_node, "spacemit,k3-pll")) { + struct device_node *mpmu =3D of_parse_phandle(dev->of_node, "spacemit,mp= mu", 0); + + if (!mpmu) + return dev_err_probe(dev, -ENODEV, + "Cannot parse MPMU region\n"); + + lock_regmap =3D device_node_to_regmap(mpmu); + of_node_put(mpmu); + + if (IS_ERR(lock_regmap)) + return dev_err_probe(dev, PTR_ERR(lock_regmap), + "failed to get lock regmap\n"); + } + + data =3D of_device_get_match_data(dev); + + ret =3D spacemit_ccu_register(dev, base_regmap, lock_regmap, data); + if (ret) + return dev_err_probe(dev, ret, "failed to register clocks\n"); + + ret =3D spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); + if (ret) + return dev_err_probe(dev, ret, "failed to register resets\n"); + + return 0; +} + +static const struct of_device_id of_k3_ccu_match[] =3D { + { + .compatible =3D "spacemit,k3-pll", + .data =3D &k3_ccu_pll_data, + }, + { + .compatible =3D "spacemit,k3-syscon-mpmu", + .data =3D &k3_ccu_mpmu_data, + }, + { + .compatible =3D "spacemit,k3-syscon-apbc", + .data =3D &k3_ccu_apbc_data, + }, + { + .compatible =3D "spacemit,k3-syscon-apmu", + .data =3D &k3_ccu_apmu_data, + }, + { + .compatible =3D "spacemit,k3-syscon-dciu", + .data =3D &k3_ccu_dciu_data, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_k3_ccu_match); + +static struct platform_driver k3_ccu_driver =3D { + .driver =3D { + .name =3D "spacemit,k3-ccu", + .of_match_table =3D of_k3_ccu_match, + }, + .probe =3D k3_ccu_probe, +}; +module_platform_driver(k3_ccu_driver); + +MODULE_DESCRIPTION("SpacemiT K3 CCU driver"); +MODULE_LICENSE("GPL"); diff --git a/include/soc/spacemit/ccu.h b/include/soc/spacemit/ccu.h new file mode 100644 index 000000000000..30f4281597d9 --- /dev/null +++ b/include/soc/spacemit/ccu.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_SPACEMIT_CCU_H__ +#define __SOC_SPACEMIT_CCU_H__ + +/* Auxiliary device used to represent a CCU reset controller */ +struct spacemit_ccu_adev { + struct auxiliary_device adev; + struct regmap *regmap; +}; + +static inline struct spacemit_ccu_adev * +to_spacemit_ccu_adev(struct auxiliary_device *adev) +{ + return container_of(adev, struct spacemit_ccu_adev, adev); +} + +#endif /* __SOC_SPACEMIT_CCU_H__ */ diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-sys= con.h index 354751562c55..0be7a2e8d445 100644 --- a/include/soc/spacemit/k1-syscon.h +++ b/include/soc/spacemit/k1-syscon.h @@ -5,17 +5,7 @@ #ifndef __SOC_K1_SYSCON_H__ #define __SOC_K1_SYSCON_H__ =20 -/* Auxiliary device used to represent a CCU reset controller */ -struct spacemit_ccu_adev { - struct auxiliary_device adev; - struct regmap *regmap; -}; - -static inline struct spacemit_ccu_adev * -to_spacemit_ccu_adev(struct auxiliary_device *adev) -{ - return container_of(adev, struct spacemit_ccu_adev, adev); -} +#include "ccu.h" =20 /* APBS register offset */ #define APBS_PLL1_SWCR1 0x100 diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-sys= con.h new file mode 100644 index 000000000000..0299bea065a0 --- /dev/null +++ b/include/soc/spacemit/k3-syscon.h @@ -0,0 +1,273 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* SpacemiT clock and reset driver definitions for the K3 SoC */ + +#ifndef __SOC_K3_SYSCON_H__ +#define __SOC_K3_SYSCON_H__ + +#include "ccu.h" + +/* APBS register offset */ +#define APBS_PLL1_SWCR1 0x100 +#define APBS_PLL1_SWCR2 0x104 +#define APBS_PLL1_SWCR3 0x108 +#define APBS_PLL2_SWCR1 0x118 +#define APBS_PLL2_SWCR2 0x11c +#define APBS_PLL2_SWCR3 0x120 +#define APBS_PLL3_SWCR1 0x124 +#define APBS_PLL3_SWCR2 0x128 +#define APBS_PLL3_SWCR3 0x12c +#define APBS_PLL4_SWCR1 0x130 +#define APBS_PLL4_SWCR2 0x134 +#define APBS_PLL4_SWCR3 0x138 +#define APBS_PLL5_SWCR1 0x13c +#define APBS_PLL5_SWCR2 0x140 +#define APBS_PLL5_SWCR3 0x144 +#define APBS_PLL6_SWCR1 0x148 +#define APBS_PLL6_SWCR2 0x14c +#define APBS_PLL6_SWCR3 0x150 +#define APBS_PLL7_SWCR1 0x158 +#define APBS_PLL7_SWCR2 0x15c +#define APBS_PLL7_SWCR3 0x160 +#define APBS_PLL8_SWCR1 0x180 +#define APBS_PLL8_SWCR2 0x184 +#define APBS_PLL8_SWCR3 0x188 + +/* MPMU register offset */ +#define MPMU_FCCR 0x0008 +#define MPMU_POSR 0x0010 +#define POSR_PLL1_LOCK BIT(24) +#define POSR_PLL2_LOCK BIT(25) +#define POSR_PLL3_LOCK BIT(26) +#define POSR_PLL4_LOCK BIT(27) +#define POSR_PLL5_LOCK BIT(28) +#define POSR_PLL6_LOCK BIT(29) +#define POSR_PLL7_LOCK BIT(30) +#define POSR_PLL8_LOCK BIT(31) +#define MPMU_SUCCR 0x0014 +#define MPMU_ISCCR 0x0044 +#define MPMU_WDTPCR 0x0200 +#define MPMU_RIPCCR 0x0210 +#define MPMU_ACGR 0x1024 +#define MPMU_APBCSCR 0x1050 +#define MPMU_SUCCR_1 0x10b0 + +#define MPMU_I2S0_SYSCLK 0x1100 +#define MPMU_I2S2_SYSCLK 0x1104 +#define MPMU_I2S3_SYSCLK 0x1108 +#define MPMU_I2S4_SYSCLK 0x110c +#define MPMU_I2S5_SYSCLK 0x1110 +#define MPMU_I2S_SYSCLK_CTRL 0x1114 + +/* APBC register offset */ +#define APBC_UART0_CLK_RST 0x00 +#define APBC_UART2_CLK_RST 0x04 +#define APBC_GPIO_CLK_RST 0x08 +#define APBC_PWM0_CLK_RST 0x0c +#define APBC_PWM1_CLK_RST 0x10 +#define APBC_PWM2_CLK_RST 0x14 +#define APBC_PWM3_CLK_RST 0x18 +#define APBC_TWSI8_CLK_RST 0x20 +#define APBC_UART3_CLK_RST 0x24 +#define APBC_RTC_CLK_RST 0x28 +#define APBC_TWSI0_CLK_RST 0x2c +#define APBC_TWSI1_CLK_RST 0x30 +#define APBC_TIMERS0_CLK_RST 0x34 +#define APBC_TWSI2_CLK_RST 0x38 +#define APBC_AIB_CLK_RST 0x3c +#define APBC_TWSI4_CLK_RST 0x40 +#define APBC_TIMERS1_CLK_RST 0x44 +#define APBC_ONEWIRE_CLK_RST 0x48 +#define APBC_TWSI5_CLK_RST 0x4c +#define APBC_DRO_CLK_RST 0x58 +#define APBC_IR0_CLK_RST 0x5c +#define APBC_IR1_CLK_RST 0x1c +#define APBC_TWSI6_CLK_RST 0x60 +#define APBC_COUNTER_CLK_SEL 0x64 +#define APBC_TSEN_CLK_RST 0x6c +#define APBC_UART4_CLK_RST 0x70 +#define APBC_UART5_CLK_RST 0x74 +#define APBC_UART6_CLK_RST 0x78 +#define APBC_SSP3_CLK_RST 0x7c +#define APBC_SSPA0_CLK_RST 0x80 +#define APBC_SSPA1_CLK_RST 0x84 +#define APBC_SSPA2_CLK_RST 0x88 +#define APBC_SSPA3_CLK_RST 0x8c +#define APBC_IPC_AP2AUD_CLK_RST 0x90 +#define APBC_UART7_CLK_RST 0x94 +#define APBC_UART8_CLK_RST 0x98 +#define APBC_UART9_CLK_RST 0x9c +#define APBC_CAN0_CLK_RST 0xa0 +#define APBC_CAN1_CLK_RST 0xa4 +#define APBC_PWM4_CLK_RST 0xa8 +#define APBC_PWM5_CLK_RST 0xac +#define APBC_PWM6_CLK_RST 0xb0 +#define APBC_PWM7_CLK_RST 0xb4 +#define APBC_PWM8_CLK_RST 0xb8 +#define APBC_PWM9_CLK_RST 0xbc +#define APBC_PWM10_CLK_RST 0xc0 +#define APBC_PWM11_CLK_RST 0xc4 +#define APBC_PWM12_CLK_RST 0xc8 +#define APBC_PWM13_CLK_RST 0xcc +#define APBC_PWM14_CLK_RST 0xd0 +#define APBC_PWM15_CLK_RST 0xd4 +#define APBC_PWM16_CLK_RST 0xd8 +#define APBC_PWM17_CLK_RST 0xdc +#define APBC_PWM18_CLK_RST 0xe0 +#define APBC_PWM19_CLK_RST 0xe4 +#define APBC_TIMERS2_CLK_RST 0x11c +#define APBC_TIMERS3_CLK_RST 0x120 +#define APBC_TIMERS4_CLK_RST 0x124 +#define APBC_TIMERS5_CLK_RST 0x128 +#define APBC_TIMERS6_CLK_RST 0x12c +#define APBC_TIMERS7_CLK_RST 0x130 + +#define APBC_CAN2_CLK_RST 0x148 +#define APBC_CAN3_CLK_RST 0x14c +#define APBC_CAN4_CLK_RST 0x150 +#define APBC_UART10_CLK_RST 0x154 +#define APBC_SSP0_CLK_RST 0x158 +#define APBC_SSP1_CLK_RST 0x15c +#define APBC_SSPA4_CLK_RST 0x160 +#define APBC_SSPA5_CLK_RST 0x164 + +/* APMU register offset */ +#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 +#define APMU_ISP_CLK_RES_CTRL 0x038 +#define APMU_PMU_CLK_GATE_CTRL 0x040 +#define APMU_LCD_CLK_RES_CTRL1 0x044 +#define APMU_LCD_SPI_CLK_RES_CTRL 0x048 +#define APMU_LCD_CLK_RES_CTRL2 0x04c +#define APMU_CCIC_CLK_RES_CTRL 0x050 +#define APMU_SDH0_CLK_RES_CTRL 0x054 +#define APMU_SDH1_CLK_RES_CTRL 0x058 +#define APMU_USB_CLK_RES_CTRL 0x05c +#define APMU_QSPI_CLK_RES_CTRL 0x060 +#define APMU_DMA_CLK_RES_CTRL 0x064 +#define APMU_AES_CLK_RES_CTRL 0x068 +#define APMU_MCB_CLK_RES_CTRL 0x06c +#define APMU_VPU_CLK_RES_CTRL 0x0a4 +#define APMU_DTC_CLK_RES_CTRL 0x0ac +#define APMU_GPU_CLK_RES_CTRL 0x0cc +#define APMU_SDH2_CLK_RES_CTRL 0x0e0 +#define APMU_PMUA_MC_CTRL 0x0e8 +#define APMU_PMU_CC2_AP 0x100 +#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 +#define APMU_UCIE_CTRL 0x11c +#define APMU_RCPU_CLK_RES_CTRL 0x14c +#define APMU_TOP_DCLK_CTRL 0x158 +#define APMU_LCD_EDP_CTRL 0x23c +#define APMU_UFS_CLK_RES_CTRL 0x268 +#define APMU_LCD_CLK_RES_CTRL3 0x26c +#define APMU_LCD_CLK_RES_CTRL4 0x270 +#define APMU_LCD_CLK_RES_CTRL5 0x274 +#define APMU_CCI550_CLK_CTRL 0x300 +#define APMU_ACLK_CLK_CTRL 0x388 +#define APMU_CPU_C0_CLK_CTRL 0x38C +#define APMU_CPU_C1_CLK_CTRL 0x390 +#define APMU_CPU_C2_CLK_CTRL 0x394 +#define APMU_CPU_C3_CLK_CTRL 0x208 +#define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 +#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 +#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 +#define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 +#define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 +#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 +#define APMU_EMAC1_CLK_RES_CTRL 0x3ec +#define APMU_EMAC2_CLK_RES_CTRL 0x248 +#define APMU_ESPI_CLK_RES_CTRL 0x240 +#define APMU_SNR_ISIM_VCLK_CTRL 0x3f8 + +/* DCIU register offsets */ +#define DCIU_DMASYS_CLK_EN 0x234 +#define DCIU_DMASYS_SDMA_CLK_EN 0x238 +#define DCIU_C2_TCM_PIPE_CLK 0x244 +#define DCIU_C3_TCM_PIPE_CLK 0x248 + +#define DCIU_DMASYS_S0_RSTN 0x204 +#define DCIU_DMASYS_S1_RSTN 0x208 +#define DCIU_DMASYS_A0_RSTN 0x20C +#define DCIU_DMASYS_A1_RSTN 0x210 +#define DCIU_DMASYS_A2_RSTN 0x214 +#define DCIU_DMASYS_A3_RSTN 0x218 +#define DCIU_DMASYS_A4_RSTN 0x21C +#define DCIU_DMASYS_A5_RSTN 0x220 +#define DCIU_DMASYS_A6_RSTN 0x224 +#define DCIU_DMASYS_A7_RSTN 0x228 +#define DCIU_DMASYS_RSTN 0x22C +#define DCIU_DMASYS_SDMA_RSTN 0x230 + +/* RCPU SYSCTRL register offsets */ +#define RCPU_CAN_CLK_RST 0x4c +#define RCPU_CAN1_CLK_RST 0xF0 +#define RCPU_CAN2_CLK_RST 0xF4 +#define RCPU_CAN3_CLK_RST 0xF8 +#define RCPU_CAN4_CLK_RST 0xFC +#define RCPU_IRC_CLK_RST 0x48 +#define RCPU_IRC1_CLK_RST 0xEC +#define RCPU_GMAC_CLK_RST 0xE4 +#define RCPU_ESPI_CLK_RST 0xDC +#define RCPU_AUDIO_I2S0_SYS_CLK_CTRL 0x70 +#define RCPU_AUDIO_I2S1_SYS_CLK_CTRL 0x44 + +/* RCPU UARTCTRL register offsets */ +#define RCPU1_UART0_CLK_RST 0x00 +#define RCPU1_UART1_CLK_RST 0x04 +#define RCPU1_UART2_CLK_RST 0x08 +#define RCPU1_UART3_CLK_RST 0x0c +#define RCPU1_UART4_CLK_RST 0x10 +#define RCPU1_UART5_CLK_RST 0x14 + +/* RCPU I2SCTRL register offsets */ +#define RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL 0x60 +#define RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL 0x64 +#define RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL 0x68 +#define RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL 0x6C + +#define RCPU2_AUDIO_I2S2_SYS_CLK_CTRL 0x44 +#define RCPU2_AUDIO_I2S3_SYS_CLK_CTRL 0x54 + +/* RCPU SPICTRL register offsets */ +#define RCPU3_SSP0_CLK_RST 0x00 +#define RCPU3_SSP1_CLK_RST 0x04 +#define RCPU3_PWR_SSP_CLK_RST 0x08 + +/* RCPU I2CCTRL register offsets */ +#define RCPU4_I2C0_CLK_RST 0x00 +#define RCPU4_I2C1_CLK_RST 0x04 +#define RCPU4_PWR_I2C_CLK_RST 0x08 + +/* RPMU register offsets */ +#define RCPU5_AON_PER_CLK_RST_CTRL 0x2C +#define RCPU5_TIMER1_CLK_RST 0x4C +#define RCPU5_TIMER2_CLK_RST 0x70 +#define RCPU5_TIMER3_CLK_RST 0x78 +#define RCPU5_TIMER4_CLK_RST 0x7C +#define RCPU5_GPIO_AND_EDGE_CLK_RST 0x74 +#define RCPU5_RCPU_BUS_CLK_CTRL 0xC0 +#define RCPU5_RT24_CORE0_CLK_CTRL 0xC4 +#define RCPU5_RT24_CORE1_CLK_CTRL 0xC8 +#define RCPU5_RT24_CORE0_SW_RESET 0xCC +#define RCPU5_RT24_CORE1_SW_RESET 0xD0 + +/* RCPU PWMCTRL register offsets */ +#define RCPU6_PWM0_CLK_RST 0x00 +#define RCPU6_PWM1_CLK_RST 0x04 +#define RCPU6_PWM2_CLK_RST 0x08 +#define RCPU6_PWM3_CLK_RST 0x0c +#define RCPU6_PWM4_CLK_RST 0x10 +#define RCPU6_PWM5_CLK_RST 0x14 +#define RCPU6_PWM6_CLK_RST 0x18 +#define RCPU6_PWM7_CLK_RST 0x1c +#define RCPU6_PWM8_CLK_RST 0x20 +#define RCPU6_PWM9_CLK_RST 0x24 + +/* APBC2 SEC register offsets */ +#define APBC2_UART1_CLK_RST 0x00 +#define APBC2_SSP2_CLK_RST 0x04 +#define APBC2_TWSI3_CLK_RST 0x08 +#define APBC2_RTC_CLK_RST 0x0c +#define APBC2_TIMERS_CLK_RST 0x10 +#define APBC2_GPIO_CLK_RST 0x1c + +#endif /* __SOC_K3_SYSCON_H__ */ --=20 2.51.0