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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f2e2ffae2sm5924073c88.9.2025.12.11.04.03.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Dec 2025 04:03:47 -0800 (PST) From: Hangxiang Ma Date: Thu, 11 Dec 2025 04:03:43 -0800 Subject: [PATCH v10 1/5] media: dt-bindings: Add CAMSS device for Kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251211-add-support-for-camss-on-kaanapali-v10-1-39e8874dcd27@oss.qualcomm.com> References: <20251211-add-support-for-camss-on-kaanapali-v10-0-39e8874dcd27@oss.qualcomm.com> In-Reply-To: <20251211-add-support-for-camss-on-kaanapali-v10-0-39e8874dcd27@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Hangxiang Ma , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Proofpoint-GUID: vEQosqTnHJNHG7QVXStZvTI4mhI4n5-1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjExMDA5MiBTYWx0ZWRfXxXdOJYNKrkXI nH6RfYzU1suGjwXH0OnVKE5rT/9fS3VsW6K9nXkESIuPrcl7aUTY+7HWITafzQHZifuSY4uaTtG CpeJ3hTR1OdTkmKbO0VHPay4rzBeEa7dNqq6jYwfBcOVW9iV+fU52bpq7TcF5cHEwCRvKt9NI1y 2m80tt0bgjjr5/DWVZTIgtrYKSHpJFwA7oFjnrSP710YgYPObZi91mocEs6XfxGuAKpCIs361DN NghflAXbnxSDtPtpC6Exd6RRiLYLEVutChOPZZ7u2L89heWbXXDsKsTD+zcJxLL6ZolJ7Ip7mSg D/kE5Het3Ux4GgGgf91+KneeWuVsIu+5iA4vYbplWSTyAw083uPu1n+nOJiLrmqgrC9tmiGGSb3 2/DHBEHF3ch64IR8N4WHv1zQ2LSZng== X-Authority-Analysis: v=2.4 cv=YokChoYX c=1 sm=1 tr=0 ts=693ab326 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=KKAkSRfTAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=78032wgmgAfrEkmTq9UA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 a=sptkURWiP4Gy88Gu7hUp:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: vEQosqTnHJNHG7QVXStZvTI4mhI4n5-1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-10_03,2025-12-09_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 suspectscore=0 bulkscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512110092 Add bindings for qcom,kaanapali-camss to support the Camera Subsystem (CAMSS) on the Qualcomm Kaanapali platform. The Kaanapali platform provides: - 3 x VFE (Video Front End), 5 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE Lite - 3 x CSID (CSI Decoder) - 2 x CSID Lite - 6 x CSIPHY (CSI Physical Layer) - 2 x ICP (Image Control Processor) - 1 x IPE (Image Processing Engine) - 2 x JPEG DMA & Downscaler - 2 x JPEG Encoder - 1 x OFE (Offline Front End) - 5 x RT CDM (Camera Data Mover) - 3 x TPG (Test Pattern Generator) Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Hangxiang Ma --- .../bindings/media/qcom,kaanapali-camss.yaml | 646 +++++++++++++++++= ++++ 1 file changed, 646 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.y= aml b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml new file mode 100644 index 000000000000..7108a4f12f58 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml @@ -0,0 +1,646 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,kaanapali-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali Camera Subsystem (CAMSS) + +maintainers: + - Hangxiang Ma + +description: + Kaanapali camera subsystem includes submodules such as CSIPHY (CSI Physi= cal Layer) + and CSID (CSI Decoder), which comply with the MIPI CSI2 protocol. + + The subsystem also integrates a set of real-time image processing engine= s and + their associated configuration modules, as well as non-real-time engines. + + Additionally, it encompasses a test pattern generator (TPG) submodule. + +properties: + compatible: + const: qcom,kaanapali-camss + + reg: + items: + - description: Registers for CSID 0 + - description: Registers for CSID 1 + - description: Registers for CSID 2 + - description: Registers for CSID Lite 0 + - description: Registers for CSID Lite 1 + - description: Registers for CSIPHY 0 + - description: Registers for CSIPHY 1 + - description: Registers for CSIPHY 2 + - description: Registers for CSIPHY 3 + - description: Registers for CSIPHY 4 + - description: Registers for CSIPHY 5 + - description: Registers for VFE (Video Front End) 0 + - description: Registers for VFE 1 + - description: Registers for VFE 2 + - description: Registers for VFE Lite 0 + - description: Registers for VFE Lite 1 + - description: Registers for ICP (Imaging Control Processor) 0 + - description: Registers for ICP 0 SYS + - description: Registers for ICP 1 + - description: Registers for ICP 1 SYS + - description: Registers for IPE (Image Processing Engine) + - description: Registers for JPEG DMA & Downscaler + - description: Registers for JPEG Encoder + - description: Registers for OFE (Offline Front End) + - description: Registers for RT CDM (Camera Data Mover) 0 + - description: Registers for RT CDM 1 + - description: Registers for RT CDM 2 + - description: Registers for RT CDM 3 + - description: Registers for RT CDM 4 + - description: Registers for TPG 0 + - description: Registers for TPG 1 + - description: Registers for TPG 2 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: icp0 + - const: icp0_sys + - const: icp1 + - const: icp1_sys + - const: ipe + - const: jpeg_dma + - const: jpeg_enc + - const: ofe + - const: rt_cdm0 + - const: rt_cdm1 + - const: rt_cdm2 + - const: rt_cdm3 + - const: rt_cdm4 + - const: tpg0 + - const: tpg1 + - const: tpg2 + + clocks: + maxItems: 60 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: camnoc_rt_vfe0 + - const: camnoc_rt_vfe1 + - const: camnoc_rt_vfe2 + - const: camnoc_rt_vfe_lite + - const: cpas_ahb + - const: cpas_fast_ahb + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: gcc_axi_hf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + - const: qdss_debug_xo + - const: camnoc_ipe_nps + - const: camnoc_ofe + - const: gcc_axi_sf + - const: icp0 + - const: icp0_ahb + - const: icp1 + - const: icp1_ahb + - const: ipe_nps + - const: ipe_nps_ahb + - const: ipe_nps_fast_ahb + - const: ipe_pps + - const: ipe_pps_fast_ahb + - const: jpeg + - const: ofe_ahb + - const: ofe_anchor + - const: ofe_anchor_fast_ahb + - const: ofe_hdr + - const: ofe_hdr_fast_ahb + - const: ofe_main + - const: ofe_main_fast_ahb + - const: vfe0_bayer + - const: vfe0_bayer_fast_ahb + - const: vfe1_bayer + - const: vfe1_bayer_fast_ahb + - const: vfe2_bayer + - const: vfe2_bayer_fast_ahb + + interrupts: + maxItems: 30 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: camnoc_nrt + - const: camnoc_rt + - const: icp0 + - const: icp1 + - const: jpeg_dma + - const: jpeg_enc + - const: rt_cdm0 + - const: rt_cdm1 + - const: rt_cdm2 + - const: rt_cdm3 + - const: rt_cdm4 + - const: tpg0 + - const: tpg1 + - const: tpg2 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: cam_ahb + - const: cam_hf_mnoc + - const: cam_sf_icp_mnoc + - const: cam_sf_mnoc + + iommus: + items: + - description: VFE non-protected stream + - description: ICP0 shared stream + - description: ICP1 shared stream + - description: IPE CDM non-protected stream + - description: IPE non-protected stream + - description: JPEG non-protected stream + - description: OFE CDM non-protected stream + - description: OFE non-protected stream + - description: VFE / VFE Lite CDM non-protected stream + + power-domains: + items: + - description: + IFE0 GDSC - Global Distributed Switch Controller for IFE0. + - description: + IFE1 GDSC - Global Distributed Switch Controller for IFE1. + - description: + IFE2 GDSC - Global Distributed Switch Controller for IFE2. + - description: + Titan GDSC - Global Distributed Switch Controller for the entire= camss. + - description: + IPE GDSC - Global Distributed Switch Controller for IPE. + - description: + OFE GDSC - Block Global Distributed Switch Controller for OFE. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + - const: ipe + - const: ofe + + vdd-csiphy0-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY0 core block. + + vdd-csiphy0-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY0 pll block. + + vdd-csiphy1-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY1 core block. + + vdd-csiphy1-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY1 pll block. + + vdd-csiphy2-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY2 core block. + + vdd-csiphy2-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY2 pll block. + + vdd-csiphy3-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY3 core block. + + vdd-csiphy3-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY3 pll block. + + vdd-csiphy4-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY4 core block. + + vdd-csiphy4-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY4 pll block. + + vdd-csiphy5-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY5 core block. + + vdd-csiphy5-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY5 pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + +patternProperties: + "^port@[0-5]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input ports for receiving CSI data on CSIPHY 0-5. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + isp@9253000 { + compatible =3D "qcom,kaanapali-camss"; + + reg =3D <0x0 0x09253000 0x0 0x5e80>, + <0x0 0x09263000 0x0 0x5e80>, + <0x0 0x09273000 0x0 0x5e80>, + <0x0 0x092d3000 0x0 0x3880>, + <0x0 0x092e7000 0x0 0x3880>, + <0x0 0x09523000 0x0 0x2000>, + <0x0 0x09525000 0x0 0x2000>, + <0x0 0x09527000 0x0 0x2000>, + <0x0 0x09529000 0x0 0x2000>, + <0x0 0x0952b000 0x0 0x2000>, + <0x0 0x0952d000 0x0 0x2000>, + <0x0 0x09151000 0x0 0x20000>, + <0x0 0x09171000 0x0 0x20000>, + <0x0 0x09191000 0x0 0x20000>, + <0x0 0x092dc000 0x0 0x1300>, + <0x0 0x092f0000 0x0 0x1300>, + <0x0 0x0900e000 0x0 0x1000>, + <0x0 0x0900d000 0x0 0x1000>, + <0x0 0x0902e000 0x0 0x1000>, + <0x0 0x0902d000 0x0 0x1000>, + <0x0 0x090d7000 0x0 0x20000>, + <0x0 0x0904e000 0x0 0x1000>, + <0x0 0x0904d000 0x0 0x1000>, + <0x0 0x09057000 0x0 0x40000>, + <0x0 0x09147000 0x0 0x580>, + <0x0 0x09148000 0x0 0x580>, + <0x0 0x09149000 0x0 0x580>, + <0x0 0x0914a000 0x0 0x580>, + <0x0 0x0914b000 0x0 0x580>, + <0x0 0x093fd000 0x0 0x400>, + <0x0 0x093fe000 0x0 0x400>, + <0x0 0x093ff000 0x0 0x400>; + reg-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "icp0", + "icp0_sys", + "icp1", + "icp1_sys", + "ipe", + "jpeg_dma", + "jpeg_enc", + "ofe", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + clocks =3D <&camcc_cam_cc_camnoc_nrt_axi_clk>, + <&camcc_cam_cc_camnoc_rt_axi_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_0_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_1_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_2_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_lite_clk>, + <&camcc_cam_cc_cam_top_ahb_clk>, + <&camcc_cam_cc_cam_top_fast_ahb_clk>, + <&camcc_cam_cc_csid_clk>, + <&camcc_cam_cc_csid_csiphy_rx_clk>, + <&camcc_cam_cc_csiphy0_clk>, + <&camcc_cam_cc_csi0phytimer_clk>, + <&camcc_cam_cc_csiphy1_clk>, + <&camcc_cam_cc_csi1phytimer_clk>, + <&camcc_cam_cc_csiphy2_clk>, + <&camcc_cam_cc_csi2phytimer_clk>, + <&camcc_cam_cc_csiphy3_clk>, + <&camcc_cam_cc_csi3phytimer_clk>, + <&camcc_cam_cc_csiphy4_clk>, + <&camcc_cam_cc_csi4phytimer_clk>, + <&camcc_cam_cc_csiphy5_clk>, + <&camcc_cam_cc_csi5phytimer_clk>, + <&gcc_gcc_camera_hf_axi_clk>, + <&camcc_cam_cc_vfe_0_main_clk>, + <&camcc_cam_cc_vfe_0_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_1_main_clk>, + <&camcc_cam_cc_vfe_1_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_2_main_clk>, + <&camcc_cam_cc_vfe_2_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_lite_clk>, + <&camcc_cam_cc_vfe_lite_ahb_clk>, + <&camcc_cam_cc_vfe_lite_cphy_rx_clk>, + <&camcc_cam_cc_vfe_lite_csid_clk>, + <&camcc_cam_cc_qdss_debug_xo_clk>, + <&camcc_cam_cc_camnoc_nrt_ipe_nps_clk>, + <&camcc_cam_cc_camnoc_nrt_ofe_main_clk>, + <&gcc_gcc_camera_sf_axi_clk>, + <&camcc_cam_cc_icp_0_clk>, + <&camcc_cam_cc_icp_0_ahb_clk>, + <&camcc_cam_cc_icp_1_clk>, + <&camcc_cam_cc_icp_1_ahb_clk>, + <&camcc_cam_cc_ipe_nps_clk>, + <&camcc_cam_cc_ipe_nps_ahb_clk>, + <&camcc_cam_cc_ipe_nps_fast_ahb_clk>, + <&camcc_cam_cc_ipe_pps_clk>, + <&camcc_cam_cc_ipe_pps_fast_ahb_clk>, + <&camcc_cam_cc_jpeg_clk>, + <&camcc_cam_cc_ofe_ahb_clk>, + <&camcc_cam_cc_ofe_anchor_clk>, + <&camcc_cam_cc_ofe_anchor_fast_ahb_clk>, + <&camcc_cam_cc_ofe_hdr_clk>, + <&camcc_cam_cc_ofe_hdr_fast_ahb_clk>, + <&camcc_cam_cc_ofe_main_clk>, + <&camcc_cam_cc_ofe_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_0_bayer_clk>, + <&camcc_cam_cc_vfe_0_bayer_fast_ahb_clk>, + <&camcc_cam_cc_vfe_1_bayer_clk>, + <&camcc_cam_cc_vfe_1_bayer_fast_ahb_clk>, + <&camcc_cam_cc_vfe_2_bayer_clk>, + <&camcc_cam_cc_vfe_2_bayer_fast_ahb_clk>; + clock-names =3D "camnoc_nrt_axi", + "camnoc_rt_axi", + "camnoc_rt_vfe0", + "camnoc_rt_vfe1", + "camnoc_rt_vfe2", + "camnoc_rt_vfe_lite", + "cpas_ahb", + "cpas_fast_ahb", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "gcc_axi_hf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "qdss_debug_xo", + "camnoc_ipe_nps", + "camnoc_ofe", + "gcc_axi_sf", + "icp0", + "icp0_ahb", + "icp1", + "icp1_ahb", + "ipe_nps", + "ipe_nps_ahb", + "ipe_nps_fast_ahb", + "ipe_pps", + "ipe_pps_fast_ahb", + "jpeg", + "ofe_ahb", + "ofe_anchor", + "ofe_anchor_fast_ahb", + "ofe_hdr", + "ofe_hdr_fast_ahb", + "ofe_main", + "ofe_main_fast_ahb", + "vfe0_bayer", + "vfe0_bayer_fast_ahb", + "vfe1_bayer", + "vfe1_bayer_fast_ahb", + "vfe2_bayer", + "vfe2_bayer_fast_ahb"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "camnoc_nrt", + "camnoc_rt", + "icp0", + "icp1", + "jpeg_dma", + "jpeg_enc", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + interconnects =3D <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACT= IVE_ONLY + &config_noc_slave_camera_cfg QCOM_ICC_TAG_ACT= IVE_ONLY>, + <&mmss_noc_master_camnoc_hf QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc_master_camnoc_sf_icp QCOM_ICC_TAG_A= LWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc_master_camnoc_sf QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "cam_ahb", + "cam_hf_mnoc", + "cam_sf_icp_mnoc", + "cam_sf_mnoc"; + + iommus =3D <&apps_smmu 0x1c00 0x00>, + <&apps_smmu 0x18c0 0x00>, + <&apps_smmu 0x1980 0x00>, + <&apps_smmu 0x1840 0x00>, + <&apps_smmu 0x1800 0x00>, + <&apps_smmu 0x18a0 0x00>, + <&apps_smmu 0x1880 0x00>, + <&apps_smmu 0x1820 0x00>, + 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f2e2ffae2sm5924073c88.9.2025.12.11.04.03.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Dec 2025 04:03:48 -0800 (PST) From: Hangxiang Ma Date: Thu, 11 Dec 2025 04:03:44 -0800 Subject: [PATCH v10 2/5] media: qcom: camss: Add Kaanapali compatible camss driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251211-add-support-for-camss-on-kaanapali-v10-2-39e8874dcd27@oss.qualcomm.com> References: <20251211-add-support-for-camss-on-kaanapali-v10-0-39e8874dcd27@oss.qualcomm.com> In-Reply-To: <20251211-add-support-for-camss-on-kaanapali-v10-0-39e8874dcd27@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Hangxiang Ma X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=At7jHe9P c=1 sm=1 tr=0 ts=693ab326 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=Eph36bqoL6-XvbZcx_wA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 78_Yn4dtce7cRr8--XmF35cNMDmol63Y X-Proofpoint-GUID: 78_Yn4dtce7cRr8--XmF35cNMDmol63Y X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjExMDA5MiBTYWx0ZWRfX3NOOLT07t1sH jarkcFiF6cXWLJJvB36RwtRHw+hlEewQ1QAAkxIL9SH37wAoCORkck4lZIybbCXtm2sJhnLxatL TZVVE3eoYcGZjoVQOWizd4zEKt3wnanAw59YWrNoJVD9QvMqIgIV84D6KeufOYmAHVvGMHFC+QV 7o7WuBJYmgHT/K1uls2j6zXQftq3mcvZqqmzBep3x5WGbrc1SCX+vHT1DushqImcDEjZ0nGfTWC a6HyUSAYrlB3XU6dq8DT9FbF96bjv0koh9oFeWmfutMwLe8Ld2kTh/TQs7xXDXUSXUlP5kdnn2V Eg5HYaoav2zXh9qma0FpNWmH0id8ztgmlSHkywFbvn4K7z7dQDM8KPqKqw2RBv+uo084VCMyzTK 7YZbYvBkU0ZasLaybRLmNK+9bdYzyw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-10_03,2025-12-09_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 phishscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512110092 Add support for Kaanapali in the camss driver. Add high level resource information along with the bus bandwidth votes. Module level detailed resource information will be enumerated in the following patches of the series. Reviewed-by: Bryan O'Donoghue Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/camss.c | 22 ++++++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 2fbcd0e343aa..6388897c5fad 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -34,6 +34,20 @@ =20 static const struct parent_dev_ops vfe_parent_dev_ops; =20 +static const struct resources_icc icc_res_kaanapali[] =3D { + { + .name =3D "cam_ahb", + .icc_bw_tbl.avg =3D 150000, + .icc_bw_tbl.peak =3D 300000, + }, + /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */ + { + .name =3D "cam_hf_mnoc", + .icc_bw_tbl.avg =3D 471860, + .icc_bw_tbl.peak =3D 925857, + }, +}; + static const struct camss_subdev_resources csiphy_res_8x16[] =3D { /* CSIPHY0 */ { @@ -4291,6 +4305,13 @@ static void camss_remove(struct platform_device *pde= v) camss_genpd_cleanup(camss); } =20 +static const struct camss_resources kaanapali_resources =3D { + .version =3D CAMSS_KAANAPALI, + .pd_name =3D "top", + .icc_res =3D icc_res_kaanapali, + .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), +}; + static const struct camss_resources msm8916_resources =3D { .version =3D CAMSS_8x16, .csiphy_res =3D csiphy_res_8x16, @@ -4467,6 +4488,7 @@ static const struct camss_resources x1e80100_resource= s =3D { }; =20 static const struct of_device_id camss_dt_match[] =3D { + { .compatible =3D "qcom,kaanapali-camss", .data =3D &kaanapali_resources = }, { .compatible =3D "qcom,msm8916-camss", .data =3D &msm8916_resources }, { .compatible =3D "qcom,msm8953-camss", .data =3D &msm8953_resources }, { .compatible =3D "qcom,msm8996-camss", .data =3D &msm8996_resources }, diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index 901f84efaf7d..876cd2a64cbe 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -90,6 +90,7 @@ enum camss_version { CAMSS_845, CAMSS_8550, CAMSS_8775P, + CAMSS_KAANAPALI, CAMSS_X1E80100, }; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f2e2ffae2sm5924073c88.9.2025.12.11.04.03.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Dec 2025 04:03:49 -0800 (PST) From: Hangxiang Ma Date: Thu, 11 Dec 2025 04:03:45 -0800 Subject: [PATCH v10 3/5] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251211-add-support-for-camss-on-kaanapali-v10-3-39e8874dcd27@oss.qualcomm.com> References: <20251211-add-support-for-camss-on-kaanapali-v10-0-39e8874dcd27@oss.qualcomm.com> In-Reply-To: <20251211-add-support-for-camss-on-kaanapali-v10-0-39e8874dcd27@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjExMDA5MiBTYWx0ZWRfX5+IT1TUS8u7p mZdYl25Lnp97Bmhfj4O2VPRHvRuoJpiCBlUPXjL51qTbfYybPbLhv+RWV1iF7PTg50eP35YXuLl lF4s4GuAy7dphFbNu1lQ6eGR+rrvzEcRAxYyU0+7hVxUoZOvhc9jiiJi+9/oeCr3w3GrvlNz2xM 44S5Vt3DmR13hPySwJuntHH5v19hOIDeyFFOciU4I3lPWhReT794m0jFtp1w+FTb5IZtVmI39rh oKpZM0p69UmMRpPavH+gmshLA6vMCdpzDEMx9RoO1hpI2z6t52nuj+0WmpSrRb+23keppWNoaNC qBOZNcS1QB/jb15aqwTkAdrpnZyUvjiM/FhuRdSwruUYd1GsETlAEjud9DWkCwMACuO6emWOn3N kUniglujHEG6y7r8RcU7NSu0aVpgdg== X-Proofpoint-GUID: 4psxoHAY2CMaO54iuhdC81mQeqsu8Ji9 X-Authority-Analysis: v=2.4 cv=C6nkCAP+ c=1 sm=1 tr=0 ts=693ab327 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=fxCOb-bM6HI3QnfcwHgA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 4psxoHAY2CMaO54iuhdC81mQeqsu8Ji9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-10_03,2025-12-09_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 impostorscore=0 phishscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512110092 Add more detailed resource information for CSIPHY devices in the camss driver along with the support for v2.4.0 in the 2 phase CSIPHY driver that is responsible for the PHY lane register configuration, module reset and interrupt handling. Reviewed-by: Bryan O'Donoghue Signed-off-by: Hangxiang Ma --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 124 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss.c | 107 ++++++++++++++++++ 2 files changed, 231 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 9b6a0535cdf8..b186029cd604 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -588,6 +588,123 @@ csiphy_lane_regs lane_regs_sm8550[] =3D { {0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 +/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */ +static const struct +csiphy_lane_regs lane_regs_2_4_0[] =3D { + /* LN 0 */ + {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x005C, 0x54, 0x00, CSIPHY_SKEW_CAL}, + {0x0060, 0xFD, 0x00, CSIPHY_SKEW_CAL}, + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + /* LN 2 */ + {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x045C, 0x54, 0x00, CSIPHY_SKEW_CAL}, + {0x0460, 0xFD, 0x00, CSIPHY_SKEW_CAL}, + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + /* LN 4 */ + {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x085C, 0x54, 0x00, CSIPHY_SKEW_CAL}, + {0x0860, 0xFD, 0x00, CSIPHY_SKEW_CAL}, + {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + /* LN 6 */ + {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x0C5C, 0x54, 0x00, CSIPHY_SKEW_CAL}, + {0x0C60, 0xFD, 0x00, CSIPHY_SKEW_CAL}, + {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + /* LN CLK */ + {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + /* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */ static const struct csiphy_lane_regs lane_regs_x1e80100[] =3D { @@ -921,6 +1038,7 @@ static bool csiphy_is_gen2(u32 version) case CAMSS_845: case CAMSS_8550: case CAMSS_8775P: + case CAMSS_KAANAPALI: case CAMSS_X1E80100: ret =3D true; break; @@ -1030,6 +1148,12 @@ static int csiphy_init(struct csiphy_device *csiphy) regs->lane_regs =3D &lane_regs_sa8775p[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sa8775p); break; + case CAMSS_KAANAPALI: + regs->lane_regs =3D &lane_regs_2_4_0[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_2_4_0); + regs->offset =3D 0x1000; + regs->common_status_offset =3D 0x138; + break; default: break; } diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 6388897c5fad..9a650503d10e 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -34,6 +34,111 @@ =20 static const struct parent_dev_ops vfe_parent_dev_ops; =20 +static const struct camss_subdev_resources csiphy_res_kaanapali[] =3D { + /* CSIPHY0 */ + { + .regulators =3D { "vdd-csiphy0-0p8", "vdd-csiphy0-1p2" }, + .clock =3D { "csiphy0", "csiphy0_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy0" }, + .interrupt =3D { "csiphy0" }, + .csiphy =3D { + .id =3D 0, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY1 */ + { + .regulators =3D { "vdd-csiphy1-0p8", "vdd-csiphy1-1p2" }, + .clock =3D { "csiphy1", "csiphy1_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy1" }, + .interrupt =3D { "csiphy1" }, + .csiphy =3D { + .id =3D 1, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY2 */ + { + .regulators =3D { "vdd-csiphy2-0p8", "vdd-csiphy2-1p2" }, + .clock =3D { "csiphy2", "csiphy2_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy2" }, + .interrupt =3D { "csiphy2" }, + .csiphy =3D { + .id =3D 2, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY3 */ + { + .regulators =3D { "vdd-csiphy3-0p8", "vdd-csiphy3-1p2" }, + .clock =3D { "csiphy3", "csiphy3_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy3" }, + .interrupt =3D { "csiphy3" }, + .csiphy =3D { + .id =3D 3, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY4 */ + { + .regulators =3D { "vdd-csiphy4-0p8", "vdd-csiphy4-1p2" }, + .clock =3D { "csiphy4", "csiphy4_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy4" }, + .interrupt =3D { "csiphy4" }, + .csiphy =3D { + .id =3D 4, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY5 */ + { + .regulators =3D { "vdd-csiphy5-0p8", "vdd-csiphy5-1p2" }, + .clock =3D { "csiphy5", "csiphy5_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy5" }, + .interrupt =3D { "csiphy5" }, + .csiphy =3D { + .id =3D 5, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, +}; + static const struct resources_icc icc_res_kaanapali[] =3D { { .name =3D "cam_ahb", @@ -4308,8 +4413,10 @@ static void camss_remove(struct platform_device *pde= v) static const struct camss_resources kaanapali_resources =3D { .version =3D CAMSS_KAANAPALI, .pd_name =3D "top", + .csiphy_res =3D csiphy_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), + .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), }; =20 static const struct camss_resources msm8916_resources =3D { --=20 2.34.1 From nobody Fri Dec 19 09:54:35 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f2e2ffae2sm5924073c88.9.2025.12.11.04.03.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Dec 2025 04:03:50 -0800 (PST) From: Hangxiang Ma Date: Thu, 11 Dec 2025 04:03:46 -0800 Subject: [PATCH v10 4/5] media: qcom: camss: csid: Add support for CSID gen4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251211-add-support-for-camss-on-kaanapali-v10-4-39e8874dcd27@oss.qualcomm.com> References: <20251211-add-support-for-camss-on-kaanapali-v10-0-39e8874dcd27@oss.qualcomm.com> In-Reply-To: <20251211-add-support-for-camss-on-kaanapali-v10-0-39e8874dcd27@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Hangxiang Ma , Atiya Kailany X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: nJxJplt84dRQXjLpbi8QhOuu5eTJVbEu X-Proofpoint-GUID: nJxJplt84dRQXjLpbi8QhOuu5eTJVbEu X-Authority-Analysis: v=2.4 cv=G9sR0tk5 c=1 sm=1 tr=0 ts=693ab329 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=FsTJpaSC_kWcQGXz8SoA:9 a=4Q4zU7iZy6iiv8wZ:21 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjExMDA5MiBTYWx0ZWRfX8kMnG7L4dlMf i9tT4vcTbXwuwlibO7WllrtbMYA2KMemZjADeDXZW50bKyX/qeyE3+K6lItv3p0NSOQCZ6qJnnu vKh42UUqJWVs5/BLNVnXFRjbMa/jhKkUvm6biqwrAa5tFcG1iHx1Tg8zbNbGAMzO8ZzUQOJp5iZ 5UE1aaHM28R3qZ810ucpZtH2c7aePQ4FgWYXuE8z7G5W574K3ecs9e7p8ZovCgCprw4h7MrZsXX gCUOsketar8HDyX689LI4cas+RTfGDcEZkYcUivrgaIWyuVrx0ZX1+/wwY6zHmUXe/stXwyuYeW +PAk1pe5w09GjKyJq54849cmxjWsGxtThdDQK05lOAR2wR9nywruFm9YegSbc/2o22swQNY1UmA DhN6BMMp55sd8Z/lwaH3oV+keR3a9g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-10_03,2025-12-09_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512110092 Add more detailed resource information for CSID devices along with the driver for CSID gen4 that is responsible for CSID register configuration, module reset and IRQ handling for BUF_DONE events. And aggregate a common definition 'CSI2_RX_CFG0_PHY_SEL_BASE_IDX' into csid header file. In this CSID version, RUP and AUP update values are split into two registers along with a SET register. Accordingly, enhance the CSID interface to accommodate both the legacy combined reg_update and the split RUP and AUP updates. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/Makefile | 1 + drivers/media/platform/qcom/camss/camss-csid-680.c | 1 - .../media/platform/qcom/camss/camss-csid-gen3.c | 1 - .../media/platform/qcom/camss/camss-csid-gen4.c | 376 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-csid.h | 11 +- drivers/media/platform/qcom/camss/camss.c | 80 +++++ 6 files changed, 467 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index 23960d02877d..738d57214056 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -10,6 +10,7 @@ qcom-camss-objs +=3D \ camss-csid-680.o \ camss-csid-gen2.o \ camss-csid-gen3.o \ + camss-csid-gen4.o \ camss-csiphy-2ph-1-0.o \ camss-csiphy-3ph-1-0.o \ camss-csiphy.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-680.c b/drivers/m= edia/platform/qcom/camss/camss-csid-680.c index 3ad3a174bcfb..86134a23cd4e 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-680.c +++ b/drivers/media/platform/qcom/camss/camss-csid-680.c @@ -101,7 +101,6 @@ #define CSI2_RX_CFG0_DL2_INPUT_SEL 12 #define CSI2_RX_CFG0_DL3_INPUT_SEL 16 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 -#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 #define CSI2_RX_CFG0_PHY_TYPE_SEL 24 =20 #define CSID_CSI2_RX_CFG1 0x204 diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/= media/platform/qcom/camss/camss-csid-gen3.c index 664245cf6eb0..f09b5575572a 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c @@ -103,7 +103,6 @@ #define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (csid_is_lite(csid) && IS_CSID_= 690(csid) ?\ (0x34C + 0x100 * (rdi)) :\ (0x54C + 0x100 * (rdi))) -#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 =20 static void __csid_configure_rx(struct csid_device *csid, struct csid_phy_config *phy, int vc) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen4.c b/drivers/= media/platform/qcom/camss/camss-csid-gen4.c new file mode 100644 index 000000000000..b000bd3e9c2e --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-csid-gen4.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-csid-gen4.c + * + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include + +#include "camss.h" +#include "camss-csid.h" +#include "camss-csid-gen3.h" + +/* Reset and Command Registers */ +#define CSID_RST_CFG 0x108 +#define RST_MODE BIT(0) +#define RST_LOCATION BIT(4) + +/* Reset and Command Registers */ +#define CSID_RST_CMD 0x10C +#define SELECT_HW_RST BIT(0) +#define SELECT_IRQ_RST BIT(2) +#define CSID_IRQ_CMD 0x110 +#define IRQ_CMD_CLEAR BIT(0) + +/* Register Update Commands, RUP/AUP */ +#define CSID_RUP_CMD 0x114 +#define CSID_AUP_CMD 0x118 +#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi)) +#define CSID_RUP_AUP_CMD 0x11C +#define RUP_SET BIT(0) +#define MUP BIT(4) + +/* Top level interrupt registers */ +#define CSID_TOP_IRQ_STATUS 0x180 +#define CSID_TOP_IRQ_MASK 0x184 +#define CSID_TOP_IRQ_CLEAR 0x188 +#define INFO_RST_DONE BIT(0) +#define CSI2_RX_IRQ_STATUS BIT(2) +#define BUF_DONE_IRQ_STATUS BIT(3) + +/* Buffer done interrupt registers */ +#define CSID_BUF_DONE_IRQ_STATUS 0x1A0 +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET 16 +#define CSID_BUF_DONE_IRQ_MASK 0x1A4 +#define CSID_BUF_DONE_IRQ_CLEAR 0x1A8 +#define CSID_BUF_DONE_IRQ_SET 0x1AC + +/* CSI2 RX interrupt registers */ +#define CSID_CSI2_RX_IRQ_STATUS 0x1B0 +#define CSID_CSI2_RX_IRQ_MASK 0x1B4 +#define CSID_CSI2_RX_IRQ_CLEAR 0x1B8 +#define CSID_CSI2_RX_IRQ_SET 0x1BC + +/* CSI2 RX Configuration */ +#define CSID_CSI2_RX_CFG0 0x880 +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4 +#define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSID_CSI2_RX_CFG1 0x884 +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) +#define CSI2_RX_CFG1_VC_MODE BIT(2) + +#define MSM_CSID_MAX_SRC_STREAMS_GEN4 (csid_is_lite(csid) ? 4 : 5) + +/* RDI Configuration */ +#define CSID_RDI_CFG0(rdi) \ + ((csid_is_lite(csid) ? 0x3080 : 0x5480) + 0x200 * (rdi)) +#define RDI_CFG0_RETIME_BS BIT(5) +#define RDI_CFG0_TIMESTAMP_EN BIT(6) +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) +#define RDI_CFG0_DECODE_FORMAT 12 +#define RDI_CFG0_DT 16 +#define RDI_CFG0_VC 22 +#define RDI_CFG0_EN BIT(31) + +/* RDI Control and Configuration */ +#define CSID_RDI_CTRL(rdi) \ + ((csid_is_lite(csid) ? 0x3088 : 0x5488) + 0x200 * (rdi)) +#define RDI_CTRL_START_CMD BIT(0) + +#define CSID_RDI_CFG1(rdi) \ + ((csid_is_lite(csid) ? 0x3094 : 0x5494) + 0x200 * (rdi)) +#define RDI_CFG1_DROP_H_EN BIT(5) +#define RDI_CFG1_DROP_V_EN BIT(6) +#define RDI_CFG1_CROP_H_EN BIT(7) +#define RDI_CFG1_CROP_V_EN BIT(8) +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) + +/* RDI Pixel Store Configuration */ +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0x5498 + 0x200 * (rdi)) +#define RDI_PIX_STORE_CFG0_EN BIT(0) +#define RDI_PIX_STORE_CFG0_MIN_HBI 1 + +/* RDI IRQ Status in wrapper */ +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) (0x224 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_MASK(rdi) (0x228 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) (0x22C + (0x10 * (rdi))) +#define INFO_RUP_DONE BIT(23) + +static void __csid_aup_rup_trigger(struct csid_device *csid) +{ + /* trigger SET in combined register */ + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD); +} + +static void __csid_aup_rup_clear(struct csid_device *csid, int port_id) +{ + /* Hardware clears the registers upon consuming the settings */ + csid->aup_update &=3D ~CSID_RUP_AUP_RDI(port_id); + csid->rup_update &=3D ~CSID_RUP_AUP_RDI(port_id); +} + +static void __csid_aup_update(struct csid_device *csid, int port_id) +{ + csid->aup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->aup_update, csid->base + CSID_AUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_reg_update(struct csid_device *csid, int port_id) +{ + csid->rup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->rup_update, csid->base + CSID_RUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_configure_rx(struct csid_device *csid, + struct csid_phy_config *phy) +{ + int val; + + val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; + val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + writel(val, csid->base + CSID_CSI2_RX_CFG0); + + val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; + writel(val, csid->base + CSID_CSI2_RX_CFG1); +} + +static void __csid_configure_rx_vc(struct csid_device *csid, int vc) +{ + int val; + + if (vc > 3) { + val =3D readl(csid->base + CSID_CSI2_RX_CFG1); + val |=3D CSI2_RX_CFG1_VC_MODE; + writel(val, csid->base + CSID_CSI2_RX_CFG1); + } +} + +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi) +{ + int val =3D 0; + + if (enable) + val =3D RDI_CTRL_START_CMD; + + writel(val, csid->base + CSID_RDI_CTRL(rdi)); +} + +static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rd= i) +{ + u32 val; + + /* Configure pixel store to allow absorption of hblanking or idle time. + * This helps with horizontal crop and prevents line buffer conflicts. + * Reset state is 0x8 which has MIN_HBI=3D4, we keep the default MIN_HBI + * and just enable the pixel store functionality. + */ + val =3D (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN; + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi)); +} + +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enabl= e, u8 vc) +{ + u32 val; + u8 lane_cnt =3D csid->phy.lane_cnt; + + /* Source pads matching RDI channels on hardware. + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. + */ + struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIRST= _SRC + vc]; + const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res->f= ormats->formats, + csid->res->formats->nformats, + input_format->code); + + if (!lane_cnt) + lane_cnt =3D 4; + + val =3D RDI_CFG0_TIMESTAMP_EN; + val |=3D RDI_CFG0_TIMESTAMP_STB_SEL; + val |=3D RDI_CFG0_RETIME_BS; + + /* note: for non-RDI path, this should be format->decode_format */ + val |=3D DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; + val |=3D vc << RDI_CFG0_VC; + val |=3D format->data_type << RDI_CFG0_DT; + writel(val, csid->base + CSID_RDI_CFG0(vc)); + + val =3D RDI_CFG1_PACKING_FORMAT_MIPI; + writel(val, csid->base + CSID_RDI_CFG1(vc)); + + /* Configure pixel store using dedicated register in gen4 */ + if (!csid_is_lite(csid)) + __csid_configure_rdi_pix_store(csid, vc); + + val =3D 0; + writel(val, csid->base + CSID_RDI_CTRL(vc)); + + val =3D readl(csid->base + CSID_RDI_CFG0(vc)); + + if (enable) + val |=3D RDI_CFG0_EN; + + writel(val, csid->base + CSID_RDI_CFG0(vc)); +} + +static void csid_configure_stream(struct csid_device *csid, u8 enable) +{ + u8 i; + u8 vc; + + __csid_configure_rx(csid, &csid->phy); + + for (vc =3D 0; vc < MSM_CSID_MAX_SRC_STREAMS_GEN4; vc++) { + if (csid->phy.en_vc & BIT(vc)) { + __csid_configure_rdi_stream(csid, enable, vc); + __csid_configure_rx_vc(csid, vc); + + for (i =3D 0; i < CAMSS_INIT_BUF_COUNT; i++) + __csid_aup_update(csid, vc); + + __csid_reg_update(csid, vc); + + __csid_ctrl_rdi(csid, enable, vc); + } + } +} + +static int csid_configure_testgen_pattern(struct csid_device *csid, s32 va= l) +{ + return 0; +} + +static void csid_subdev_reg_update(struct csid_device *csid, int port_id, + bool clear) +{ + if (clear) + __csid_aup_rup_clear(csid, port_id); + else + __csid_aup_update(csid, port_id); +} + +/** + * csid_isr - CSID module interrupt service routine + * @irq: Interrupt line + * @dev: CSID device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t csid_isr(int irq, void *dev) +{ + struct csid_device *csid =3D dev; + u32 val, buf_done_val; + u8 reset_done; + int i; + + val =3D readl(csid->base + CSID_TOP_IRQ_STATUS); + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + + reset_done =3D val & INFO_RST_DONE; + + buf_done_val =3D readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + val =3D readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); + + if (val & INFO_RUP_DONE) + csid_subdev_reg_update(csid, i, true); + + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) + camss_buf_done(csid->camss, csid->id, i); + } + } + + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + if (reset_done) + complete(&csid->reset_complete); + + return IRQ_HANDLED; +} + +/** + * csid_reset - Trigger reset on CSID module and wait to complete + * @csid: CSID device + * + * Return 0 on success or a negative error code otherwise + */ +static int csid_reset(struct csid_device *csid) +{ + unsigned long time; + u32 val; + int i; + + reinit_completion(&csid->reset_complete); + + val =3D INFO_RST_DONE | BUF_DONE_IRQ_STATUS; + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + writel(val, csid->base + CSID_TOP_IRQ_MASK); + + val =3D 0; + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + /* + * Only need to clear buf done IRQ status here, + * RUP done IRQ status will be cleared once isr + * strobe generated by CSID_RST_CMD + */ + val |=3D BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i); + } + } + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK); + + /* Clear all IRQ status with CLEAR bits set */ + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + val =3D RST_LOCATION | RST_MODE; + writel(val, csid->base + CSID_RST_CFG); + + val =3D SELECT_HW_RST | SELECT_IRQ_RST; + writel(val, csid->base + CSID_RST_CMD); + + time =3D wait_for_completion_timeout(&csid->reset_complete, + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); + + if (!time) { + dev_err(csid->camss->dev, "CSID reset timeout\n"); + return -EIO; + } + + return 0; +} + +static void csid_subdev_init(struct csid_device *csid) +{ + csid->testgen.nmodes =3D CSID_PAYLOAD_MODE_DISABLED; +} + +const struct csid_hw_ops csid_ops_gen4 =3D { + .configure_stream =3D csid_configure_stream, + .configure_testgen_pattern =3D csid_configure_testgen_pattern, + .hw_version =3D csid_hw_version, + .isr =3D csid_isr, + .reset =3D csid_reset, + .src_pad_code =3D csid_src_pad_code, + .subdev_init =3D csid_subdev_init, + .reg_update =3D csid_subdev_reg_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media= /platform/qcom/camss/camss-csid.h index aedc96ed84b2..75a113050eb1 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -27,6 +27,8 @@ /* CSID hardware can demultiplex up to 4 outputs */ #define MSM_CSID_MAX_SRC_STREAMS 4 =20 +/* CSIPHY to hardware PHY selector mapping */ +#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 #define CSID_RESET_TIMEOUT_MS 500 =20 enum csid_testgen_mode { @@ -154,7 +156,13 @@ struct csid_device { void __iomem *base; u32 irq; char irq_name[30]; - u32 reg_update; + union { + u32 reg_update; + struct { + u32 rup_update; + u32 aup_update; + }; + }; struct camss_clock *clock; int nclocks; struct regulator_bulk_data *supplies; @@ -217,6 +225,7 @@ extern const struct csid_hw_ops csid_ops_340; extern const struct csid_hw_ops csid_ops_680; extern const struct csid_hw_ops csid_ops_gen2; extern const struct csid_hw_ops csid_ops_gen3; +extern const struct csid_hw_ops csid_ops_gen4; =20 /* * csid_is_lite - Check if CSID is CSID lite. diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 9a650503d10e..f79830e9f7c4 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -139,6 +139,84 @@ static const struct camss_subdev_resources csiphy_res_= kaanapali[] =3D { }, }; =20 +static const struct camss_subdev_resources csid_res_kaanapali[] =3D { + /* CSID0 */ + { + .regulators =3D {}, + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .regulators =3D {}, + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .regulators =3D {}, + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid2" }, + .interrupt =3D { "csid2" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE0 */ + { + .regulators =3D {}, + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite0" }, + .interrupt =3D { "csid_lite0" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE1 */ + { + .regulators =3D {}, + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite1" }, + .interrupt =3D { "csid_lite1" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + } +}; + static const struct resources_icc icc_res_kaanapali[] =3D { { .name =3D "cam_ahb", @@ -4414,9 +4492,11 @@ static const struct camss_resources kaanapali_resour= ces =3D { .version =3D CAMSS_KAANAPALI, .pd_name =3D "top", .csiphy_res =3D csiphy_res_kaanapali, + .csid_res =3D csid_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), + .csid_num =3D ARRAY_SIZE(csid_res_kaanapali), }; =20 static const struct camss_resources msm8916_resources =3D { --=20 2.34.1 From nobody Fri Dec 19 09:54:35 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0108C30CD80 for ; Thu, 11 Dec 2025 12:03:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f2e2ffae2sm5924073c88.9.2025.12.11.04.03.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Dec 2025 04:03:51 -0800 (PST) From: Hangxiang Ma Date: Thu, 11 Dec 2025 04:03:47 -0800 Subject: [PATCH v10 5/5] media: qcom: camss: vfe: Add support for VFE gen4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251211-add-support-for-camss-on-kaanapali-v10-5-39e8874dcd27@oss.qualcomm.com> References: <20251211-add-support-for-camss-on-kaanapali-v10-0-39e8874dcd27@oss.qualcomm.com> In-Reply-To: <20251211-add-support-for-camss-on-kaanapali-v10-0-39e8874dcd27@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Hangxiang Ma , Atiya Kailany X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=At7jHe9P c=1 sm=1 tr=0 ts=693ab32a cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=1ZGTSUkntXfq-hYXLBIA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-ORIG-GUID: 3CO9yoDzhNbx7zNo4I_B0eFOgpzJbaUG X-Proofpoint-GUID: 3CO9yoDzhNbx7zNo4I_B0eFOgpzJbaUG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjExMDA5MiBTYWx0ZWRfX4Eo1P3sag9LU dbjCd1IwzO1iQ28tGG5ikNSqYKiKFcNhSsmdV6tIp0O47wPBuvfHza+DEv2XM21nKCTV5UkPOI9 CFkS/uyidVC0UkS5vEW00lFjqUALRr4e9nKcNbYoPc7eGbzzLLxZwnFZz9UYIytslsM1YTw/51u lg8LRfmBlIzQSi4itTxJgdy7wAP3DOgyoEmkogiiORDfK8UCdxQEcduk30QhTfGnucL7SVaFsA7 lrIBcjr/5kOlsxoOtUpNPUOg+6+N8S5rpy0wKpijaLz0LFsX8rZt+0lx5HrogM92LiaJ7Smhclh c27VM9elkhaIrKUy9FiVU/dtmKZjQI3Wsx5yEo0OJq+Et/pVPPkmAmX2Uo2+/An0qhEzOc6kPi9 5XKk3j8ZnAiEDncv0HSm/NeP2lhp1w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-10_03,2025-12-09_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 phishscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512110092 Add Video Front End (VFE) version gen4 as found on the Kaanapali SoC. The FULL front end modules in Kaanapali camera subsystem are called TFEs (Thin Front End), however, retaining the name VFE at places to maintain consistency and avoid unnecessary code changes. This change limits the VFE output lines to 3 for now as constrained by the CAMSS driver framework. Kaanapali architecture requires for the REG_UPDATE and AUP_UPDATE to be issued after all of the CSID configuration has been done. Additionally, the number of AUP_UPDATEs should match the number of buffers enqueued to the write master while it's being enabled. Although the real time data from TFE goes through the RT_CAMNOC, we are required to enable both the camnoc_rt_axi and camnoc_nrt_axi clocks for the PDX_NOC, that follows both the RT and NRT NOCs in this architecture, to ensure that both of the latter are idle after reset. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/Makefile | 3 +- drivers/media/platform/qcom/camss/camss-vfe-gen4.c | 197 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-vfe.c | 9 +- drivers/media/platform/qcom/camss/camss-vfe.h | 2 + drivers/media/platform/qcom/camss/camss.c | 143 +++++++++++++++ 5 files changed, 351 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index 738d57214056..985464295b3f 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -22,8 +22,9 @@ qcom-camss-objs +=3D \ camss-vfe-340.o \ camss-vfe-480.o \ camss-vfe-680.o \ - camss-vfe-gen3.o \ camss-vfe-gen1.o \ + camss-vfe-gen3.o \ + camss-vfe-gen4.o \ camss-vfe.o \ camss-video.o \ camss-format.o \ diff --git a/drivers/media/platform/qcom/camss/camss-vfe-gen4.c b/drivers/m= edia/platform/qcom/camss/camss-vfe-gen4.c new file mode 100644 index 000000000000..d73d70898710 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-vfe-gen4.c + * + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen4 + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include + +#include "camss.h" +#include "camss-vfe.h" + +/* VFE-gen4 Bus Register Base Addresses */ +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000) + +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) + +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128) + +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) * 0x100) +#define WM_CFG_EN BIT(0) +#define WM_VIR_FRM_EN BIT(1) +#define WM_CFG_MODE BIT(16) +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n) * 0x100) +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n) * 0x100) +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50C + (n) * 0x100) +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n) * 0x100) +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF) +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n) * 0x100) + +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530 + (n) * 0= x100) +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534 + (n) * = 0x100) + +/* VFE lite has no such registers */ +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538 + (n) * 0x10= 0) +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53C + (n) * 0x1= 00) + +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560 + (n) * 0x10= 0) +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x564 + (n) = * 0x100) + +/* + * IFE write master client IDs + * + * VIDEO_FULL 0 + * VIDEO_DC4_Y 1 + * VIDEO_DC4_C 2 + * VIDEO_DC16_Y 3 + * VIDEO_DC16_C 4 + * DISPLAY_DS2_Y 5 + * DISPLAY_DS2_C 6 + * FD_Y 7 + * FD_C 8 + * PIXEL_RAW 9 + * STATS_AEC_BG 10 + * STATS_AEC_BHIST 11 + * STATS_TINTLESS_BG 12 + * STATS_AWB_BG 13 + * STATS_AWB_BFW 14 + * STATS_AF_BHIST 15 + * STATS_ALSC_BG 16 + * STATS_FLICKER_BAYERRS 17 + * STATS_TMC_BHIST 18 + * PDAF_0 19 + * PDAF_1 20 + * PDAF_2 21 + * PDAF_3 22 + * RDI0 23 + * RDI1 24 + * RDI2 25 + * RDI3 26 + * RDI4 27 + * + * IFE Lite write master client IDs + * + * RDI0 0 + * RDI1 1 + * RDI2 2 + * RDI3 3 + * GAMMA 4 + * STATES_BE 5 + */ +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n)) + +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *l= ine) +{ + struct v4l2_pix_format_mplane *pix =3D + &line->video_out.active_fmt.fmt.pix_mp; + + wm =3D RDI_WM(wm); + + /* no clock gating at bus input */ + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); + + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); + + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8, + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); + writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF), + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE, + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); + writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); + + /* no dropped frames, one irq per frame */ + if (!vfe_is_lite(vfe)) { + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); + } + + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); + + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm)); + writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm)); + + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) +{ + wm =3D RDI_WM(wm); + writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, + struct vfe_line *line) +{ + wm =3D RDI_WM(wm); + writel(addr >> 8, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); + + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr); +} + +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_i= d) +{ + int port_id =3D line_id; + + camss_reg_update(vfe->camss, vfe->id, port_id, false); +} + +static inline void vfe_reg_update_clear(struct vfe_device *vfe, + enum vfe_line_id line_id) +{ + int port_id =3D line_id; + + camss_reg_update(vfe->camss, vfe->id, port_id, true); +} + +static const struct camss_video_ops vfe_video_ops_gen4 =3D { + .queue_buffer =3D vfe_queue_buffer_v2, + .flush_buffers =3D vfe_flush_buffers, +}; + +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) +{ + vfe->video_ops =3D vfe_video_ops_gen4; +} + +static void vfe_global_reset(struct vfe_device *vfe) +{ + vfe_isr_reset_ack(vfe); +} + +static irqreturn_t vfe_isr(int irq, void *dev) +{ + /* nop */ + return IRQ_HANDLED; +} + +static int vfe_halt(struct vfe_device *vfe) +{ + /* rely on vfe_disable_output() to stop the VFE */ + return 0; +} + +const struct vfe_hw_ops vfe_ops_gen4 =3D { + .global_reset =3D vfe_global_reset, + .hw_version =3D vfe_hw_version, + .isr =3D vfe_isr, + .pm_domain_off =3D vfe_pm_domain_off, + .pm_domain_on =3D vfe_pm_domain_on, + .reg_update =3D vfe_reg_update, + .reg_update_clear =3D vfe_reg_update_clear, + .subdev_init =3D vfe_subdev_init, + .vfe_disable =3D vfe_disable, + .vfe_enable =3D vfe_enable_v2, + .vfe_halt =3D vfe_halt, + .vfe_wm_start =3D vfe_wm_start, + .vfe_wm_stop =3D vfe_wm_stop, + .vfe_buf_done =3D vfe_buf_done, + .vfe_wm_update =3D vfe_wm_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/= platform/qcom/camss/camss-vfe.c index 2753c2bb6c04..fd03e4fb5b5a 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -349,6 +349,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 = sink_code, case CAMSS_845: case CAMSS_8550: case CAMSS_8775P: + case CAMSS_KAANAPALI: case CAMSS_X1E80100: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: @@ -521,7 +522,8 @@ int vfe_enable_output_v2(struct vfe_line *line) =20 spin_lock_irqsave(&vfe->output_lock, flags); =20 - ops->reg_update_clear(vfe, line->id); + if (ops->reg_update_clear) + ops->reg_update_clear(vfe, line->id); =20 if (output->state > VFE_OUTPUT_RESERVED) { dev_err(vfe->camss->dev, @@ -548,7 +550,9 @@ int vfe_enable_output_v2(struct vfe_line *line) output->gen2.active_num++; ops->vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line); - ops->reg_update(vfe, line->id); + + if (!vfe->res->reg_update_after_csid_config) + ops->reg_update(vfe, line->id); } =20 spin_unlock_irqrestore(&vfe->output_lock, flags); @@ -1998,6 +2002,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) case CAMSS_845: case CAMSS_8550: case CAMSS_8775P: + case CAMSS_KAANAPALI: case CAMSS_X1E80100: ret =3D 16; break; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/= platform/qcom/camss/camss-vfe.h index 0300efdb1c46..30c0c560fc5a 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.h +++ b/drivers/media/platform/qcom/camss/camss-vfe.h @@ -133,6 +133,7 @@ struct vfe_isr_ops { =20 struct vfe_subdev_resources { bool is_lite; + bool reg_update_after_csid_config; u8 line_num; bool has_pd; char *pd_name; @@ -246,6 +247,7 @@ extern const struct vfe_hw_ops vfe_ops_340; extern const struct vfe_hw_ops vfe_ops_480; extern const struct vfe_hw_ops vfe_ops_680; extern const struct vfe_hw_ops vfe_ops_gen3; +extern const struct vfe_hw_ops vfe_ops_gen4; =20 int vfe_get(struct vfe_device *vfe); void vfe_put(struct vfe_device *vfe); diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index f79830e9f7c4..59698c7630e8 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -217,6 +217,147 @@ static const struct camss_subdev_resources csid_res_k= aanapali[] =3D { } }; =20 +/* In Kaanapali, CAMNOC requires all CAMNOC_RT_TFEX clocks + * to operate on any TFE Full. + */ +static const struct camss_subdev_resources vfe_res_kaanapali[] =3D { + /* VFE0 - TFE Full */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "vfe0_fast_ahb", "vfe0", + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe0" }, + .interrupt =3D { "vfe0" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "ife0", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE1 - TFE Full */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "vfe1_fast_ahb", "vfe1", + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe1" }, + .interrupt =3D { "vfe1" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "ife1", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE2 - TFE Full */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "vfe2_fast_ahb", "vfe2", + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe2" }, + .interrupt =3D { "vfe2" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "ife2", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE3 - IFE Lite */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite", + "camnoc_rt_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe_lite0" }, + .interrupt =3D { "vfe_lite0" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .reg_update_after_csid_config =3D true, + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE4 - IFE Lite */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite", + "camnoc_rt_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe_lite1" }, + .interrupt =3D { "vfe_lite1" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .reg_update_after_csid_config =3D true, + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, +}; + static const struct resources_icc icc_res_kaanapali[] =3D { { .name =3D "cam_ahb", @@ -4493,10 +4634,12 @@ static const struct camss_resources kaanapali_resou= rces =3D { .pd_name =3D "top", .csiphy_res =3D csiphy_res_kaanapali, .csid_res =3D csid_res_kaanapali, + .vfe_res =3D vfe_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), .csid_num =3D ARRAY_SIZE(csid_res_kaanapali), + .vfe_num =3D ARRAY_SIZE(vfe_res_kaanapali), }; =20 static const struct camss_resources msm8916_resources =3D { --=20 2.34.1