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Tue, 09 Dec 2025 21:25:16 -0800 (PST) From: Daniel Lezcano To: wbg@kernel.org, robh@kernel.org, conor+dt@kernel.org, krzk+dt@kernel.org Cc: s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org Subject: [PATCH v2 1/3] counters: Reorder the Makefile Date: Wed, 10 Dec 2025 06:24:45 +0100 Message-ID: <20251210052449.4154283-2-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251210052449.4154283-1-daniel.lezcano@linaro.org> References: <20251210052449.4154283-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The next changes provide a new driver. For the sake of clarity, reorder the Makefile alphabetically. No functional changes intended. Signed-off-by: Daniel Lezcano --- drivers/counter/Makefile | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile index fa3c1d08f706..40e644948e7a 100644 --- a/drivers/counter/Makefile +++ b/drivers/counter/Makefile @@ -6,14 +6,16 @@ obj-$(CONFIG_COUNTER) +=3D counter.o counter-y :=3D counter-core.o counter-sysfs.o counter-chrdev.o =20 -obj-$(CONFIG_I8254) +=3D i8254.o -obj-$(CONFIG_104_QUAD_8) +=3D 104-quad-8.o +obj-$(CONFIG_104_QUAD_8) +=3D 104-quad-8.o +obj-$(CONFIG_FTM_QUADDEC) +=3D ftm-quaddec.o +obj-$(CONFIG_I8254) +=3D i8254.o +obj-$(CONFIG_INTEL_QEP) +=3D intel-qep.o obj-$(CONFIG_INTERRUPT_CNT) +=3D interrupt-cnt.o -obj-$(CONFIG_RZ_MTU3_CNT) +=3D rz-mtu3-cnt.o -obj-$(CONFIG_STM32_TIMER_CNT) +=3D stm32-timer-cnt.o -obj-$(CONFIG_STM32_LPTIMER_CNT) +=3D stm32-lptimer-cnt.o -obj-$(CONFIG_TI_EQEP) +=3D ti-eqep.o -obj-$(CONFIG_FTM_QUADDEC) +=3D ftm-quaddec.o obj-$(CONFIG_MICROCHIP_TCB_CAPTURE) +=3D microchip-tcb-capture.o -obj-$(CONFIG_INTEL_QEP) +=3D intel-qep.o -obj-$(CONFIG_TI_ECAP_CAPTURE) +=3D ti-ecap-capture.o +obj-$(CONFIG_RZ_MTU3_CNT) +=3D rz-mtu3-cnt.o +obj-$(CONFIG_STM32_TIMER_CNT) +=3D stm32-timer-cnt.o +obj-$(CONFIG_STM32_LPTIMER_CNT) +=3D stm32-lptimer-cnt.o +obj-$(CONFIG_TI_ECAP_CAPTURE) +=3D ti-ecap-capture.o +obj-$(CONFIG_TI_EQEP) +=3D ti-eqep.o + + --=20 2.43.0 From nobody Sun Dec 14 06:40:14 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5E412FDC53 for ; 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charset="utf-8" Add the System Timer Module description found on the NXP s32 platform when it is used as a counter and the compatible for the s32g2 variant. Reviewed-by: Rob Herring (Arm) Signed-off-by: Daniel Lezcano --- .../bindings/counter/nxp,s32g2-stm-cnt.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/counter/nxp,s32g2-stm= -cnt.yaml diff --git a/Documentation/devicetree/bindings/counter/nxp,s32g2-stm-cnt.ya= ml b/Documentation/devicetree/bindings/counter/nxp,s32g2-stm-cnt.yaml new file mode 100644 index 000000000000..4d42996f5ad3 --- /dev/null +++ b/Documentation/devicetree/bindings/counter/nxp,s32g2-stm-cnt.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/counter/nxp,s32g2-stm-cnt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP System Timer Module (STM) + +maintainers: + - Daniel Lezcano + +description: + The System Timer Module supports commonly required system and application + software timing functions. STM includes a 32-bit count-up timer and four + 32-bit compare channels with a separate interrupt source for each channe= l. + The counter is driven by the STM module clock divided by an 8-bit presca= le + value. + +properties: + compatible: + oneOf: + - const: nxp,s32g2-stm-cnt + - items: + - const: nxp,s32g3-stm-cnt + - const: nxp,s32g2-stm-cnt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Counter clock + - description: Module clock + - description: Register clock + + clock-names: + items: + - const: counter + - const: module + - const: register + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + timer@4011c000 { + compatible =3D "nxp,s32g2-stm-cnt"; + reg =3D <0x4011c000 0x3000>; + interrupts =3D ; + clocks =3D <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names =3D "counter", "module", "register"; + }; --=20 2.43.0 From nobody Sun Dec 14 06:40:14 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E10033009C7 for ; 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Tue, 09 Dec 2025 21:25:21 -0800 (PST) Received: from mai.box.freepro.com ([2a05:6e02:1041:c10:4fde:b93c:87db:86e6]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47a7d3a75a3sm33485695e9.6.2025.12.09.21.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Dec 2025 21:25:21 -0800 (PST) From: Daniel Lezcano To: wbg@kernel.org, robh@kernel.org, conor+dt@kernel.org, krzk+dt@kernel.org Cc: s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, Maxime Coquelin , Alexandre Torgue , linux-stm32@st-md-mailman.stormreply.com (moderated list:ARM/STM32 ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH v2 3/3] counter: Add STM based counter Date: Wed, 10 Dec 2025 06:24:47 +0100 Message-ID: <20251210052449.4154283-4-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251210052449.4154283-1-daniel.lezcano@linaro.org> References: <20251210052449.4154283-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The NXP S32G2 automotive platform integrates four Cortex-A53 cores and three Cortex-M7 cores, along with a large number of timers and counters. These hardware blocks can be used as clocksources or clockevents, or as timestamp counters shared across the various subsystems running alongside the Linux kernel, such as firmware components. Their actual usage depends on the overall platform software design. In a Linux-based system, the kernel controls the counter, which is a read-only shared resource for the other subsystems. One of its primary purposes is to act as a common timestamp source for messages or traces, allowing correlation of events occurring in different operating system contexts. These changes introduce a basic counter driver that can start, stop, and reset the counter. It also handles overflow accounting and configures the prescaler value. Signed-off-by: Daniel Lezcano --- drivers/counter/Kconfig | 10 + drivers/counter/Makefile | 1 + drivers/counter/nxp-stm-cnt.c | 386 ++++++++++++++++++++++++++++++++++ 3 files changed, 397 insertions(+) create mode 100644 drivers/counter/nxp-stm-cnt.c diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig index d30d22dfe577..bf5b281f194c 100644 --- a/drivers/counter/Kconfig +++ b/drivers/counter/Kconfig @@ -90,6 +90,16 @@ config MICROCHIP_TCB_CAPTURE To compile this driver as a module, choose M here: the module will be called microchip-tcb-capture. =20 +config NXP_STM_CNT + tristate "NXP System Timer Module Counter driver" + depends on ARCH_S32 || COMPILE_TEST + help + Select this option to enable the NXP System Timer Module + Counter driver. + + To compile this driver as a module, choose M here: the + module will be called nxp_stm_cnt. + config RZ_MTU3_CNT tristate "Renesas RZ/G2L MTU3a counter driver" depends on RZ_MTU3 diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile index 40e644948e7a..196b3c216875 100644 --- a/drivers/counter/Makefile +++ b/drivers/counter/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_I8254) +=3D i8254.o obj-$(CONFIG_INTEL_QEP) +=3D intel-qep.o obj-$(CONFIG_INTERRUPT_CNT) +=3D interrupt-cnt.o obj-$(CONFIG_MICROCHIP_TCB_CAPTURE) +=3D microchip-tcb-capture.o +obj-$(CONFIG_NXP_STM_CNT) +=3D nxp-stm-cnt.o obj-$(CONFIG_RZ_MTU3_CNT) +=3D rz-mtu3-cnt.o obj-$(CONFIG_STM32_TIMER_CNT) +=3D stm32-timer-cnt.o obj-$(CONFIG_STM32_LPTIMER_CNT) +=3D stm32-lptimer-cnt.o diff --git a/drivers/counter/nxp-stm-cnt.c b/drivers/counter/nxp-stm-cnt.c new file mode 100644 index 000000000000..4b310dbbc76f --- /dev/null +++ b/drivers/counter/nxp-stm-cnt.c @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018,2021-2025 NXP + * Copyright 2025 Linaro Limited + * + * Author: Daniel Lezcano + * + * NXP S32G System Timer Module counters: + * + * STM supports commonly required system and application software + * timing functions. STM includes a 32-bit count-up timer and four + * 32-bit compare channels with a separate interrupt source for each + * channel. The timer is driven by the STM module clock divided by an + * 8-bit prescale value (1 to 256). It has ability to stop the timer + * in Debug mode + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define STM_CR(__base) (__base) +#define STM_CR_TEN BIT(0) +#define STM_CR_FRZ BIT(1) +#define STM_CR_CPS_MASK GENMASK(15, 8) + +#define STM_CCR0(__base) ((__base) + 0x10) +#define STM_CCR_CEN BIT(0) + +#define STM_CIR0(__base) ((__base) + 0x14) +#define STM_CIR_CIF BIT(0) + +#define STM_CMP0(__base) ((__base) + 0x18) + +#define STM_CNT(__base) ((__base) + 0x04) + +#define STM_ENABLE_MASK (STM_CR_FRZ | STM_CR_TEN) + +struct nxp_stm_cnt { + spinlock_t lock; + void __iomem *base; + u64 overflow; + u32 counter; + u8 prescaler; + bool is_started; +}; + +static void nxp_stm_cnt_enable(struct nxp_stm_cnt *stm_cnt) +{ + u32 reg; + + reg =3D readl(STM_CR(stm_cnt->base)); + + reg |=3D STM_ENABLE_MASK; + + writel(reg, STM_CR(stm_cnt->base)); +} + +static void nxp_stm_cnt_disable(struct nxp_stm_cnt *stm_cnt) +{ + u32 reg; + + reg =3D readl(STM_CR(stm_cnt->base)); + + reg &=3D ~STM_ENABLE_MASK; + + writel(reg, STM_CR(stm_cnt->base)); +} + +static void nxp_stm_cnt_ccr_disable(struct nxp_stm_cnt *stm_cnt) +{ + writel(0, STM_CCR0(stm_cnt->base)); +} + +static void nxp_stm_cnt_ccr_enable(struct nxp_stm_cnt *stm_cnt) +{ + writel(STM_CCR_CEN, STM_CCR0(stm_cnt->base)); +} + +static void nxp_stm_cnt_set_overflow(struct nxp_stm_cnt *stm_cnt) +{ + writel(UINT_MAX, STM_CMP0(stm_cnt->base)); +} + +static u32 nxp_stm_cnt_get_counter(struct nxp_stm_cnt *stm_cnt) +{ + return readl(STM_CNT(stm_cnt->base)); +} + +static void nxp_stm_cnt_set_counter(struct nxp_stm_cnt *stm_cnt, u32 count= er) +{ + writel(counter, STM_CNT(stm_cnt->base)); +} + +static void nxp_stm_cnt_set_prescaler(struct nxp_stm_cnt *stm_cnt, u8 pres= caler) +{ + u32 reg; + + reg =3D readl(STM_CR(stm_cnt->base)); + + FIELD_MODIFY(STM_CR_CPS_MASK, ®, prescaler); + + writel(reg, STM_CR(stm_cnt->base)); +} + +static u8 nxp_stm_cnt_get_prescaler(struct nxp_stm_cnt *stm_cnt) +{ + u32 reg =3D readl(STM_CR(stm_cnt->base)); + + return FIELD_GET(STM_CR_CPS_MASK, reg); +} + +static bool nxp_stm_cnt_is_started(struct nxp_stm_cnt *stm_cnt) +{ + u32 reg; + + reg =3D readl(STM_CR(stm_cnt->base)); + + return !!FIELD_GET(STM_CR_TEN, reg); +} + +static void nxp_stm_cnt_irq_ack(struct nxp_stm_cnt *stm_cnt) +{ + writel(STM_CIR_CIF, STM_CIR0(stm_cnt->base)); +} + +static irqreturn_t nxp_stm_cnt_irq(int irq, void *dev_id) +{ + struct nxp_stm_cnt *stm_cnt =3D dev_id; + + nxp_stm_cnt_irq_ack(stm_cnt); + + spin_lock(&stm_cnt->lock); + stm_cnt->overflow++; + spin_unlock(&stm_cnt->lock); + + return IRQ_HANDLED; +} + +static void nxp_stm_cnt_start(struct nxp_stm_cnt *stm_cnt) +{ + nxp_stm_cnt_ccr_enable(stm_cnt); + nxp_stm_cnt_set_overflow(stm_cnt); + nxp_stm_cnt_enable(stm_cnt); +} + +static void nxp_stm_cnt_stop(struct nxp_stm_cnt *stm_cnt) +{ + nxp_stm_cnt_disable(stm_cnt); + nxp_stm_cnt_irq_ack(stm_cnt); + nxp_stm_cnt_ccr_disable(stm_cnt); +} + +static int nxp_stm_cnt_overflow_read(struct counter_device *counter, + struct counter_count *count, u64 *val) +{ + struct nxp_stm_cnt *stm_cnt =3D counter_priv(counter); + unsigned long irqflags; + + spin_lock_irqsave(&stm_cnt->lock, irqflags); + *val =3D stm_cnt->overflow; + spin_unlock_irqrestore(&stm_cnt->lock, irqflags); + + return 0; +} + +static int nxp_stm_cnt_overflow_write(struct counter_device *counter, + struct counter_count *count, u64 val) +{ + struct nxp_stm_cnt *stm_cnt =3D counter_priv(counter); + unsigned long irqflags; + + spin_lock_irqsave(&stm_cnt->lock, irqflags); + stm_cnt->overflow =3D val; + spin_unlock_irqrestore(&stm_cnt->lock, irqflags); + + return 0; +} + +static int nxp_stm_cnt_reset_write(struct counter_device *counter, + struct counter_count *count, u8 val) +{ + struct nxp_stm_cnt *stm_cnt =3D counter_priv(counter); + + nxp_stm_cnt_set_counter(stm_cnt, 0); + spin_lock(&stm_cnt->lock); + stm_cnt->overflow =3D 0; + spin_unlock(&stm_cnt->lock); + + return 0; +} + +static int nxp_stm_cnt_prescaler_read(struct counter_device *counter, + struct counter_count *count, u8 *val) +{ + struct nxp_stm_cnt *stm_cnt =3D counter_priv(counter); + + *val =3D nxp_stm_cnt_get_prescaler(stm_cnt); + + return 0; +} + +static int nxp_stm_cnt_prescaler_write(struct counter_device *counter, + struct counter_count *count, u8 val) +{ + struct nxp_stm_cnt *stm_cnt =3D counter_priv(counter); + + nxp_stm_cnt_set_prescaler(stm_cnt, val); + + return 0; +} + +static int nxp_stm_cnt_count_enable_write(struct counter_device *counter, + struct counter_count *count, u8 enable) +{ + struct nxp_stm_cnt *stm_cnt =3D counter_priv(counter); + + if (enable) + nxp_stm_cnt_start(stm_cnt); + else + nxp_stm_cnt_stop(stm_cnt); + + return 0; +} + +static int nxp_stm_cnt_count_enable_read(struct counter_device *counter, + struct counter_count *count, u8 *enable) +{ + struct nxp_stm_cnt *stm_cnt =3D counter_priv(counter); + + *enable =3D nxp_stm_cnt_is_started(stm_cnt); + + return 0; +} + +static struct counter_comp stm_cnt_count_ext[] =3D { + COUNTER_COMP_COUNT_BOOL("reset", NULL, nxp_stm_cnt_reset_write), + COUNTER_COMP_COUNT_U8("prescaler", nxp_stm_cnt_prescaler_read, nxp_stm_cn= t_prescaler_write), + COUNTER_COMP_COUNT_U64("overflows", nxp_stm_cnt_overflow_read, nxp_stm_cn= t_overflow_write), + COUNTER_COMP_ENABLE(nxp_stm_cnt_count_enable_read, nxp_stm_cnt_count_enab= le_write), +}; + +static int nxp_stm_cnt_count_read(struct counter_device *dev, + struct counter_count *count, u64 *val) +{ + struct nxp_stm_cnt *stm_cnt =3D counter_priv(dev); + + *val =3D nxp_stm_cnt_get_counter(stm_cnt); + + return 0; +} + +static const struct counter_ops nxp_stm_cnt_counter_ops =3D { + .count_read =3D nxp_stm_cnt_count_read, +}; + +static struct counter_count nxp_stm_cnt_counts[] =3D { + { + .id =3D 0, + .name =3D "stm_cnt", + .ext =3D stm_cnt_count_ext, + .num_ext =3D ARRAY_SIZE(stm_cnt_count_ext), + }, +}; + +static int nxp_stm_cnt_suspend(struct device *dev) +{ + struct nxp_stm_cnt *stm_cnt =3D dev_get_drvdata(dev); + + stm_cnt->is_started =3D nxp_stm_cnt_is_started(stm_cnt); + + if (stm_cnt->is_started) { + nxp_stm_cnt_stop(stm_cnt); + stm_cnt->prescaler =3D nxp_stm_cnt_get_prescaler(stm_cnt); + stm_cnt->counter =3D nxp_stm_cnt_get_counter(stm_cnt); + } + + return 0; +} + +static int nxp_stm_cnt_resume(struct device *dev) +{ + struct nxp_stm_cnt *stm_cnt =3D dev_get_drvdata(dev); + + if (stm_cnt->is_started) { + nxp_stm_cnt_set_counter(stm_cnt, stm_cnt->counter); + nxp_stm_cnt_set_prescaler(stm_cnt, stm_cnt->prescaler); + nxp_stm_cnt_start(stm_cnt); + } + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(nxp_stm_cnt_pm_ops, nxp_stm_cnt_suspend, + nxp_stm_cnt_resume); + +static int nxp_stm_cnt_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + struct counter_device *counter; + struct nxp_stm_cnt *stm_cnt; + struct clk *clk; + void __iomem *base; + int irq, ret; + + base =3D devm_of_iomap(dev, np, 0, NULL); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), "Failed to iomap %pOFn\n", np); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return dev_err_probe(dev, irq, "Failed to get IRQ\n"); + + clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "Clock not found\n"); + + counter =3D devm_counter_alloc(dev, sizeof(*stm_cnt)); + if (!counter) + return -ENOMEM; + + stm_cnt =3D counter_priv(counter); + + stm_cnt->base =3D base; + stm_cnt->overflow =3D 0; + spin_lock_init(&stm_cnt->lock); + + counter->name =3D "stm_counter"; + counter->parent =3D &pdev->dev; + counter->ops =3D &nxp_stm_cnt_counter_ops; + counter->counts =3D nxp_stm_cnt_counts; + counter->num_counts =3D ARRAY_SIZE(nxp_stm_cnt_counts); + + ret =3D devm_request_irq(dev, irq, nxp_stm_cnt_irq, IRQF_TIMER | IRQF_NOB= ALANCING, + dev_name(&counter->dev), stm_cnt); + if (ret) + return dev_err_probe(dev, ret, "Unable to allocate interrupt line\n"); + + ret =3D devm_counter_add(dev, counter); + if (ret) + return dev_err_probe(dev, ret, "Failed to register counter\n"); + + platform_set_drvdata(pdev, stm_cnt); + + return 0; +} + +static void nxp_stm_cnt_remove(struct platform_device *pdev) +{ + struct nxp_stm_cnt *stm_cnt =3D platform_get_drvdata(pdev); + + if (nxp_stm_cnt_is_started(stm_cnt)) + nxp_stm_cnt_stop(stm_cnt); +} + +static const struct of_device_id nxp_stm_cnt_of_match[] =3D { + { .compatible =3D "nxp,s32g2-stm", }, + { } +}; +MODULE_DEVICE_TABLE(of, nxp_stm_cnt_of_match); + +static struct platform_driver nxp_stm_cnt_driver =3D { + .probe =3D nxp_stm_cnt_probe, + .remove =3D nxp_stm_cnt_remove, + .driver =3D { + .name =3D "nxp-stm-cnt", + .pm =3D pm_sleep_ptr(&nxp_stm_cnt_pm_ops), + .of_match_table =3D nxp_stm_cnt_of_match, + }, +}; +module_platform_driver(nxp_stm_cnt_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Daniel Lezcano"); +MODULE_DESCRIPTION("NXP System Timer Module counter driver"); +MODULE_IMPORT_NS("COUNTER"); --=20 2.43.0