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[153.246.134.248]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34a7000c984sm705234a91.6.2025.12.09.17.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Dec 2025 17:43:41 -0800 (PST) From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:25 +0900 Subject: [PATCH v4 1/9] dt-bindings: cpufreq: qcom-hw: document Milos CPUFREQ Hardware Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-sm7635-fp6-initial-v4-1-b05fddd8b45c@fairphone.com> References: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> In-Reply-To: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Thomas Gleixner , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765331010; l=1206; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=i2fJ3oSJhw/ySwSUDxCvlBN2veS0HqsGf63LfSGR3lY=; b=B6fM0qV+kskrVmWrQrdWrdJegC4lscc5t5rGLEmjxKdgwtQcYnqbU6yJ2+Vpsji8OYmgZzx3Q zOxdKXnTJnFALGIximQ+/5iJfIDmy7CiRbk3LF8mMSrBGYwC2Pw+dYY X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the CPUFREQ Hardware on the Milos SoC. Acked-by: Rob Herring (Arm) Acked-by: Viresh Kumar Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index 2d42fc3d8ef8..22eeaef14f55 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -35,6 +35,7 @@ properties: - description: v2 of CPUFREQ HW (EPSS) items: - enum: + - qcom,milos-cpufreq-epss - qcom,qcs8300-cpufreq-epss - qcom,qdu1000-cpufreq-epss - qcom,sa8255p-cpufreq-epss @@ -169,6 +170,7 @@ allOf: compatible: contains: enum: + - qcom,milos-cpufreq-epss - qcom,qcs8300-cpufreq-epss - qcom,sc7280-cpufreq-epss - qcom,sm8250-cpufreq-epss --=20 2.52.0 From nobody Tue Dec 16 21:27:18 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC0972343BE for ; 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[153.246.134.248]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34a7000c984sm705234a91.6.2025.12.09.17.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Dec 2025 17:43:46 -0800 (PST) From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:26 +0900 Subject: [PATCH v4 2/9] dt-bindings: crypto: qcom,prng: document Milos Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-sm7635-fp6-initial-v4-2-b05fddd8b45c@fairphone.com> References: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> In-Reply-To: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Thomas Gleixner , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765331010; l=921; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=xhCXot8hsmFt2DLcSKtSiw4vNTASFIkZ8KLq7GSl+P8=; b=uiHgbBzSh/cvk/RRJg9TS9wPZ3NQ27X91ICPemjxsmFWX4ZAsH6iHP01WgSN8lo1qZwesg/1h kEnQZwCIdjIAGmxpMUxDCitqwcrIBDFnbc/XAkCmlbc6L36YYyelCEc X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document Milos SoC compatible for the True Random Number Generator. Acked-by: Rob Herring (Arm) Reviewed-by: Bjorn Andersson Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Docu= mentation/devicetree/bindings/crypto/qcom,prng.yaml index 597441d94cf1..a9674e29144e 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml @@ -21,6 +21,7 @@ properties: - qcom,ipq5424-trng - qcom,ipq9574-trng - qcom,kaanapali-trng + - qcom,milos-trng - qcom,qcs615-trng - qcom,qcs8300-trng - qcom,sa8255p-trng --=20 2.52.0 From nobody Tue Dec 16 21:27:18 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B4611B4F0A for ; Wed, 10 Dec 2025 01:43:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Miller" , Vinod Koul , Thomas Gleixner , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765331010; l=902; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=64R8FCiMEBBuwRxLEqvZs1seDkt/c99ioBjBkZyRvHI=; b=mS3y+bW1cfkBNdq9xXjZsHMDg9KgFcK33rSnqdmmReA8YaNj9DNz+pBy+zfhLNlKKb8jKt0Dj 9TE9ZpjTAS1AbioGTNl4NiN0f/N3jL0VZ44slBPjbpXyAPv/MTK1/BH X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the Power Domain Controller on the Milos SoC. Acked-by: Rob Herring (Arm) Reviewed-by: Bjorn Andersson Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pd= c.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.ya= ml index 38d0c2d57dd6..0c80bf79c162 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -27,6 +27,7 @@ properties: items: - enum: - qcom,glymur-pdc + - qcom,milos-pdc - qcom,qcs615-pdc - qcom,qcs8300-pdc - qcom,qdu1000-pdc --=20 2.52.0 From nobody Tue Dec 16 21:27:18 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1ED9A1B87C0 for ; Wed, 10 Dec 2025 01:44:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[153.246.134.248]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34a7000c984sm705234a91.6.2025.12.09.17.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Dec 2025 17:43:57 -0800 (PST) From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:28 +0900 Subject: [PATCH v4 4/9] dt-bindings: arm: qcom: Add Milos and The Fairphone (Gen. 6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-sm7635-fp6-initial-v4-4-b05fddd8b45c@fairphone.com> References: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> In-Reply-To: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Thomas Gleixner , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765331010; l=824; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=Oj83634LuR0Sk6h6LV1CwwmH8/xA1oyqe0fNzBAzWv0=; b=EOx8pyQClbvxV0JmxPZtxhQaHpK3rsiOVVqGjOi/NNcSkhi4NB2293BkQWHtDObYSmVC6Frya Yl7gJHRuUU6DjCXJCKCgPEBBMffksNyiPLo6G0Z5+OwcMXj2haqKv0Y X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the Milos-based The Fairphone (Gen. 6) smartphone. Acked-by: Rob Herring (Arm) Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index d84bd3bca201..43d45fe95ed3 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -61,6 +61,11 @@ properties: - qcom,apq8084-sbc - const: qcom,apq8084 =20 + - items: + - enum: + - fairphone,fp6 + - const: qcom,milos + - items: - enum: - microsoft,dempsey --=20 2.52.0 From nobody Tue Dec 16 21:27:18 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBEFA22D7A9 for ; Wed, 10 Dec 2025 01:44:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765331047; cv=none; b=S0ov4KON+kMAKoy3et7++fP6RQzYJIqmX6p1k0ErBtJkoY/aITl7ipyti6YAD6cKw3tK9jdi4q+3VZyU3tE3F6Z2CE/I5nApqsCN7qHiglLAgdtfBjS7wDzqdN42Y6qwciuFz173lkpeE3GBhGG48L0GhMYa8gvNtXxZpdJgB9Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765331047; c=relaxed/simple; bh=XI4lYRmhSismtq3/ELTZaza6xilSunWDD+VaWKBs0/w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Otm+tlKGfJ6ciectPvaMJYLNE5Vz7S36bx2yo1YbERvgP1qKUQi2p9Csi08zjhzwCHbu6RGVVt+QOhAFD9MnbdjA3OX1vR0vSeyUxrFWvPSbNZ6TP3zOxnilbF2LxVAnCPa20CLbfw4zjvofhwnta6zJYURcTGYzJfiH6S6lhLI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=S4e6Gyd1; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="S4e6Gyd1" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-477a2ab455fso71840025e9.3 for ; Tue, 09 Dec 2025 17:44:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1765331044; x=1765935844; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Mt4WjG0W0q19OmnI9QBXdOvVdmS1ko/5DxfFU7nvRX4=; b=S4e6Gyd1SjUcxpDFEfKJlIA+HpmS+Kw1UEj2nssBJE5WPmtU9nROVck4ZHRGzDcfi7 E9YP1SkOaAbu0ZYBca0286w4cXEM6ZT7XgPQEKvMQ2Magnp8xDZvX1co7qSKtF5+Hr80 aOuouJcWlXrEtPtZJovgKkbmbTJ/7R9+3fPhyvVa+YiIy+WOKSdTK4j2+U/rzivbb0O4 SOlROWyKjyzZKIwYr3q2S5vwEkuykK/O19dQ14e0x8SKCRl6HFoRpLDPgsl7wRNptwwI 79G1iKkL2aqwyZrHyoXpCCVUYCS7GT01qMmi8KAiPaSt7Cb8LoahyKNUWRWzQeMsVNFZ O/oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765331044; x=1765935844; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Mt4WjG0W0q19OmnI9QBXdOvVdmS1ko/5DxfFU7nvRX4=; b=RGtfjZDfdbhy8coOIfMs44xWdADQJ4dlYlJXWKUEWdCVMPL1Lu1wRXlhU3Germ/H13 ZwtpYeLAkCRqt1wry1rJB9husuwtDUPlQZJmjszb9jSUDCuYB3LgX/PJxe1h3r1p21pf zTOkisBXSsK1EA4So91n8MeolZpMWhoiEwMxuTZizr7GlkI9pl/BmlKUegMSDi/48Gtj xef7p0ZcD7qeScT3oyB2uNUMI1XBdTFI7FBLC+6PBl4MJ3aTf5t9u8uuRl6+it2i+Ln3 77gTfximzq3ooVAkuvPRrY06RbxbGPfVvOPjsaUViw/uwQlWvaOShVkCv1yiEKtx4+si o5lw== X-Forwarded-Encrypted: i=1; AJvYcCUOi+dmJFHvPOKxu9OIQF+kFAYZ7iezlq94dSK/Tg2ejkdMSV1RbaX7ExniStbEJVqlhurzzNxXCCK6JgI=@vger.kernel.org X-Gm-Message-State: AOJu0Yxfp/pefdUzPPJsyg1l9nEGdaH0JUc8s/zGi5tBEKoeZ5klhkFa 5J0kkicvJh+7pUncz8si0VRyr5pPIjjw69DCTLAvPVKCUuWc4eZlnVx1D72fS0DjfIw= X-Gm-Gg: ASbGncs5zZ/OP/aMHYOYv29gpd5F0IJ/CU9pblHpjjfRcxxGe3c8qY4LZyNEp/HLWmV Z/PFPdCYe1pawZHQQwX3pXEwuC7IbSTEUiC4EO0h/i8+ZReld/4AF4BQyIyyiHoF2dqC+8gJMK9 /6511g+fYNW7L4Fse71jewIdXGIl/drXyUWMzYv19d9pD7gbGrtmeelQfR+E9mjXJr3timK9/V0 NaX9I5kSq92c0+ARA7EU4ZH9yeyDMEDYXMo7w0sXveuDNy9O3/M1KB1MTIqDLuQtYpYZZfjUPjs dtfzJoyDG30hfCJo3KiuCeSwjBl8Pt67YMtokhfNhvg7Qk3SyWlqa/5Y/6zPBjbY8ayXd+fPCPf NBrVbIcDS/0KSPhTvQ6nikwMz+dmf4a9ZA/5PD1sWbAD4NMtryrac8E/XQju7IB1KLbCHqjnlTi QafsXh8LQcQPvZcJRkIKveZUF5t81HmJ58XPwa8HN/PmJORp93Gg== X-Google-Smtp-Source: AGHT+IHWWLr0DhBakQkIgDcOAqKdZ1ODTrL388GNUGyz0XsgeupSnN05Wl5WF+21O8AY09feCkBJ5w== X-Received: by 2002:a05:600c:4e92:b0:477:9976:9e1a with SMTP id 5b1f17b1804b1-47a8374de44mr6993825e9.6.1765331044069; Tue, 09 Dec 2025 17:44:04 -0800 (PST) Received: from [10.200.8.8] (p99249-ipoefx.ipoe.ocn.ne.jp. [153.246.134.248]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34a7000c984sm705234a91.6.2025.12.09.17.43.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Dec 2025 17:44:03 -0800 (PST) From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:29 +0900 Subject: [PATCH v4 5/9] arm64: dts: qcom: pm8550vs: Disable different PMIC SIDs by default Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-sm7635-fp6-initial-v4-5-b05fddd8b45c@fairphone.com> References: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> In-Reply-To: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Thomas Gleixner , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Luca Weiss , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765331010; l=7651; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=XI4lYRmhSismtq3/ELTZaza6xilSunWDD+VaWKBs0/w=; b=xW7TGKmLG5/XAytZdY9wYxVnTZPxIyaVaKdBApDDl58eSio+hjSXifwQs/wQc1rZnEi7YhI3x 40XQJqkfnGrCbX0FeIS0jeKMwqVFphygxaevSgu4It6OZRS+b11rxL3 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Keep the different PMIC definitions in pm8550vs.dtsi disabled by default, and only enable them in boards explicitly. This allows to support boards better which only have pm8550vs_c, like the Milos/SM7635-based Fairphone (Gen. 6). Note: I assume that at least some of these devices with PM8550VS also don't have _c, _d, _e and _g, but this patch is keeping the resulting devicetree the same as before this change, disabling them on boards that don't actually have those is out of scope for this patch. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 8 ++++++++ arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 16 ++++++++++++= ++++ .../boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 16 ++++++++++++= ++++ 10 files changed, 152 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/q= com/pm8550vs.dtsi index 6426b431616b..7b5898c263ad 100644 --- a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi @@ -98,6 +98,8 @@ pm8550vs_c: pmic@2 { #address-cells =3D <1>; #size-cells =3D <0>; =20 + status =3D "disabled"; + pm8550vs_c_temp_alarm: temp-alarm@a00 { compatible =3D "qcom,spmi-temp-alarm"; reg =3D <0xa00>; @@ -122,6 +124,8 @@ pm8550vs_d: pmic@3 { #address-cells =3D <1>; #size-cells =3D <0>; =20 + status =3D "disabled"; + pm8550vs_d_temp_alarm: temp-alarm@a00 { compatible =3D "qcom,spmi-temp-alarm"; reg =3D <0xa00>; @@ -146,6 +150,8 @@ pm8550vs_e: pmic@4 { #address-cells =3D <1>; #size-cells =3D <0>; =20 + status =3D "disabled"; + pm8550vs_e_temp_alarm: temp-alarm@a00 { compatible =3D "qcom,spmi-temp-alarm"; reg =3D <0xa00>; @@ -170,6 +176,8 @@ pm8550vs_g: pmic@6 { #address-cells =3D <1>; #size-cells =3D <0>; =20 + status =3D "disabled"; + pm8550vs_g_temp_alarm: temp-alarm@a00 { compatible =3D "qcom,spmi-temp-alarm"; reg =3D <0xa00>; diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot= /dts/qcom/qcs8550-aim300.dtsi index e6ac529e6b72..e6ebb643203b 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -366,6 +366,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &sleep_clk { clock-frequency =3D <32764>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8550-hdk.dts index 599850c48494..ee13e6136a82 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1107,6 +1107,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &pon_pwrkey { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8550-mtp.dts index f430038bd402..94ed1c221856 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -789,6 +789,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &qupv3_id_0 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/= qcom/sm8550-qrd.dts index 05c98fe2c25b..3fd261377a0c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -1003,6 +1003,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &pon_pwrkey { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/b= oot/dts/qcom/sm8550-samsung-q5q.dts index b4ef40ae2cd9..81c02ee27fe9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -533,6 +533,22 @@ volume_up_n: volume-up-n-state { }; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &pon_pwrkey { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/= arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index d90dc7b37c4a..0e6ed6fce614 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -661,6 +661,22 @@ focus_n: focus-n-state { }; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &pm8550vs_g_gpios { cam_pwr_a_cs: cam-pwr-a-cs-state { pins =3D "gpio4"; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8650-hdk.dts index 5bf1af3308ce..eabc828c05b4 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1046,6 +1046,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &pon_pwrkey { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8650-mtp.dts index c67bbace2743..bb688a5d21c2 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -692,6 +692,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &qupv3_id_1 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/= qcom/sm8650-qrd.dts index b2feac61a89f..809fd6080a99 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1002,6 +1002,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; 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Miller" , Vinod Koul , Thomas Gleixner , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765331010; l=2033; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=LXmL+2Ud8K9B81a/ps47BQzEahaViMs6WOczoItxNxo=; b=nXqbJoE88R92aUN0quHB4SmewPu3iqg7cOV6P8Xk5EWQGIr5x8Sw2iBPFd8xc2GBDAuLQHyht cYVM3vbboUuB/aziF7usoPX2qgy83uOrX6m7O/kjcNBx0z+9e4mp0C2 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add a dts for the PMIC used e.g. with Milos SoC-based devices. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/pm7550.dtsi | 67 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm7550.dtsi b/arch/arm64/boot/dts/qco= m/pm7550.dtsi new file mode 100644 index 000000000000..b886c2397fe7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm7550.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss + */ + +#include +#include + +/ { + thermal-zones { + pm7550_thermal: pm7550-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&pm7550_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + /* + * Current Linux driver currently only supports up to + * 125=C2=B0C, should be updated to 145=C2=B0C once available. + */ + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pm7550: pmic@1 { + compatible =3D "qcom,pm7550", "qcom,spmi-pmic"; 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[153.246.134.248]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34a7000c984sm705234a91.6.2025.12.09.17.44.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Dec 2025 17:44:14 -0800 (PST) From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:31 +0900 Subject: [PATCH v4 7/9] arm64: dts: qcom: Add PMIV0104 PMIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-sm7635-fp6-initial-v4-7-b05fddd8b45c@fairphone.com> References: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> In-Reply-To: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Thomas Gleixner , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Luca Weiss , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765331010; l=2204; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=/3f0t4BZ1kTyyQ6hLM2p+V6L+8Ptg1VnPTNQ3bym2iE=; b=JHks+wlOz9dw6vQB0HKk0ZK3dlNr3cs4hUE/f7/+7JcDmpcSweHGNYwVniHnAzAT6bx7wHkUE qyEky8Ll/afB0lSIPzc346s8Fr8ngztmwAkkRKXRKhaL34MDBrehFKH X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add a dts for the PMIC used e.g. on devices with the Milos SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/pmiv0104.dtsi | 73 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmiv0104.dtsi b/arch/arm64/boot/dts/q= com/pmiv0104.dtsi new file mode 100644 index 000000000000..85ee8911d93e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmiv0104.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss + */ + +#include +#include + +/ { + thermal-zones { + pmiv0104-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&pmiv0104_temp_alarm>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + + trip2 { + /* + * Current Linux driver currently only supports up to + * 125=C2=B0C, should be updated to 145=C2=B0C once available. + */ + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@PMIV0104_SID { + compatible =3D "qcom,pmiv0104", "qcom,spmi-pmic"; + reg =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmiv0104_temp_alarm: temp-alarm@a00 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0xa00>; + interrupts =3D ; + #thermal-sensor-cells =3D <0>; + }; + + pmiv0104_gpios: gpio@8800 { + compatible =3D "qcom,pmiv0104-gpio", "qcom,spmi-gpio"; + reg =3D <0x8800>; + gpio-controller; + gpio-ranges =3D <&pmiv0104_gpios 0 0 10>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + pmiv0104_eusb2_repeater: phy@fd00 { + compatible =3D "qcom,pmiv0104-eusb2-repeater"; + reg =3D <0xfd00>; + #phy-cells =3D <0>; + }; + }; +}; --=20 2.52.0 From nobody Tue Dec 16 21:27:18 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D85C22A4E9 for ; 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[153.246.134.248]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34a7000c984sm705234a91.6.2025.12.09.17.44.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Dec 2025 17:44:20 -0800 (PST) From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:32 +0900 Subject: [PATCH v4 8/9] arm64: dts: qcom: Add initial Milos dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-sm7635-fp6-initial-v4-8-b05fddd8b45c@fairphone.com> References: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> In-Reply-To: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Thomas Gleixner , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765331010; l=66886; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=bb79thUYCFqGgwdaErH60yhukhkj/MoVJ0lMPxs7aWg=; b=LQDdTt6cUAo4smKhQoRYoGyM8EaJCBmMk4XdWyDlN4tMzcz2bWRNjsaOuf6kh2XEECwRRGRDv ch5DBJhdZ65Dc0DL8mDG7W61WiRusqrBYCLfETT/yfGKPoYdjUOH7SZ X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add a devicetree description for the Milos SoC, which is for example Snapdragon 7s Gen 3 (SM7635). Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/milos.dtsi | 2633 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 2633 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi new file mode 100644 index 000000000000..e1a51d43943f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -0,0 +1,2633 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <76800000>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32764>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x0>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x100>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + #cooling-cells =3D <2>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x200>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_2>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + #cooling-cells =3D <2>; + + l2_2: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x300>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_2>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + #cooling-cells =3D <2>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x400>; + + clocks =3D <&cpufreq_hw 1>; + + power-domains =3D <&cpu_pd4>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_4>; + capacity-dmips-mhz =3D <1670>; + dynamic-power-coefficient =3D <264>; + + qcom,freq-domain =3D <&cpufreq_hw 1>; + + #cooling-cells =3D <2>; + + l2_4: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x500>; + + clocks =3D <&cpufreq_hw 1>; + + power-domains =3D <&cpu_pd5>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_5>; + capacity-dmips-mhz =3D <1670>; + dynamic-power-coefficient =3D <264>; + + qcom,freq-domain =3D <&cpufreq_hw 1>; + + #cooling-cells =3D <2>; + + l2_5: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x600>; + + clocks =3D <&cpufreq_hw 1>; + + power-domains =3D <&cpu_pd6>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_6>; + capacity-dmips-mhz =3D <1670>; + dynamic-power-coefficient =3D <264>; + + qcom,freq-domain =3D <&cpufreq_hw 1>; + + #cooling-cells =3D <2>; + + l2_6: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x700>; + + clocks =3D <&cpufreq_hw 2>; + + power-domains =3D <&cpu_pd7>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_7>; + capacity-dmips-mhz =3D <1670>; + dynamic-power-coefficient =3D <287>; + + qcom,freq-domain =3D <&cpufreq_hw 2>; + + #cooling-cells =3D <2>; + + l2_7: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + silver_cpu_sleep_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "pc"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <250>; + exit-latency-us =3D <700>; + min-residency-us =3D <5200>; + local-timer-stop; + }; + + silver_cpu_sleep_1: cpu-sleep-0-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <550>; + exit-latency-us =3D <750>; + min-residency-us =3D <6700>; + local-timer-stop; + }; + + gold_cpu_sleep_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <400>; + exit-latency-us =3D <900>; + min-residency-us =3D <5511>; + local-timer-stop; + }; + + gold_cpu_sleep_1: cpu-sleep-1-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <600>; + exit-latency-us =3D <1300>; + min-residency-us =3D <8136>; + local-timer-stop; + }; + + gold_plus_cpu_sleep_0: cpu-sleep-2-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-plus-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <600>; + exit-latency-us =3D <1500>; + min-residency-us =3D <8551>; + local-timer-stop; + }; + }; + + domain-idle-states { + cluster_sleep_0: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000044>; + entry-latency-us =3D <750>; + exit-latency-us =3D <2350>; + min-residency-us =3D <9144>; + }; + + cluster_sleep_1: cluster-sleep-1 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41003344>; + entry-latency-us =3D <2800>; + exit-latency-us =3D <4400>; + min-residency-us =3D <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-milos", "qcom,scm"; + qcom,dload-mode =3D <&tcsr 0x19000>; + }; + }; + + clk_virt: interconnect-0 { + compatible =3D "qcom,milos-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible =3D "qcom,milos-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + memory@0 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0 0 0 0>; + }; + + pmu-a520 { + compatible =3D "arm,cortex-a520-pmu"; + interrupts =3D ; + }; + + pmu-a720 { + compatible =3D "arm,cortex-a720-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_plus_cpu_sleep_0>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_sleep_0>, <&cluster_sleep_1>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gunyah_hyp_mem: gunyah-hyp-region@80000000 { + reg =3D <0x0 0x80000000 0x0 0xe00000>; + no-map; + }; + + xbl_sc_mem: xbl-sc-region@81800000 { + reg =3D <0x0 0x81800000 0x0 0x40000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw-region@81840000 { + reg =3D <0x0 0x81840000 0x0 0x1c0000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog-region@81a00000 { + reg =3D <0x0 0x81a00000 0x0 0x40000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump-region@81a40000 { + reg =3D <0x0 0x81a40000 0x0 0x1c0000>; + no-map; + }; + + aop_image_mem: aop-image-region@81c00000 { + reg =3D <0x0 0x81c00000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-region@81c60000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: aop-config-region@81c80000 { + reg =3D <0x0 0x81c80000 0x0 0x20000>; + no-map; + }; + + tme_crash_dump_mem: tme-crash-dump-region@81ca0000 { + reg =3D <0x0 0x81ca0000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: tme-log-region@81ce0000 { + reg =3D <0x0 0x81ce0000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: uefi-log-region@81ce4000 { + reg =3D <0x0 0x81ce4000 0x0 0x10000>; + no-map; + }; + + chipinfo_mem: chipinfo-region@81cf4000 { + reg =3D <0x0 0x81cf4000 0x0 0x1000>; + no-map; + }; + + secdata_apss_mem: secdata-apss-region@81cff000 { + reg =3D <0x0 0x81cff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem-region@81d00000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x81d00000 0x0 0x200000>; + hwlocks =3D <&tcsr_mutex 3>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi-region@81f00000 { + reg =3D <0x0 0x81f00000 0x0 0x20000>; + no-map; + }; + + pvm_fw_mem: pvm-fw-region@824a0000 { + reg =3D <0x0 0x824a0000 0x0 0x100000>; + no-map; + }; + + hyp_mem_database_mem: hyp-mem-database-region@825a0000 { + reg =3D <0x0 0x825a0000 0x0 0x60000>; + no-map; + }; + + global_sync_mem: global-sync-region@82600000 { + reg =3D <0x0 0x82600000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat-region@82700000 { + reg =3D <0x0 0x82700000 0x0 0x100000>; + no-map; + }; + + qdss_apps_mem: qdss-apps-region@82800000 { + reg =3D <0x0 0x82800000 0x0 0x2000000>; + reusable; + }; + + mpss_mem: mpss-region@8ac00000 { + reg =3D <0x0 0x8ac00000 0x0 0xe600000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb-region@99200000 { + reg =3D <0x0 0x99200000 0x0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb-region@99280000 { + reg =3D <0x0 0x99280000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi-region@99300000 { + reg =3D <0x0 0x99300000 0x0 0x2800000>; + no-map; + }; + + wpss_mem: wpss-region@9bb00000 { + reg =3D <0x0 0x9bb00000 0x0 0x1900000>; + no-map; + }; + + video_mem: video-region@9d400000 { + reg =3D <0x0 0x9d400000 0x0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp-region@9db00000 { + reg =3D <0x0 0x9db00000 0x0 0xf00000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9ea00000 { + reg =3D <0x0 0x9ea00000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@9ea80000 { + reg =3D <0x0 0x9ea80000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@9ea90000 { + reg =3D <0x0 0x9ea90000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode-region@9ea9a000 { + reg =3D <0x0 0x9ea9a000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera-region@9eb00000 { + reg =3D <0x0 0x9eb00000 0x0 0x800000>; + no-map; + }; + + wlan_msa_mem: wlan-msa-region@a6400000 { + reg =3D <0x0 0xa6400000 0x0 0xc00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm-region@e0600000 { + reg =3D <0x0 0xe0600000 0x0 0x400000>; + no-map; + }; + + rmtfs_mem: rmtfs@e1f00000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0xe1f00000 0x0 0x600000>; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D ; + }; + + qtee_mem: qtee-region@e8900000 { + reg =3D <0x0 0xe8900000 0x0 0x500000>; + no-map; + }; + + tags_mem: tags-region@e8e00000 { + reg =3D <0x0 0xe8e00000 0x0 0x700000>; + no-map; + }; + + trusted_apps_mem: trusted-apps-region@e9500000 { + reg =3D <0x0 0xe9500000 0x0 0x1200000>; + no-map; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-cdsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <94>, <432>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + smp2p_ipa_out: ipa-ap-to-modem { + qcom,entry-name =3D "ipa"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_ipa_in: ipa-modem-to-ap { + qcom,entry-name =3D "ipa"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-wpss { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <617>, <616>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <13>; + + smp2p_wpss_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_wpss_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + smp2p_wlan_out: wlan-ap-to-wpss { + qcom,entry-name =3D "wlan"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_wlan_in: wlan-wpss-to-ap { + qcom,entry-name =3D "wlan"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0 0 0 0 0x10 0>; + ranges =3D <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,milos-gcc"; + reg =3D <0x0 0x00100000 0x0 0x1f4200>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, /* pcie_0_pipe_clk */ + <0>, /* pcie_1_pipe_clk */ + <0>, /* ufs_phy_rx_symbol_0_clk */ + <0>, /* ufs_phy_rx_symbol_1_clk */ + <0>, /* ufs_phy_tx_symbol_0_clk */ + <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */ + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + ipcc: mailbox@405000 { + compatible =3D "qcom,milos-ipcc", "qcom,ipcc"; + reg =3D <0x0 0x00405000 0x0 0x1000>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + + #mbox-cells =3D <2>; + }; + + gpi_dma1: dma-controller@800000 { + compatible =3D "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00800000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x3f>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x36 0x0>; + dma-coherent; + }; + + qupv3_id_1: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x008c0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core"; + + iommus =3D <&apps_smmu 0x23 0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + i2c7: i2c@880000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c7_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart11: serial@890000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart11_default>, <&qup_uart11_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + gpi_dma0: dma-controller@a00000 { + compatible =3D "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00a00000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x3e>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x576 0x0>; + dma-coherent; + }; + + qupv3_id_0: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core"; + + iommus =3D <&apps_smmu 0x563 0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + spi0: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c1: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c1_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c3_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart5: serial@a94000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart5_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + rng: rng@10c3000 { + compatible =3D "qcom,milos-trng", "qcom,trng"; + reg =3D <0x0 0x010c3000 0x0 0x1000>; + }; + + mmss_noc: interconnect@1400000 { + compatible =3D "qcom,milos-mmss-noc"; + reg =3D <0x0 0x01400000 0x0 0xdb800>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + cnoc_main: interconnect@1500000 { + compatible =3D "qcom,milos-cnoc-main"; + reg =3D <0x0 0x01500000 0x0 0x14400>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + cnoc_cfg: interconnect@1600000 { + compatible =3D "qcom,milos-cnoc-cfg"; + reg =3D <0x0 0x01600000 0x0 0x6e00>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,milos-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x40000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect@16c0000 { + compatible =3D "qcom,milos-pcie-anoc"; + reg =3D <0x0 0x016c0000 0x0 0x12400>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible =3D "qcom,milos-aggre1-noc"; + reg =3D <0x0 0x016e0000 0x0 0x16400>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,milos-aggre2-noc"; + reg =3D <0x0 0x01700000 0x0 0x1f400>; + #interconnect-cells =3D <2>; + clocks =3D <&rpmhcc RPMH_IPA_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + + #hwlock-cells =3D <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible =3D "qcom,milos-tcsr", "syscon"; + reg =3D <0x0 0x01fc0000 0x0 0xa0000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + remoteproc_adsp: remoteproc@3000000 { + compatible =3D "qcom,milos-adsp-pas"; + reg =3D <0x0 0x03000000 0x0 0x10000>; + + interrupts-extended =3D <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names =3D "lcx", + "lmx"; + + interconnects =3D <&lpass_ag_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region =3D <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_adsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "lpass"; + qcom,remote-pid =3D <2>; + }; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible =3D "qcom,milos-lpass-ag-noc"; + reg =3D <0x0 0x03c40000 0x0 0x17200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,milos-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,milos-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names =3D "hlos", + "bus", + "iface", + "ahb"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible =3D "qcom,milos-mpss-pas"; + reg =3D <0x0 0x04080000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; + power-domain-names =3D "cx", + "mss"; + + interconnects =3D <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region =3D <&mpss_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_modem_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "mpss"; + qcom,remote-pid =3D <1>; + }; + }; + + sdhc_2: mmc@8804000 { + compatible =3D "qcom,milos-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x08804000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "core", + "xo"; + + interconnects =3D <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "sdhc-ddr", + "cpu-sdhc"; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&sdhc2_opp_table>; + + iommus =3D <&apps_smmu 0x540 0>; + + bus-width =3D <4>; + + qcom,dll-config =3D <0x0007442c>; + qcom,ddr-config =3D <0x80040868>; + + dma-coherent; + + status =3D "disabled"; + + sdhc2_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + usb_1_hsphy: phy@88e3000 { + compatible =3D "qcom,milos-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg =3D <0x0 0x088e3000 0x0 0x154>; + #phy-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status =3D "disabled"; + }; + + remoteproc_wpss: remoteproc@8a00000 { + compatible =3D "qcom,milos-wpss-pas"; + reg =3D <0x0 0x08a00000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 579 IRQ_TYPE_EDGE_RISING 0>, + <&smp2p_wpss_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names =3D "cx", + "mx"; + + memory-region =3D <&wpss_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_wpss_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "wpss"; + qcom,remote-pid =3D <13>; + }; + }; + + usb_1: usb@a600000 { + compatible =3D "qcom,milos-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a600000 0x0 0xfc000>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 0>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + iommus =3D <&apps_smmu 0x40 0x0>; + power-domains =3D <&gcc USB30_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + phys =3D <&usb_1_hsphy>; + phy-names =3D "usb2-phy"; + + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,has-lpm-erratum; + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,parkmode-disable-ss-quirk; + tx-fifo-resize; + dma-coherent; + usb-role-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + }; + }; + + videocc: clock-controller@aaf0000 { + compatible =3D "qcom,milos-videocc"; + reg =3D <0x0 0x0aaf0000 0x0 0x10000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + camcc: clock-controller@adb0000 { + compatible =3D "qcom,milos-camcc"; + reg =3D <0x0 0x0adb0000 0x0 0x40000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + dispcc: clock-controller@af00000 { + compatible =3D "qcom,milos-dispcc"; + reg =3D <0x0 0x0af00000 0x0 0x20000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <0>, /* dsi0_phy_pll_out_byteclk */ + <0>, /* dsi0_phy_pll_out_dsiclk */ + <0>, /* dp0_phy_pll_link_clk */ + <0>; /* dp0_phy_pll_vco_div_clk */ + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,milos-pdc", "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x30000>, + <0x0 0x174000f0 0x0 0x64>; + interrupt-parent =3D <&intc>; + + qcom,pdc-ranges =3D <0 480 40>, <40 140 11>, <51 527 47>, + <98 609 31>, <129 63 1>, <130 716 12>, + <142 251 5>; + + #interrupt-cells =3D <2>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c228000 { + compatible =3D "qcom,milos-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c228000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + + interrupts-extended =3D <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <15>; + + #thermal-sensor-cells =3D <1>; + }; + + tsens1: thermal-sensor@c229000 { + compatible =3D "qcom,milos-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c229000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + + interrupts-extended =3D <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <14>; + + #thermal-sensor-cells =3D <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible =3D "qcom,milos-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0x0 0x0c300000 0x0 0x400>; + + interrupt-parent =3D <&ipcc>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_= QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells =3D <0>; + }; + + sram@c3f0000 { + compatible =3D "qcom,rpmh-stats"; + reg =3D <0x0 0x0c3f0000 0x0 0x400>; + }; + + spmi_bus: spmi@c400000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c500000 0x0 0x400000>, + <0x0 0x0c440000 0x0 0x80000>, + <0x0 0x0c4c0000 0x0 0x10000>, + <0x0 0x0c42d000 0x0 0x4000>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "periph_irq"; + + qcom,ee =3D <0>; + qcom,channel =3D <0>; + qcom,bus-id =3D <0>; + + interrupt-controller; + #interrupt-cells =3D <4>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,milos-tlmm"; + reg =3D <0x0 0x0f100000 0x0 0x300000>; + + interrupts =3D ; + + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + gpio-ranges =3D <&tlmm 0 0 168>; + + wakeup-parent =3D <&pdc>; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio4", "gpio5"; + function =3D "qup0_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio15", "gpio16"; + function =3D "qup0_se3"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio32", "gpio33"; + function =3D "qup1_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins =3D "gpio3"; + function =3D "qup0_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio0", "gpio1", "gpio2"; + function =3D "qup0_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + /* TX, RX */ + pins =3D "gpio25", "gpio26"; + function =3D "qup0_se5"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart11_default: qup-uart11-default-state { + /* TX, RX */ + pins =3D "gpio50", "gpio51"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart11_cts_rts: qup-uart11-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio48", "gpio49"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins =3D "gpio62"; + function =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio61"; + function =3D "sdc2_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio58", "gpio57", "gpio35", "gpio34"; + function =3D "sdc2_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins =3D "gpio62"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio61"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio58", "gpio57", "gpio35", "gpio34"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,milos-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x15000000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-coherent; + }; + + intc: interrupt-controller@17100000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17100000 0x0 0x10000>, + <0x0 0x17180000 0x0 0x200000>; + + interrupts =3D ; + + #interrupt-cells =3D <4>; + interrupt-controller; + + #redistributor-regions =3D <1>; + redistributor-stride =3D <0 0x40000>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + + gic_its: msi-controller@17140000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x17140000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + }; + + timer@17420000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17420000 0x0 0x1000>; + + ranges =3D <0 0 0 0x20000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@17421000 { + reg =3D <0x17421000 0x1000>, + <0x17422000 0x1000>; + + interrupts =3D , + ; + + frame-number =3D <0>; + }; + + frame@17423000 { + reg =3D <0x17423000 0x1000>; + + interrupts =3D ; + + frame-number =3D <1>; + + status =3D "disabled"; + }; + + frame@17425000 { + reg =3D <0x17425000 0x1000>; + + interrupts =3D ; + + frame-number =3D <2>; + + status =3D "disabled"; + }; + + frame@17427000 { + reg =3D <0x17427000 0x1000>; + + interrupts =3D ; + + frame-number =3D <3>; + + status =3D "disabled"; + }; + + frame@17429000 { + reg =3D <0x17429000 0x1000>; + + interrupts =3D ; + + frame-number =3D <4>; + + status =3D "disabled"; + }; + + frame@1742b000 { + reg =3D <0x1742b000 0x1000>; + + interrupts =3D ; + + frame-number =3D <5>; + + status =3D "disabled"; + }; + + frame@1742d000 { + reg =3D <0x1742d000 0x1000>; + + interrupts =3D ; + + frame-number =3D <6>; + + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + + interrupts =3D , + , + ; + + power-domains =3D <&cluster_pd>; + + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , , + , ; + + label =3D "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,milos-rpmh-clk"; + + clocks =3D <&xo_board>; + clock-names =3D "xo"; + + #clock-cells =3D <1>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,milos-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level =3D ; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible =3D "qcom,milos-cpufreq-epss", "qcom,cpufreq-epss"; + reg =3D <0x0 0x17d91000 0x0 0x1000>, + <0x0 0x17d92000 0x0 0x1000>, + <0x0 0x17d93000 0x0 0x1000>; + reg-names =3D "freq-domain0", + "freq-domain1", + "freq-domain2"; + + interrupts =3D , + , + ; + interrupt-names =3D "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPLL0>; + clock-names =3D "xo", + "alternate"; + + #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; + }; + + gem_noc: interconnect@24100000 { + compatible =3D "qcom,milos-gem-noc"; + reg =3D <0x0 0x24100000 0x0 0xff080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + nsp_noc: interconnect@320c0000 { + compatible =3D "qcom,milos-nsp-noc"; + reg =3D <0x0 0x320c0000 0x0 0xe080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible =3D "qcom,milos-cdsp-pas"; + reg =3D <0x0 0x32300000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names =3D "cx", + "mx"; + + interconnects =3D <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region =3D <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_cdsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "cdsp"; + qcom,remote-pid =3D <5>; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + thermal-sensors =3D <&tsens0 0>; + + trips { + aoss0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + aoss0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors =3D <&tsens0 1>; + + trips { + cpuss0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors =3D <&tsens0 2>; + + trips { + cpuss1-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu4-left-thermal { + thermal-sensors =3D <&tsens0 3>; + + trips { + cpu4-left-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu4-right-thermal { + thermal-sensors =3D <&tsens0 4>; + + trips { + cpu4-right-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu5-left-thermal { + thermal-sensors =3D <&tsens0 5>; + + trips { + cpu5-left-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu5-right-thermal { + thermal-sensors =3D <&tsens0 6>; + + trips { + cpu5-right-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu6-left-thermal { + thermal-sensors =3D <&tsens0 7>; + + trips { + cpu6-left-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu6-right-thermal { + thermal-sensors =3D <&tsens0 8>; + + trips { + cpu6-right-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-left-thermal { + thermal-sensors =3D <&tsens0 9>; + + trips { + cpu7-left-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-right-thermal { + thermal-sensors =3D <&tsens0 10>; + + trips { + cpu7-right-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu0-thermal { + thermal-sensors =3D <&tsens0 11>; + + trips { + cpu0-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu1-thermal { + thermal-sensors =3D <&tsens0 12>; + + trips { + cpu1-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu2-thermal { + thermal-sensors =3D <&tsens0 13>; + + trips { + cpu2-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu3-thermal { + thermal-sensors =3D <&tsens0 14>; + + trips { + cpu3-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss1-thermal { + thermal-sensors =3D <&tsens1 0>; + + trips { + aoss1-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + aoss1-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphvx0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 1>; + + trips { + nsphvx0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + nsphvx0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 2>; + + trips { + nsphmx1-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + nsphmx1-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 3>; + + trips { + nsphmx0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + nsphmx0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 4>; + + trips { + gpu0_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + gpuss0-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 5>; + + trips { + gpu1_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + gpuss1-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors =3D <&tsens1 7>; + + trips { + video-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + video-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 8>; + + trips { + ddr-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + ddr-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + camera0-thermal { + thermal-sensors =3D <&tsens1 9>; + + trips { + camera0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + camera0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&tsens1 10>; + + trips { + modem0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + modem0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&tsens1 11>; + + trips { + modem1-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + modem1-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&tsens1 12>; + + trips { + modem2-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + modem2-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + modem3-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&tsens1 13>; + + trips { + modem3-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + modem3-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; 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[153.246.134.248]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34a7000c984sm705234a91.6.2025.12.09.17.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Dec 2025 17:44:25 -0800 (PST) From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:33 +0900 Subject: [PATCH v4 9/9] arm64: dts: qcom: Add The Fairphone (Gen. 6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-sm7635-fp6-initial-v4-9-b05fddd8b45c@fairphone.com> References: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> In-Reply-To: <20251210-sm7635-fp6-initial-v4-0-b05fddd8b45c@fairphone.com> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Thomas Gleixner , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765331010; l=21055; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=dQvpXyrMYNrV6758bacgoGHBnAGoyVS3u4Zw6ofPsuc=; b=rHbfp4lTxD5+8kacAPdKXOlGPj+PIHoYhyMjyOOvV1IdEiEdpkHWlSSZxOR88UTt7Qz/U7gTm rk3KrJ14rP4Bbn5/CKocqSe8JT0LomUgQxqLr3mWG17e4jK5AmqCLmW X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based on the Milos/SM7635 SoC. Supported functionality as of this initial submission: * Debug UART * Regulators (PM7550, PM8550VS, PMR735B, PM8008) * Remoteprocs (ADSP, CDSP, MPSS, WPSS) * Power Button, Volume Keys, Switch * PMIC-GLINK (Charger, Fuel gauge, USB-C mode switching) * Camera flash/torch LED * SD card * USB Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 790 +++++++++++++++++++= ++++ 2 files changed, 791 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 6f34d5ed331c..4b061124d7af 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -37,6 +37,7 @@ lemans-evk-camera-dtbs :=3D lemans-evk.dtb lemans-evk-cam= era.dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-camera-csi1-imx577.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-camera.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/= boot/dts/qcom/milos-fairphone-fp6.dts new file mode 100644 index 000000000000..52895dd9e4fa --- /dev/null +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -0,0 +1,790 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss + */ + +/dts-v1/; + +#define PMIV0104_SID 7 + +#include +#include +#include +#include "milos.dtsi" +#include "pm7550.dtsi" +#include "pm8550vs.dtsi" +#include "pmiv0104.dtsi" /* PMIV0108 */ +#include "pmk8550.dtsi" /* PMK7635 */ +#include "pmr735b.dtsi" + +/ { + model =3D "The Fairphone (Gen. 6)"; + compatible =3D "fairphone,fp6", "qcom,milos"; + chassis-type =3D "handset"; + + aliases { + serial0 =3D &uart5; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&volume_up_default>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + gpios =3D <&pm7550_gpios 6 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + + switch { + label =3D "Switch"; + gpios =3D <&tlmm 107 GPIO_ACTIVE_HIGH>; + linux,input-type =3D ; + linux,code =3D ; + }; + }; + + pmic-glink { + compatible =3D "qcom,milos-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + orientation-gpios =3D <&tlmm 131 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_hs>; + }; + }; + }; + }; + }; + + vreg_ff_afvdd_2p8: regulator-ff-afvdd-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "ff_afvdd_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 93 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_bob>; + }; + + vreg_uw_afvdd_2p8: regulator-uw-afvdd-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "uw_afvdd_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_bob>; + }; + + vreg_uw_dvdd: regulator-uw-dvdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "uw_dvdd"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_s1b>; + }; + + vreg_ois_avdd0_1p8: regulator-ois-avdd0-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "ois_avdd0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_bob>; + }; + + vreg_ois_vdd: regulator-ois-vdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "ois_vdd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vph_pwr>; + }; + + vreg_oled_dvdd_1p2: regulator-oled-dvdd-1p2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "oled_dvdd_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + + gpio =3D <&tlmm 54 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_s2b>; + + regulator-boot-on; + }; + + vreg_s1j: regulator-pm3001a-s1j { + compatible =3D "regulator-fixed"; + regulator-name =3D "pm3001a_s1j"; + regulator-min-microvolt =3D <2200000>; + regulator-max-microvolt =3D <2200000>; + startup-delay-us =3D <1000>; + + gpio =3D <&pmr735b_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vph_pwr>; + + pinctrl-0 =3D <&s1j_enable_default>; + pinctrl-names =3D "default"; + }; + + vreg_vtof_ldo_3p3: regulator-vtof-ldo-3p3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vtof_ldo_3p3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 76 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vph_pwr>; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + thermal-zones { + pm8008-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pm8008>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm7550-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s1b>; + vdd-l2-l3-supply =3D <&vreg_s3b>; + vdd-l4-l5-supply =3D <&vreg_s2b>; + vdd-l6-supply =3D <&vreg_s2b>; + vdd-l7-supply =3D <&vreg_s1b>; + vdd-l8-supply =3D <&vreg_s1b>; + vdd-l9-l10-supply =3D <&vreg_s1b>; + vdd-l11-supply =3D <&vreg_s1b>; + vdd-l12-l14-supply =3D <&vreg_bob>; + vdd-l13-l16-supply =3D <&vreg_bob>; + vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply =3D <&vreg_bob>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "b"; + + vreg_s1b: smps1 { + regulator-name =3D "vreg_s1b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2080000>; + regulator-initial-mode =3D ; + }; + + vreg_s2b: smps2 { + regulator-name =3D "vreg_s2b"; + regulator-min-microvolt =3D <1256000>; + regulator-max-microvolt =3D <1408000>; + regulator-initial-mode =3D ; + }; + + vreg_s3b: smps3 { + regulator-name =3D "vreg_s3b"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <1040000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b: ldo2 { + regulator-name =3D "vreg_l2b"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l3b: ldo3 { + regulator-name =3D "vreg_l3b"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l4b: ldo4 { + regulator-name =3D "vreg_l4b"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l5b: ldo5 { + regulator-name =3D "vreg_l5b"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l7b: ldo7 { + regulator-name =3D "vreg_l7b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b: ldo8 { + regulator-name =3D "vreg_l8b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b: ldo9 { + regulator-name =3D "vreg_l9b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l10b: ldo10 { + regulator-name =3D "vreg_l10b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l11b: ldo11 { + regulator-name =3D "vreg_l11b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b: ldo12 { + regulator-name =3D "vreg_l12b"; + /* + * Skip voltage voting for UFS VCC. + */ + regulator-initial-mode =3D ; + }; + + vreg_l13b: ldo13 { + regulator-name =3D "vreg_l13b"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l14b: ldo14 { + regulator-name =3D "vreg_l14b"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b: ldo15 { + regulator-name =3D "vreg_l15b"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + }; + + vreg_l16b: ldo16 { + regulator-name =3D "vreg_l16b"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b: ldo17 { + regulator-name =3D "vreg_l17b"; + regulator-min-microvolt =3D <3104000>; + regulator-max-microvolt =3D <3104000>; + regulator-initial-mode =3D ; + }; + + vreg_l18b: ldo18 { + regulator-name =3D "vreg_l18b"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l19b: ldo19 { + regulator-name =3D "vreg_l19b"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + }; + + vreg_l20b: ldo20 { + regulator-name =3D "vreg_l20b"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l21b: ldo21 { + regulator-name =3D "vreg_l21b"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l22b: ldo22 { + regulator-name =3D "vreg_l22b"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + }; + + vreg_l23b: ldo23 { + regulator-name =3D "vreg_l23b"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_bob: bob { + regulator-name =3D "vreg_bob"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s3b>; + vdd-l3-supply =3D <&vreg_s3b>; + + qcom,pmic-id =3D "c"; + + vreg_l2c: ldo2 { + regulator-name =3D "vreg_l2c"; + regulator-min-microvolt =3D <320000>; + regulator-max-microvolt =3D <650000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmr735b-rpmh-regulators"; + + vdd-l1-l2-supply=3D <&vreg_s3b>; + vdd-l3-supply=3D <&vreg_s3b>; + vdd-l4-supply=3D <&vreg_s1b>; + vdd-l5-supply=3D <&vreg_s2b>; + vdd-l6-supply=3D <&vreg_s2b>; + vdd-l7-l8-supply=3D <&vreg_s2b>; + vdd-l9-supply=3D <&vreg_s3b>; + vdd-l10-supply=3D <&vreg_s1b>; + vdd-l11-supply=3D <&vreg_s3b>; + vdd-l12-supply=3D <&vreg_s3b>; + + qcom,pmic-id =3D "f"; + + vreg_l1f: ldo1 { + regulator-name =3D "vreg_l1f"; + regulator-min-microvolt =3D <852000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f: ldo2 { + regulator-name =3D "vreg_l2f"; + regulator-min-microvolt =3D <751000>; + regulator-max-microvolt =3D <824000>; + regulator-initial-mode =3D ; + }; + + vreg_l3f: ldo3 { + regulator-name =3D "vreg_l3f"; + regulator-min-microvolt =3D <650000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + + vreg_l4f: ldo4 { + regulator-name =3D "vreg_l4f"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <1950000>; + regulator-initial-mode =3D ; + }; + + vreg_l5f: ldo5 { + regulator-name =3D "vreg_l5f"; + regulator-min-microvolt =3D <1140000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + }; + + vreg_l6f: ldo6 { + regulator-name =3D "vreg_l6f"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l7f: ldo7 { + regulator-name =3D "vreg_l7f"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D ; + }; + + vreg_l8f: ldo8 { + regulator-name =3D "vreg_l8f"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1320000>; + regulator-initial-mode =3D ; + }; + + vreg_l9f: ldo9 { + regulator-name =3D "vreg_l9f"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + }; + + vreg_l10f: ldo10 { + regulator-name =3D "vreg_l10f"; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l11f: ldo11 { + regulator-name =3D "vreg_l11f"; + regulator-min-microvolt =3D <320000>; + regulator-max-microvolt =3D <864000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&gcc { + protected-clocks =3D , , + , , + , , + , , + , , + , ; +}; + +&i2c1 { + /* Samsung NFC @ 0x27 */ + + status =3D "okay"; +}; + +&i2c3 { + /* AW88261FCR amplifier (top) @ 0x34 */ + /* AW88261FCR amplifier (bottom) @ 0x35 */ + + status =3D "okay"; +}; + +&i2c7 { + status =3D "okay"; + + pm8008: pmic@8 { + compatible =3D "qcom,pm8008"; + reg =3D <0x8>; + + interrupts-extended =3D <&tlmm 125 IRQ_TYPE_EDGE_RISING>; + reset-gpios =3D <&pmr735b_gpios 3 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply =3D <&vreg_s2b>; + vdd-l3-l4-supply =3D <&vreg_bob>; + vdd-l5-supply =3D <&vreg_bob>; + vdd-l6-supply =3D <&vreg_s1b>; + vdd-l7-supply =3D <&vreg_bob>; + + pinctrl-0 =3D <&pm8008_int_default>, <&pm8008_reset_n_default>; + pinctrl-names =3D "default"; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + #thermal-sensor-cells =3D <0>; + + regulators { + vreg_l1p: ldo1 { + regulator-name =3D "vreg_l1p"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1200000>; + }; + + vreg_l2p: ldo2 { + regulator-name =3D "vreg_l2p"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1144000>; + }; + + vreg_l3p: ldo3 { + regulator-name =3D "vreg_l3p"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3000000>; + }; + + vreg_l4p: ldo4 { + regulator-name =3D "vreg_l4p"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <2900000>; + }; + + vreg_l5p: ldo5 { + regulator-name =3D "vreg_l5p"; + regulator-min-microvolt =3D <2704000>; + regulator-max-microvolt =3D <2900000>; + }; + + vreg_l6p: ldo6 { + regulator-name =3D "vreg_l6p"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <1896000>; + }; + + vreg_l7p: ldo7 { + regulator-name =3D "vreg_l7p"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3400000>; + }; + }; + }; + + /* VL53L3 ToF @ 0x29 */ + /* AW86938FCR vibrator @ 0x5a */ +}; + +&pm8550vs_c { + status =3D "okay"; +}; + +&pmiv0104_eusb2_repeater { + vdd18-supply =3D <&vreg_l7b>; + vdd3-supply =3D <&vreg_l17b>; + + qcom,tune-res-fsdif =3D /bits/ 8 <0x5>; + qcom,tune-usb2-amplitude =3D /bits/ 8 <0x8>; + qcom,tune-usb2-disc-thres =3D /bits/ 8 <0x7>; + qcom,tune-usb2-preem =3D /bits/ 8 <0x6>; +}; + +&pmr735b_gpios { + s1j_enable_default: s1j-enable-default-state { + pins =3D "gpio1"; + function =3D PMIC_GPIO_FUNC_NORMAL; + power-source =3D <0>; + bias-disable; + output-low; + }; + + pm8008_reset_n_default: pm8008-reset-n-default-state { + pins =3D "gpio3"; + function =3D PMIC_GPIO_FUNC_NORMAL; + bias-pull-down; + }; +}; + +&pm7550_gpios { + volume_up_default: volume-up-default-state { + pins =3D "gpio6"; + function =3D PMIC_GPIO_FUNC_NORMAL; + power-source =3D <1>; + bias-pull-up; + }; +}; + +&pm7550_flash { + status =3D "okay"; + + led-0 { + function =3D LED_FUNCTION_FLASH; + color =3D ; + led-sources =3D <1>, <4>; + led-max-microamp =3D <350000>; + flash-max-microamp =3D <1500000>; + flash-max-timeout-us =3D <400000>; + }; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/milos/fairphone/fp6/adsp.mbn", + "qcom/milos/fairphone/fp6/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/milos/fairphone/fp6/cdsp.mbn", + "qcom/milos/fairphone/fp6/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_mpss { + firmware-name =3D "qcom/milos/fairphone/fp6/modem.mbn"; + + status =3D "okay"; +}; + +&remoteproc_wpss { + firmware-name =3D "qcom/milos/fairphone/fp6/wpss.mbn"; + + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 65 GPIO_ACTIVE_HIGH>; + + vmmc-supply =3D <&vreg_l13b>; + vqmmc-supply =3D <&vreg_l23b>; + no-sdio; + no-mmc; + + pinctrl-0 =3D <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 =3D <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; +}; + +&spi0 { + /* Eswin EPH8621 touchscreen @ 0 */ +}; + +&tlmm { + gpio-reserved-ranges =3D <8 4>, /* Fingerprint SPI */ + <13 1>, /* NC */ + <63 2>; /* WLAN UART */ + + sdc2_card_det_n: sdc2-card-det-state { + pins =3D "gpio65"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + pm8008_int_default: pm8008-int-default-state { + pins =3D "gpio125"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; + +&uart5 { + status =3D "okay"; +}; + +&usb_1 { + dr_mode =3D "otg"; + + /* USB 2.0 only, HW does not support USB 3.x */ + qcom,select-utmi-as-pipe-clk; + + status =3D "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l2b>; + vdda12-supply =3D <&vreg_l4b>; + + phys =3D <&pmiv0104_eusb2_repeater>; + + status =3D "okay"; +}; --=20 2.52.0