From nobody Wed Dec 17 01:45:59 2025 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA3ED30DED1 for ; Wed, 10 Dec 2025 16:14:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765383251; cv=none; b=Jcxjvpuid4KZ02v2WY9hR8QisyhILuroK3Ce07ElMMLLqccjLUD30YL5OKBFUqf/QcvMoDuPiU39ALrLXRwfNtIxU6Bcf3I6EkCrBKPT7zHAPpPZY5YiFgZPRzQl8pYGUpcFlvy6DNTC4ErZ2i2KI1vbp0qwnoIm843YWudf6iI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765383251; c=relaxed/simple; bh=PXm4AG2hGsdYLwwyM2sQFSEI0LSfo1j2CNnPg+fTqTA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lxHv0QHZ79211jRvFuxf9fmoQQDeho+Ezl+utnWWJWDmSlIt4l2hviefGuhmcfSjPbCuSh3JDZ5aXRkp6uuO5a0fVwaFfw4le1XNy1u5pGtZ2EXOLlqMQSE//7VGEti/eH7sllrCIZRAp9HExWtwefrRzROYToju6MRF4oQB3Rk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc.com header.i=@rivosinc.com header.b=MKtYkhzY; arc=none smtp.client-ip=209.85.210.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc.com header.i=@rivosinc.com header.b="MKtYkhzY" Received: by mail-pf1-f178.google.com with SMTP id d2e1a72fcca58-7aa2170adf9so5901191b3a.0 for ; Wed, 10 Dec 2025 08:14:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc.com; s=google; t=1765383245; x=1765988045; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jTeBxOv2SMEIJm2X1dOR2xoggDwy3sZYySAZ+VrtZTc=; b=MKtYkhzYB8WGecu/DLdUnYrZru02lVpEl5++RCZ71oxE+oWBb4OJ3HTj8but1J/nVF ytMdAdpX3Ot/9f9CEplMIJSeGOZytIlFHRYlpq40zCzuDZj2fJMy7kTVKq1rzY1psrBq GKo1h1L1WPinXhG4uY3ExGxlweAhfO7CbsTdt/po1GuyzltKL5cXaQg3I8k3mSbzldVj 9K8bAUEhqmH/r4Q2B/9NICp5oBSxfF5+Fjmz0QQz+blY+DMEm/7srkJz7dPvhWd4RgLb +k12RLFo/BKuVIydXXMHwcnlW+wqjFCM4N2S+s00XlDkkG3Xhgr3uYyo/UZHyBEU+oHa RwZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765383245; x=1765988045; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=jTeBxOv2SMEIJm2X1dOR2xoggDwy3sZYySAZ+VrtZTc=; b=Kfz1BghDwpVORUA1P4mMLNIcPsly9GtPiGcYcewHFmhiiny52nmyI0zL62ONNioNgt iW2OZtq4oW5UonXV4cNX0eDb1FyU1lkMd485mfY6QtRIxAgJtzsZzuX6LXgaGp4RqDbr fA11CDazhjqt6SDI3ozcQXFiYR9/gMGuNv9SxmCgEJakRC0eejE/g7Jba0Bpx2AV7ma4 bsiKdZ2UItBWFxnAsaaYdXEjtsHS4zC2ZN6lwQ2jpUjFtAd8ecaKk3duD500b9Qi5lbp GW8f/WHmSgAQBZX1oLQ1BPHqGQNqmemWDsgMLrHxeMARyQVG2O+0lQuv6ylA8H0RYz8h gPbw== X-Forwarded-Encrypted: i=1; AJvYcCXA+WTa02anojbKgxQzq8g/+lx5TuMyij4QTE8YCW5QoXJbmp9YLh+VU2xeFylTUR1fxPQn1M+A+cFxNDU=@vger.kernel.org X-Gm-Message-State: AOJu0YyIfeC7vOwBCXhI6FoN/jMzHk5+uyzeJiKWYuURCiAkeRm3bOiF WcnJuP8ga6zj7E8tgBiAiJePlMJJcR0q5AXynWbqzpnwv/WpNEYTjG2Yozbywvlu5gE= X-Gm-Gg: ASbGnctw+iPRtIjSkGhcfkRAivUoSgaHVLu+0PjYvugrAx6OOW30gnuWxSXjphgW2lz npKHBx/mt3SmzopPPDdXxGDIyw+2r1PTN2pC2z9m6Aom0tM6swlz3ZlqXPxOKAf/vLYMTHlUGR2 BkOsxZCuhabKQQ7PbsuaBYDnGb8hWFXvNdH1yZzrma32v3VIQjaOEYuQ1ZTc/beoZXyS9cuqCAA jxvua8A6t8aoGLvAsuN8Zlq7AY7kPa7Ti/XOygHo4xRpD11LTH9sFbUwEbFjIOBOvCop+WXcT8x vGjsV6ON1Z3UdZVPpRdh/Aw7qX7SF9ASm/oqFh1vrxEGHVXbvJ0bmi3Wj0vbr0yCau0eVGkv9t4 SPMGwpSfFWF1zodcdkcw04Yqmrwby7qw+CO6rExAH2qrS1bLBw90aQCEABWEmG4UiDu3EAOINn3 hR1aRJrQnR8gVh7DtrEfSOD/PPe5pTaHR3B6b8P+YNDnf/szyz+gRfazF/FviU4uX3hFsP9WVW2 MJXcoPGufkZ X-Google-Smtp-Source: AGHT+IEnH2JCzQBXPTwYTipTGasI37dEmVRsGwF2tVJaArwKUp9ryzfhwoIxbl9WMS+Ke/jAN7fjLA== X-Received: by 2002:a05:7022:6289:b0:11b:9e5e:1a40 with SMTP id a92af1059eb24-11f2967d192mr2057361c88.15.1765383244756; Wed, 10 Dec 2025 08:14:04 -0800 (PST) Received: from [127.0.1.1] (p7838222-ipoefx.ipoe.ocn.ne.jp. [123.225.39.221]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f283d4733sm10364600c88.17.2025.12.10.08.14.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 08:14:04 -0800 (PST) From: Charlie Jenkins X-Google-Original-From: Charlie Jenkins Date: Wed, 10 Dec 2025 08:13:43 -0800 Subject: [PATCH RFC 06/10] riscv: Makefile: Add enabled extensions to compiler flags Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-profiles-v1-6-315a6ff2ca5a@gmail.com> References: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> In-Reply-To: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Samuel Holland , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Luke Nelson , Xi Wang , Eric Biggers , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765383226; l=7578; i=thecharlesjenkins@gmail.com; s=20240124; h=from:subject:message-id; bh=PXm4AG2hGsdYLwwyM2sQFSEI0LSfo1j2CNnPg+fTqTA=; b=0kvyOA3UMAW8IGwuP4q/SaToDXNlSkfb6ktLVtbx8kmnGX7Cnn9oikqQ51/0sCC+HvEusUnER HzDVolRAfIsAveQLbAR9G8+jDUiBSxWBDEXdwGEg/9W6pYn//C48M0u X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=eVndo3OHViAjwuqHqbJB4ZtzJzzvk/r6fUf84tZ3rw4= Build an optimized kernel with all extensions that the hardware is expected to support. Extensions that might be supported by hardware and will be detected at runtime will be added to the assembler flags but not to the compiler flags. Signed-off-by: Charlie Jenkins --- arch/riscv/Makefile | 135 ++++++++++++++++++++++++++++++++++++++++++++----= ---- 1 file changed, 116 insertions(+), 19 deletions(-) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index ef1a7b1bffe8..efe43537e984 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -57,37 +57,134 @@ ifeq ($(CONFIG_SHADOW_CALL_STACK),y) KBUILD_LDFLAGS +=3D --no-relax-gp endif =20 -# ISA string setting -riscv-march-y :=3D $(CONFIG_ARCH) -riscv-march-$(CONFIG_FPU) :=3D $(riscv-march-y)fd -riscv-march-$(CONFIG_RISCV_ISA_C) :=3D $(riscv-march-y)c -riscv-march-$(CONFIG_RISCV_ISA_V) :=3D $(riscv-march-y)v +# Handling of riscv extensions +# There are a couple of considerations when enabling extensions: +# 1. Does the toolchain support the extension? +# 2. Is the extension supported by the hardware the kernel will run on? +# 3. Does the extension have registers that need to be save/restored= on +# a context switch? +# 4. Is this extension emitted by the compiler or only by hand-coded +# assembly? +# +# This section has helpers to support extensions with varying answers to t= hese questions. +# +# The compiler will be allowed to emit an extension if all of the following +# are satisfied: +# - The extension is a "stateless" extension (i.e. doesn't introduce= additional +# registers) +# - The extension is supported by the toolchain (selected by CONFIG_TOOLCH= AIN_HAS_*) +# - The extension is enabled for use in the kernel (selected by CONFIG_RIS= CV_ISA_*=3Dy) +# +# Assembler support for the instruction will be added if the extension is +# supported by the assembler (selected by CONFIG_TOOLCHAIN_HAS_*). + +# Extensions that the compiler is allowed to emit anywhere. +riscv-march-standard :=3D $(CONFIG_ARCH) + +# Extensions that the compiler is allowed to emit in FPU contexts. +# This should riscv-march-standard plus the FPU-specific extensions. +riscv-march-fpu :=3D $(CONFIG_ARCH) + +# All extensions supported by the kernel. Some of these extensions require +# special care so they cannot be arbitrarily emitted by the compiler. +riscv-march-full :=3D $(CONFIG_ARCH) + +# Returns the instruction if it is supported, returns the empty string oth= erwise. +# An instruction is only "supported" if RISCV_ISA_*!=3Dn. +# An instruction that is "supported" can be emitted through alternatives, = but an instruction that is +# "enabled" can be emitted arbitrarily by the compiler. +# Arguments: +# $1 - name of extension +# $2 - extension delimiter. Should be empty for base extensions and +# underscore otherwise +extension_supported=3D$(if $(and $(or $(filter $(CONFIG_RISCV_ISA_$(shell = echo $1 | tr a-z A-Z)),m), $(filter $(CONFIG_RISCV_ISA_$(shell echo $1 | tr= a-z A-Z)),y)), $(filter $(CONFIG_TOOLCHAIN_HAS_$(shell echo $1 | tr a-z A-= Z)),y)),$2$1) + +# Returns the instruction if it is enabled, returns the empty string other= wise. +# An instruction is only "enabled" if RISCV_ISA_*=3Dy. +# An instruction that is "supported" can be emitted through alternatives, = but an instruction that is +# "enabled" can be emitted arbitrarily by the compiler. +# Arguments: +# $1 - name of extension +# $2 - extension delimiter. Should be empty for base extensions and +# underscore otherwise +extension_enabled=3D$(if $(and $(filter $(CONFIG_RISCV_ISA_$(shell echo $1= | tr a-z A-Z)),y), $(filter $(CONFIG_TOOLCHAIN_HAS_$(shell echo $1 | tr a-= z A-Z)),y)),$2$1) + +# Use this macro to add support for an extension that is stateless. +# A "stateless" extension is one that does not add additional registers. +# +# Arguments: +# $1 - name of extension +# $2 - extension delimiter. Should be empty for base extensions and +# underscore otherwise +define add_stateless_extension +$(eval riscv-march-standard=3D$(riscv-march-standard)$(call extension_enab= led,$1,$2)) +$(eval riscv-march-fpu=3D$(riscv-march-fpu)$(call extension_enabled,$1,$2)) +$(eval riscv-march-full=3D$(riscv-march-full)$(call extension_supported,$1= ,$2)) +endef =20 -ifneq ($(CONFIG_RISCV_ISA_C),y) - KBUILD_RUSTFLAGS +=3D -Ctarget-feature=3D-c -endif +# Use this macro to add support for a floating point extension. +# Floating point extensions are not able to be used in all contexts, so th= ey +# are kept separate. +# +# Arguments: +# $1 - name of extension +# $2 - extension delimiter. Should be empty for base extensions and +# underscore otherwise +define add_fpu_extension +$(eval riscv-march-fpu=3D$(riscv-march-fpu)$(call extension_enabled,$1,$2)) +$(eval riscv-march-full=3D$(riscv-march-full)$(call extension_supported,$1= ,$2)) +endef + +# Use this macro to add support for an extension that is stateful. +# A "stateful" extension is one that adds additional registers, or requires +# hand-coded assembly (instead of being arbitrarily emitted by the compile= r). +# +# Arguments: +# $1 - name of extension +# $2 - extension delimiter. Should be empty for base extensions and +# underscore otherwise +define add_stateful_extension +$(eval riscv-march-full=3D$(riscv-march-full)$(call extension_supported,$1= ,$2)) +endef + +# Extensions must be added in the canonical ISA string order + +# Base extensions +$(call add_fpu_extension,f) +$(call add_fpu_extension,d) +$(call add_stateless_extension,c) +$(call add_stateful_extension,v) =20 ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC KBUILD_CFLAGS +=3D -Wa,-misa-spec=3D2.2 KBUILD_AFLAGS +=3D -Wa,-misa-spec=3D2.2 else -riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) :=3D $(riscv= -march-y)_zicsr_zifencei +$(call add_stateless_extension,zicsr,_) +$(call add_stateless_extension,zifencei,_) endif =20 -# Check if the toolchain supports Zacas -riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) :=3D $(riscv-march-y)_zacas +# Standard extensions +$(call add_stateless_extension,zabha,_) +$(call add_stateless_extension,zacas,_) +$(call add_stateless_extension,zba,_) +$(call add_stateless_extension,zbb,_) +$(call add_stateless_extension,zbc,_) +$(call add_stateless_extension,zbkb,_) =20 -# Check if the toolchain supports Zabha -riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZABHA) :=3D $(riscv-march-y)_zabha +ifneq ($(CONFIG_RISCV_ISA_C),y) + KBUILD_RUSTFLAGS +=3D -Ctarget-feature=3D-c +endif =20 -# Remove F,D,V from isa string for all. Keep extensions between "fd" and "= v" by -# matching non-v and non-multi-letter extensions out with the filter ([^v_= ]*) -KBUILD_CFLAGS +=3D -march=3D$(shell echo $(riscv-march-y) | sed -E 's/(rv3= 2ima|rv64ima)fd([^v_]*)v?/\1\2/') +# Only include extensions that do not introduce additional state. This +# "additional state" most often means extra registers. +KBUILD_CFLAGS +=3D -march=3D$(riscv-march-standard) =20 -KBUILD_AFLAGS +=3D -march=3D$(riscv-march-y) +# Make all instructions available to the assembler +KBUILD_AFLAGS +=3D -march=3D$(riscv-march-full) =20 -# For C code built with floating-point support, exclude V but keep F and D. -CC_FLAGS_FPU :=3D -march=3D$(shell echo $(riscv-march-y) | sed -E 's/(rv3= 2ima|rv64ima)([^v_]*)v?/\1\2/') +# As an extension of the "standard" march string, include any extensions t= hat +# are able to be used when the FPU is enabled. +CC_FLAGS_FPU :=3D -march=3D$(riscv-march-fpu) =20 KBUILD_CFLAGS +=3D -mno-save-restore =20 --=20 2.43.0