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[123.225.39.221]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f283d4733sm10364600c88.17.2025.12.10.08.13.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 08:13:51 -0800 (PST) From: Charlie Jenkins X-Google-Original-From: Charlie Jenkins Date: Wed, 10 Dec 2025 08:13:38 -0800 Subject: [PATCH RFC 01/10] riscv: Standardize extension capitilization Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-profiles-v1-1-315a6ff2ca5a@gmail.com> References: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> In-Reply-To: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Samuel Holland , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Luke Nelson , Xi Wang , Eric Biggers , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765383226; l=8486; i=thecharlesjenkins@gmail.com; s=20240124; h=from:subject:message-id; bh=1WKxEfgWpJW5Y/4vJJvMgYWzEgjhCSLzMxJDGx9+sF4=; b=GyXzSZm2+GBG8FIkFmBsJDnn2dvMLsepCSRBCLpA05cARsuwW8jyX3svDK36JOrPN1+NQZvfu E8oxZBULm4CB48hfqcbnOyBY5CLyOYlmkbwKllrcKeNjJjyDfygDZve X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=eVndo3OHViAjwuqHqbJB4ZtzJzzvk/r6fUf84tZ3rw4= The base extensions are often lowercase and were written as lowercase in hwcap, but other references to these extensions in the kernel are uppercase. Standardize the case to make it easier to handle macro expansion. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/hwcap.h | 18 +++++++++--------- arch/riscv/include/asm/switch_to.h | 4 ++-- arch/riscv/kernel/cpufeature.c | 32 ++++++++++++++++---------------- arch/riscv/kernel/sys_hwprobe.c | 4 ++-- arch/riscv/kvm/vcpu_onereg.c | 16 ++++++++-------- 5 files changed, 37 insertions(+), 37 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index affd63e11b0a..1ed73effc700 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -10,15 +10,15 @@ =20 #include =20 -#define RISCV_ISA_EXT_a ('a' - 'a') -#define RISCV_ISA_EXT_c ('c' - 'a') -#define RISCV_ISA_EXT_d ('d' - 'a') -#define RISCV_ISA_EXT_f ('f' - 'a') -#define RISCV_ISA_EXT_h ('h' - 'a') -#define RISCV_ISA_EXT_i ('i' - 'a') -#define RISCV_ISA_EXT_m ('m' - 'a') -#define RISCV_ISA_EXT_q ('q' - 'a') -#define RISCV_ISA_EXT_v ('v' - 'a') +#define RISCV_ISA_EXT_A ('a' - 'a') +#define RISCV_ISA_EXT_C ('c' - 'a') +#define RISCV_ISA_EXT_D ('d' - 'a') +#define RISCV_ISA_EXT_F ('f' - 'a') +#define RISCV_ISA_EXT_H ('h' - 'a') +#define RISCV_ISA_EXT_I ('i' - 'a') +#define RISCV_ISA_EXT_M ('m' - 'a') +#define RISCV_ISA_EXT_Q ('q' - 'a') +#define RISCV_ISA_EXT_V ('v' - 'a') =20 /* * These macros represent the logical IDs of each multi-letter RISC-V ISA diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 0e71eb82f920..ff35a4d04f85 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -60,8 +60,8 @@ static inline void __switch_to_fpu(struct task_struct *pr= ev, =20 static __always_inline bool has_fpu(void) { - return riscv_has_extension_likely(RISCV_ISA_EXT_f) || - riscv_has_extension_likely(RISCV_ISA_EXT_d); + return riscv_has_extension_likely(RISCV_ISA_EXT_F) || + riscv_has_extension_likely(RISCV_ISA_EXT_D); } #else static __always_inline bool has_fpu(void) { return false; } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 72ca768f4e91..47612e9ca1c6 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -83,7 +83,7 @@ EXPORT_SYMBOL_GPL(__riscv_isa_extension_available); static int riscv_ext_f_depends(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { - if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_F)) return 0; =20 return -EPROBE_DEFER; @@ -145,7 +145,7 @@ static int riscv_ext_f_validate(const struct riscv_isa_= ext_data *data, * Due to extension ordering, d is checked before f, so no deferral * is required. */ - if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) { + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_D)) { pr_warn_once("This kernel does not support systems with F but not D\n"); return -EINVAL; } @@ -188,7 +188,7 @@ static int riscv_ext_vector_float_validate(const struct= riscv_isa_ext_data *data * Since this function validates vector only, and v/Zve* are probed * after f/d, there's no need for a deferral here. */ - if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_D)) return -EINVAL; =20 return 0; @@ -223,7 +223,7 @@ static int riscv_ext_zcd_validate(const struct riscv_is= a_ext_data *data, const unsigned long *isa_bitmap) { if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && - __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_D)) return 0; =20 return -EPROBE_DEFER; @@ -236,7 +236,7 @@ static int riscv_ext_zcf_validate(const struct riscv_is= a_ext_data *data, return -EINVAL; =20 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && - __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_F)) return 0; =20 return -EPROBE_DEFER; @@ -448,15 +448,15 @@ static const unsigned int riscv_c_exts[] =3D { * New entries to this struct should follow the ordering rules described a= bove. */ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { - __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i), - __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m), - __RISCV_ISA_EXT_SUPERSET(a, RISCV_ISA_EXT_a, riscv_a_exts), - __RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_f, riscv_ext_f_validate), - __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate), - __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), - __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), - __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv= _ext_vector_float_validate), - __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), + __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_I), + __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_M), + __RISCV_ISA_EXT_SUPERSET(a, RISCV_ISA_EXT_A, riscv_a_exts), + __RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_F, riscv_ext_f_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_D, riscv_ext_d_validate), + __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_Q), + __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_C, riscv_c_exts), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_V, riscv_v_exts, riscv= _ext_vector_float_validate), + __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_H), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xli= nuxenvcfg_exts, riscv_ext_zicbom_validate), __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zic= bop_validate), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xli= nuxenvcfg_exts, riscv_ext_zicboz_validate), @@ -847,8 +847,8 @@ static void __init riscv_fill_hwcap_from_isa_string(uns= igned long *isa2hwcap) * marchid. */ if (acpi_disabled && boot_vendorid =3D=3D THEAD_VENDOR_ID && boot_archid= =3D=3D 0x0) { - this_hwcap &=3D ~isa2hwcap[RISCV_ISA_EXT_v]; - clear_bit(RISCV_ISA_EXT_v, source_isa); + this_hwcap &=3D ~isa2hwcap[RISCV_ISA_EXT_V]; + clear_bit(RISCV_ISA_EXT_V, source_isa); } =20 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 199d13f86f31..c9eb28f6ba93 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -80,10 +80,10 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, if (has_fpu()) pair->value |=3D RISCV_HWPROBE_IMA_FD; =20 - if (riscv_isa_extension_available(NULL, c)) + if (riscv_isa_extension_available(NULL, C)) pair->value |=3D RISCV_HWPROBE_IMA_C; =20 - if (has_vector() && riscv_isa_extension_available(NULL, v)) + if (has_vector() && riscv_isa_extension_available(NULL, V)) pair->value |=3D RISCV_HWPROBE_IMA_V; =20 /* diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 865dae903aa0..b6f5d1a74aec 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -26,14 +26,14 @@ /* Mapping between KVM ISA Extension ID & guest ISA extension ID */ static const unsigned long kvm_isa_ext_arr[] =3D { /* Single letter extensions (alphabetically sorted) */ - [KVM_RISCV_ISA_EXT_A] =3D RISCV_ISA_EXT_a, - [KVM_RISCV_ISA_EXT_C] =3D RISCV_ISA_EXT_c, - [KVM_RISCV_ISA_EXT_D] =3D RISCV_ISA_EXT_d, - [KVM_RISCV_ISA_EXT_F] =3D RISCV_ISA_EXT_f, - [KVM_RISCV_ISA_EXT_H] =3D RISCV_ISA_EXT_h, - [KVM_RISCV_ISA_EXT_I] =3D RISCV_ISA_EXT_i, - [KVM_RISCV_ISA_EXT_M] =3D RISCV_ISA_EXT_m, - [KVM_RISCV_ISA_EXT_V] =3D RISCV_ISA_EXT_v, + [KVM_RISCV_ISA_EXT_A] =3D RISCV_ISA_EXT_A, + [KVM_RISCV_ISA_EXT_C] =3D RISCV_ISA_EXT_C, + [KVM_RISCV_ISA_EXT_D] =3D RISCV_ISA_EXT_D, + [KVM_RISCV_ISA_EXT_F] =3D RISCV_ISA_EXT_F, + [KVM_RISCV_ISA_EXT_H] =3D RISCV_ISA_EXT_H, + [KVM_RISCV_ISA_EXT_I] =3D RISCV_ISA_EXT_I, + [KVM_RISCV_ISA_EXT_M] =3D RISCV_ISA_EXT_M, + [KVM_RISCV_ISA_EXT_V] =3D RISCV_ISA_EXT_V, /* Multi letter extensions (alphabetically sorted) */ KVM_ISA_EXT_ARR(SMNPM), KVM_ISA_EXT_ARR(SMSTATEEN), --=20 2.43.0 From nobody Tue Dec 16 16:37:33 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6EDB2D877E for ; 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[123.225.39.221]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f283d4733sm10364600c88.17.2025.12.10.08.13.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 08:13:53 -0800 (PST) From: Charlie Jenkins X-Google-Original-From: Charlie Jenkins Date: Wed, 10 Dec 2025 08:13:39 -0800 Subject: [PATCH RFC 02/10] riscv: kconfig: Reorganize extensions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-profiles-v1-2-315a6ff2ca5a@gmail.com> References: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> In-Reply-To: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Samuel Holland , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Luke Nelson , Xi Wang , Eric Biggers , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765383226; l=25843; i=thecharlesjenkins@gmail.com; s=20240124; h=from:subject:message-id; bh=6kdwEBivu3J/tQ+c4q+1xArl8gxFukdS+lE2W9b0Sa8=; b=70fU2e5YGdMgLe7488IT4Exyl8vGb5qHBzDtAPU0zUI2ZFzkboYP47dj8/Mij4dBYUH25bp23 LK46KddT9B0DXIq2+youyrywKKO1iIVM5Auq2HgXzgZ9kAPC/xlgQq2 X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=eVndo3OHViAjwuqHqbJB4ZtzJzzvk/r6fUf84tZ3rw4= Move extension management out of the main riscv kconfig and into an extension specific one. Since there are so many extensions in riscv, listed them in a separate file can help to keep the kconfig files organized. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig | 335 +-------------------------------------= -- arch/riscv/Kconfig.extensions | 345 ++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 346 insertions(+), 334 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fadec20b87a8..22a6fed0b216 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -552,340 +552,7 @@ config RISCV_ALTERNATIVE_EARLY help Allows early patching of the kernel for special errata =20 -config RISCV_ISA_C - bool "Emit compressed instructions when building Linux" - default y - help - Adds "C" to the ISA subsets that the toolchain is allowed to emit - when building Linux, which results in compressed instructions in the - Linux binary. This option produces a kernel that will not run on - systems that do not support compressed instructions. - - If you don't know what to do here, say Y. - -config RISCV_ISA_SUPM - bool "Supm extension for userspace pointer masking" - depends on 64BIT - default y - help - Add support for pointer masking in userspace (Supm) when the - underlying hardware extension (Smnpm or Ssnpm) is detected at boot. - - If this option is disabled, userspace will be unable to use - the prctl(PR_{SET,GET}_TAGGED_ADDR_CTRL) API. - -config RISCV_ISA_SVNAPOT - bool "Svnapot extension support for supervisor mode NAPOT pages" - depends on 64BIT && MMU - depends on RISCV_ALTERNATIVE - default y - help - Enable support for the Svnapot ISA-extension when it is detected - at boot. - - The Svnapot extension is used to mark contiguous PTEs as a range - of contiguous virtual-to-physical translations for a naturally - aligned power-of-2 (NAPOT) granularity larger than the base 4KB page - size. When HUGETLBFS is also selected this option unconditionally - allocates some memory for each NAPOT page size supported by the kernel. - When optimizing for low memory consumption and for platforms without - the Svnapot extension, it may be better to say N here. - - If you don't know what to do here, say Y. - -config RISCV_ISA_SVPBMT - bool "Svpbmt extension support for supervisor mode page-based memory type= s" - depends on 64BIT && MMU - depends on RISCV_ALTERNATIVE - default y - help - Add support for the Svpbmt ISA-extension (Supervisor-mode: - page-based memory types) in the kernel when it is detected at boot. - - The memory type for a page contains a combination of attributes - that indicate the cacheability, idempotency, and ordering - properties for access to that page. - - The Svpbmt extension is only available on 64-bit cpus. - - If you don't know what to do here, say Y. - -config TOOLCHAIN_HAS_V - bool - default y - depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64imv) - depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32imv) - depends on LD_IS_LLD || LD_VERSION >=3D 23800 - depends on AS_HAS_OPTION_ARCH - -config RISCV_ISA_V - bool "Vector extension support" - depends on TOOLCHAIN_HAS_V - depends on FPU - select DYNAMIC_SIGFRAME - default y - help - Add support for the Vector extension when it is detected at boot. - When this option is disabled, neither the kernel nor userspace may - use vector procedures. - - If you don't know what to do here, say Y. - -config RISCV_ISA_V_DEFAULT_ENABLE - bool "Enable userspace Vector by default" - depends on RISCV_ISA_V - default y - help - Say Y here if you want to enable Vector in userspace by default. - Otherwise, userspace has to make explicit prctl() call to enable - Vector, or enable it via the sysctl interface. - - If you don't know what to do here, say Y. - -config RISCV_ISA_V_UCOPY_THRESHOLD - int "Threshold size for vectorized user copies" - depends on RISCV_ISA_V - default 768 - help - Prefer using vectorized copy_to_user()/copy_from_user() when the - workload size exceeds this value. - -config RISCV_ISA_V_PREEMPTIVE - bool "Run kernel-mode Vector with kernel preemption" - depends on PREEMPTION - depends on RISCV_ISA_V - default y - help - Usually, in-kernel SIMD routines are run with preemption disabled. - Functions which invoke long running SIMD thus must yield the core's - vector unit to prevent blocking other tasks for too long. - - This config allows the kernel to run SIMD without explicitly disabling - preemption. Enabling this config will result in higher memory consumpti= on - due to the allocation of per-task's kernel Vector context. - -config RISCV_ISA_ZAWRS - bool "Zawrs extension support for more efficient busy waiting" - depends on RISCV_ALTERNATIVE - default y - help - The Zawrs extension defines instructions to be used in polling loops - which allow a hart to enter a low-power state or to trap to the - hypervisor while waiting on a store to a memory location. Enable the - use of these instructions in the kernel when the Zawrs extension is - detected at boot. - -config TOOLCHAIN_HAS_ZABHA - bool - default y - depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zabha) - depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zabha) - depends on AS_HAS_OPTION_ARCH - -config RISCV_ISA_ZABHA - bool "Zabha extension support for atomic byte/halfword operations" - depends on TOOLCHAIN_HAS_ZABHA - depends on RISCV_ALTERNATIVE - default y - help - Enable the use of the Zabha ISA-extension to implement kernel - byte/halfword atomic memory operations when it is detected at boot. - - If you don't know what to do here, say Y. - -config TOOLCHAIN_HAS_ZACAS - bool - default y - depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zacas) - depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zacas) - depends on AS_HAS_OPTION_ARCH - -config RISCV_ISA_ZACAS - bool "Zacas extension support for atomic CAS" - depends on RISCV_ALTERNATIVE - default y - help - Enable the use of the Zacas ISA-extension to implement kernel atomic - cmpxchg operations when it is detected at boot. - - If you don't know what to do here, say Y. - -config TOOLCHAIN_HAS_ZBB - bool - default y - depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zbb) - depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zbb) - depends on LD_IS_LLD || LD_VERSION >=3D 23900 - depends on AS_HAS_OPTION_ARCH - -# This symbol indicates that the toolchain supports all v1.0 vector crypto -# extensions, including Zvk*, Zvbb, and Zvbc. LLVM added all of these at = once. -# binutils added all except Zvkb, then added Zvkb. So we just check for Z= vkb. -config TOOLCHAIN_HAS_VECTOR_CRYPTO - def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb) - depends on AS_HAS_OPTION_ARCH - -config TOOLCHAIN_HAS_ZBA - bool - default y - depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zba) - depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zba) - depends on LD_IS_LLD || LD_VERSION >=3D 23900 - depends on AS_HAS_OPTION_ARCH - -config RISCV_ISA_ZBA - bool "Zba extension support for bit manipulation instructions" - default y - help - Add support for enabling optimisations in the kernel when the Zba - extension is detected at boot. - - The Zba extension provides instructions to accelerate the generation - of addresses that index into arrays of basic data types. - - If you don't know what to do here, say Y. - -config RISCV_ISA_ZBB - bool "Zbb extension support for bit manipulation instructions" - depends on RISCV_ALTERNATIVE - default y - help - Add support for enabling optimisations in the kernel when the - Zbb extension is detected at boot. Some optimisations may - additionally depend on toolchain support for Zbb. - - The Zbb extension provides instructions to accelerate a number - of bit-specific operations (count bit population, sign extending, - bitrotation, etc). - - If you don't know what to do here, say Y. - -config TOOLCHAIN_HAS_ZBC - bool - default y - depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zbc) - depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zbc) - depends on LD_IS_LLD || LD_VERSION >=3D 23900 - depends on AS_HAS_OPTION_ARCH - -config RISCV_ISA_ZBC - bool "Zbc extension support for carry-less multiplication instructions" - depends on TOOLCHAIN_HAS_ZBC - depends on MMU - depends on RISCV_ALTERNATIVE - default y - help - Adds support to dynamically detect the presence of the Zbc - extension (carry-less multiplication) and enable its usage. - - The Zbc extension could accelerate CRC (cyclic redundancy check) - calculations. - - If you don't know what to do here, say Y. - -config TOOLCHAIN_HAS_ZBKB - bool - default y - depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zbkb) - depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zbkb) - depends on LD_IS_LLD || LD_VERSION >=3D 23900 - depends on AS_HAS_OPTION_ARCH - -config RISCV_ISA_ZBKB - bool "Zbkb extension support for bit manipulation instructions" - depends on TOOLCHAIN_HAS_ZBKB - depends on RISCV_ALTERNATIVE - default y - help - Adds support to dynamically detect the presence of the ZBKB - extension (bit manipulation for cryptography) and enable its usage. - - The Zbkb extension provides instructions to accelerate a number - of common cryptography operations (pack, zip, etc). - - If you don't know what to do here, say Y. - -config RISCV_ISA_ZICBOM - bool "Zicbom extension support for non-coherent DMA operation" - depends on MMU - depends on RISCV_ALTERNATIVE - default y - select RISCV_DMA_NONCOHERENT - select DMA_DIRECT_REMAP - help - Add support for the Zicbom extension (Cache Block Management - Operations) and enable its use in the kernel when it is detected - at boot. - - The Zicbom extension can be used to handle for example - non-coherent DMA support on devices that need it. - - If you don't know what to do here, say Y. - -config RISCV_ISA_ZICBOZ - bool "Zicboz extension support for faster zeroing of memory" - depends on RISCV_ALTERNATIVE - default y - help - Enable the use of the Zicboz extension (cbo.zero instruction) - in the kernel when it is detected at boot. - - The Zicboz extension is used for faster zeroing of memory. - - If you don't know what to do here, say Y. - -config RISCV_ISA_ZICBOP - bool "Zicbop extension support for cache block prefetch" - depends on MMU - depends on RISCV_ALTERNATIVE - default y - help - Adds support to dynamically detect the presence of the ZICBOP - extension (Cache Block Prefetch Operations) and enable its - usage. - - The Zicbop extension can be used to prefetch cache blocks for - read/write fetch. - - If you don't know what to do here, say Y. - -config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI - def_bool y - # https://sourceware.org/git/?p=3Dbinutils-gdb.git;a=3Dcommit;h=3Daed4428= 6efa8ae8717a77d94b51ac3614e2ca6dc - # https://gcc.gnu.org/git/?p=3Dgcc.git;a=3Dcommit;h=3D98416dbb0a62579d4a7= a4a76bab51b5b52fec2cd - depends on AS_IS_GNU && AS_VERSION >=3D 23600 - help - Binutils-2.38 and GCC-12.1.0 bumped the default ISA spec to the newer - 20191213 version, which moves some instructions from the I extension to - the Zicsr and Zifencei extensions. This requires explicitly specifying - Zicsr and Zifencei when binutils >=3D 2.38 or GCC >=3D 12.1.0. Zicsr - and Zifencei are supported in binutils from version 2.36 onwards. - To make life easier, and avoid forcing toolchains that default to a - newer ISA spec to version 2.2, relax the check to binutils >=3D 2.36. - For clang < 17 or GCC < 11.3.0, for which this is not possible or need - special treatment, this is dealt with in TOOLCHAIN_NEEDS_OLD_ISA_SPEC. - -config TOOLCHAIN_NEEDS_OLD_ISA_SPEC - def_bool y - depends on TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI - # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d449= 8694e15bf8a16 - # https://gcc.gnu.org/git/?p=3Dgcc.git;a=3Dcommit;h=3Dd29f5d6ab513c52fd87= 2f532c492e35ae9fd6671 - depends on (CC_IS_CLANG && CLANG_VERSION < 170000) || (CC_IS_GCC && GCC_V= ERSION < 110300) - help - Certain versions of clang and GCC do not support zicsr and zifencei via - -march. This option causes an older ISA spec compatible with these older - versions of clang and GCC to be passed to GAS, which has the same result - as passing zicsr and zifencei to -march. - -config FPU - bool "FPU support" - default y - help - Add support for floating point operations when an FPU is detected at - boot. When this option is disabled, neither the kernel nor userspace - may use the floating point unit. - - If you don't know what to do here, say Y. +source "arch/riscv/Kconfig.extensions" =20 config IRQ_STACKS bool "Independent irq & softirq stacks" if EXPERT diff --git a/arch/riscv/Kconfig.extensions b/arch/riscv/Kconfig.extensions new file mode 100644 index 000000000000..c9433209117d --- /dev/null +++ b/arch/riscv/Kconfig.extensions @@ -0,0 +1,345 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# For a description of the syntax of this configuration file, +# see Documentation/kbuild/kconfig-language.rst. +# + + +# Base extensions + +config RISCV_ISA_C + bool "Emit compressed instructions when building Linux" + default y + help + Adds "C" to the ISA subsets that the toolchain is allowed to emit + when building Linux, which results in compressed instructions in the + Linux binary. + + If you don't know what to do here, say Y. + +config FPU + bool "FPU support" + default y + help + Say N here if you want to disable all floating-point related procedure + in the kernel. + + If you don't know what to do here, say Y. + +# Standard extensions + +config RISCV_ISA_SUPM + bool "Supm extension for userspace pointer masking" + depends on 64BIT + default y + help + Add support for pointer masking in userspace (Supm) when the + underlying hardware extension (Smnpm or Ssnpm) is detected at boot. + + If this option is disabled, userspace will be unable to use + the prctl(PR_{SET,GET}_TAGGED_ADDR_CTRL) API. + +config RISCV_ISA_SVNAPOT + bool "Svnapot extension support for supervisor mode NAPOT pages" + depends on 64BIT && MMU + depends on RISCV_ALTERNATIVE + default y + help + Allow kernel to detect the Svnapot ISA-extension dynamically at boot + time and enable its usage. + + The Svnapot extension is used to mark contiguous PTEs as a range + of contiguous virtual-to-physical translations for a naturally + aligned power-of-2 (NAPOT) granularity larger than the base 4KB page + size. When HUGETLBFS is also selected this option unconditionally + allocates some memory for each NAPOT page size supported by the kernel. + When optimizing for low memory consumption and for platforms without + the Svnapot extension, it may be better to say N here. + + If you don't know what to do here, say Y. + +config RISCV_ISA_SVPBMT + bool "Svpbmt extension support for supervisor mode page-based memory type= s" + depends on 64BIT && MMU + depends on RISCV_ALTERNATIVE + default y + help + Adds support to dynamically detect the presence of the Svpbmt + ISA-extension (Supervisor-mode: page-based memory types) and + enable its usage. + + The memory type for a page contains a combination of attributes + that indicate the cacheability, idempotency, and ordering + properties for access to that page. + + The Svpbmt extension is only available on 64-bit cpus. + + If you don't know what to do here, say Y. + +config RISCV_ISA_ZAWRS + bool "Zawrs extension support for more efficient busy waiting" + depends on RISCV_ALTERNATIVE + default y + help + The Zawrs extension defines instructions to be used in polling loops + which allow a hart to enter a low-power state or to trap to the + hypervisor while waiting on a store to a memory location. Enable the + use of these instructions in the kernel when the Zawrs extension is + detected at boot. + +config TOOLCHAIN_HAS_ZABHA + bool + default y + depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zabha) + depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zabha) + depends on AS_HAS_OPTION_ARCH + +config RISCV_ISA_ZABHA + bool "Zabha extension support for atomic byte/halfword operations" + depends on TOOLCHAIN_HAS_ZABHA + depends on RISCV_ALTERNATIVE + default y + help + Enable the use of the Zabha ISA-extension to implement kernel + byte/halfword atomic memory operations when it is detected at boot. + + If you don't know what to do here, say Y. + +config TOOLCHAIN_HAS_ZACAS + bool + default y + depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zacas) + depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zacas) + depends on AS_HAS_OPTION_ARCH + +config RISCV_ISA_ZACAS + bool "Zacas extension support for atomic CAS" + depends on TOOLCHAIN_HAS_ZACAS + depends on RISCV_ALTERNATIVE + default y + help + Enable the use of the Zacas ISA-extension to implement kernel atomic + cmpxchg operations when it is detected at boot. + + If you don't know what to do here, say Y. + +config TOOLCHAIN_HAS_ZBA + bool + default y + depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zba) + depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zba) + depends on LD_IS_LLD || LD_VERSION >=3D 23900 + depends on AS_HAS_OPTION_ARCH + +config RISCV_ISA_ZBA + bool "Zba extension support for bit manipulation instructions" + default y + help + Add support for enabling optimisations in the kernel when the Zba + extension is detected at boot. + + The Zba extension provides instructions to accelerate the generation + of addresses that index into arrays of basic data types. + + If you don't know what to do here, say Y. + +config TOOLCHAIN_HAS_ZBB + bool + default y + depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zbb) + depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zbb) + depends on LLD_VERSION >=3D 150000 || LD_VERSION >=3D 23900 + depends on AS_HAS_OPTION_ARCH + +config RISCV_ISA_ZBB + bool "Zbb extension support for bit manipulation instructions" + depends on RISCV_ALTERNATIVE + default y + help + Adds support to dynamically detect the presence of the ZBB + extension (basic bit manipulation) and enable its usage. + + The Zbb extension provides instructions to accelerate a number + of bit-specific operations (count bit population, sign extending, + bitrotation, etc). + + If you don't know what to do here, say Y. + +config TOOLCHAIN_HAS_ZBC + bool + default y + depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zbc) + depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zbc) + depends on LLD_VERSION >=3D 150000 || LD_VERSION >=3D 23900 + depends on AS_HAS_OPTION_ARCH + +config RISCV_ISA_ZBC + bool "Zbc extension support for carry-less multiplication instructions" + depends on RISCV_ALTERNATIVE + default y + help + Adds support to dynamically detect the presence of the Zbc + extension (carry-less multiplication) and enable its usage. + + The Zbc extension could accelerate CRC (cyclic redundancy check) + calculations. + + If you don't know what to do here, say Y. + +config TOOLCHAIN_HAS_ZBKB + bool + default y + depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zbkb) + depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zbkb) + depends on LD_IS_LLD || LD_VERSION >=3D 23900 + depends on AS_HAS_OPTION_ARCH + +config RISCV_ISA_ZBKB + tristate "Zbkb extension support for bit manipulation instructions" + depends on RISCV_ALTERNATIVE + depends on NONPORTABLE || m + default m + help + Adds support to dynamically detect the presence of the ZBKB + extension (bit manipulation for cryptography) and enable its usage. + + The Zbkb extension provides instructions to accelerate a number + of common cryptography operations (pack, zip, etc). + + If you don't know what to do here, say Y. + +config RISCV_ISA_ZICBOM + bool "Zicbom extension support for non-coherent DMA operation" + depends on MMU + depends on RISCV_ALTERNATIVE + default y + select RISCV_DMA_NONCOHERENT + select DMA_DIRECT_REMAP + help + Adds support to dynamically detect the presence of the ZICBOM + extension (Cache Block Management Operations) and enable its + usage. + + The Zicbom extension can be used to handle for example + non-coherent DMA support on devices that need it. + + If you don't know what to do here, say Y. + +config RISCV_ISA_ZICBOZ + bool "Zicboz extension support for faster zeroing of memory" + depends on RISCV_ALTERNATIVE + default y + help + Enable the use of the Zicboz extension (cbo.zero instruction) + when available. + + The Zicboz extension is used for faster zeroing of memory. + + If you don't know what to do here, say Y. + +config RISCV_ISA_ZICBOP + bool "Zicbop extension support for cache block prefetch" + depends on MMU + depends on RISCV_ALTERNATIVE + default y + help + Adds support to dynamically detect the presence of the ZICBOP + extension (Cache Block Prefetch Operations) and enable its + usage. + + The Zicbop extension can be used to prefetch cache blocks for + read/write fetch. + + If you don't know what to do here, say Y. + +## Vector options + +config TOOLCHAIN_HAS_V + bool + default y + depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64imv) + depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32imv) + depends on LLD_VERSION >=3D 140000 || LD_VERSION >=3D 23800 + depends on AS_HAS_OPTION_ARCH + +config RISCV_ISA_V + bool "VECTOR extension support" + depends on TOOLCHAIN_HAS_V + depends on FPU + select DYNAMIC_SIGFRAME + default y + help + Say N here if you want to disable all vector related procedure + in the kernel. + + If you don't know what to do here, say Y. + +config RISCV_ISA_V_DEFAULT_ENABLE + bool "Enable userspace Vector by default" + depends on RISCV_ISA_V + default y + help + Say Y here if you want to enable Vector in userspace by default. + Otherwise, userspace has to make explicit prctl() call to enable + Vector, or enable it via the sysctl interface. + + If you don't know what to do here, say Y. + +config RISCV_ISA_V_UCOPY_THRESHOLD + int "Threshold size for vectorized user copies" + depends on RISCV_ISA_V + default 768 + help + Prefer using vectorized copy_to_user()/copy_from_user() when the + workload size exceeds this value. + +config RISCV_ISA_V_PREEMPTIVE + bool "Run kernel-mode Vector with kernel preemption" + depends on PREEMPTION + depends on RISCV_ISA_V + default y + help + Usually, in-kernel SIMD routines are run with preemption disabled. + Functions which envoke long running SIMD thus must yield core's + vector unit to prevent blocking other tasks for too long. + + This config allows kernel to run SIMD without explicitly disable + preemption. Enabling this config will result in higher memory + consumption due to the allocation of per-task's kernel Vector context. + +# This symbol indicates that the toolchain supports all v1.0 vector crypto +# extensions, including Zvk*, Zvbb, and Zvbc. LLVM added all of these at = once. +# binutils added all except Zvkb, then added Zvkb. So we just check for Z= vkb. +config TOOLCHAIN_HAS_VECTOR_CRYPTO + def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb) + depends on AS_HAS_OPTION_ARCH + +# Legacy options + +config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI + def_bool y + # https://sourceware.org/git/?p=3Dbinutils-gdb.git;a=3Dcommit;h=3Daed4428= 6efa8ae8717a77d94b51ac3614e2ca6dc + # https://gcc.gnu.org/git/?p=3Dgcc.git;a=3Dcommit;h=3D98416dbb0a62579d4a7= a4a76bab51b5b52fec2cd + depends on AS_IS_GNU && AS_VERSION >=3D 23600 + help + Binutils-2.38 and GCC-12.1.0 bumped the default ISA spec to the newer + 20191213 version, which moves some instructions from the I extension to + the Zicsr and Zifencei extensions. This requires explicitly specifying + Zicsr and Zifencei when binutils >=3D 2.38 or GCC >=3D 12.1.0. Zicsr + and Zifencei are supported in binutils from version 2.36 onwards. + To make life easier, and avoid forcing toolchains that default to a + newer ISA spec to version 2.2, relax the check to binutils >=3D 2.36. + For clang < 17 or GCC < 11.3.0, for which this is not possible or need + special treatment, this is dealt with in TOOLCHAIN_NEEDS_OLD_ISA_SPEC. + +config TOOLCHAIN_NEEDS_OLD_ISA_SPEC + def_bool y + depends on TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI + # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d449= 8694e15bf8a16 + # https://gcc.gnu.org/git/?p=3Dgcc.git;a=3Dcommit;h=3Dd29f5d6ab513c52fd87= 2f532c492e35ae9fd6671 + depends on (CC_IS_CLANG && CLANG_VERSION < 170000) || (CC_IS_GCC && GCC_V= ERSION < 110300) + help + Certain versions of clang and GCC do not support zicsr and zifencei via + -march. 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[123.225.39.221]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f283d4733sm10364600c88.17.2025.12.10.08.13.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 08:13:56 -0800 (PST) From: Charlie Jenkins X-Google-Original-From: Charlie Jenkins Date: Wed, 10 Dec 2025 08:13:40 -0800 Subject: [PATCH RFC 03/10] riscv: kconfig: Simply arch selection Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-profiles-v1-3-315a6ff2ca5a@gmail.com> References: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> In-Reply-To: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Samuel Holland , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Luke Nelson , Xi Wang , Eric Biggers , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765383226; l=1325; i=thecharlesjenkins@gmail.com; s=20240124; h=from:subject:message-id; bh=zzLBT9CTg0Wd6TsXf4wm0xzdyCWnbtQr2Yp154TelHI=; b=mT+yscPZblLBKxRJNA6HXDldsUZrXZ0JWLfUCnFeszlF9zTiyst2vR0PuOKcwCf+sYRUsaOH2 1jU1OMRHGclA/9WQrx/nX/2sNQ06hJp7NTA843sGUBXNdk2bS0UjZWw X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=eVndo3OHViAjwuqHqbJB4ZtzJzzvk/r6fUf84tZ3rw4= Separate out the base arch into kconfig so it's reusable as a string variable. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig | 5 +++++ arch/riscv/Makefile | 3 +-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 22a6fed0b216..ecf22223962a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -418,6 +418,11 @@ config ARCH_RV64I =20 endchoice =20 +config ARCH + string + default "rv32ima" if ARCH_RV32I + default "rv64ima" if ARCH_RV64I + # We must be able to map all physical memory into the kernel, but the comp= iler # is still a bit more efficient when generating code if it's setup in a ma= nner # such that it can only map 2GiB of memory. diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 4c6de57f65ef..ef1a7b1bffe8 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -58,8 +58,7 @@ ifeq ($(CONFIG_SHADOW_CALL_STACK),y) endif =20 # ISA string setting -riscv-march-$(CONFIG_ARCH_RV32I) :=3D rv32ima -riscv-march-$(CONFIG_ARCH_RV64I) :=3D rv64ima +riscv-march-y :=3D $(CONFIG_ARCH) riscv-march-$(CONFIG_FPU) :=3D $(riscv-march-y)fd riscv-march-$(CONFIG_RISCV_ISA_C) :=3D $(riscv-march-y)c riscv-march-$(CONFIG_RISCV_ISA_V) :=3D $(riscv-march-y)v --=20 2.43.0 From nobody Tue Dec 16 16:37:33 2025 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79D7E30102B for ; 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[123.225.39.221]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f283d4733sm10364600c88.17.2025.12.10.08.13.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 08:13:59 -0800 (PST) From: Charlie Jenkins X-Google-Original-From: Charlie Jenkins Date: Wed, 10 Dec 2025 08:13:41 -0800 Subject: [PATCH RFC 04/10] riscv: kconfig: Make extensions tristate Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-profiles-v1-4-315a6ff2ca5a@gmail.com> References: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> In-Reply-To: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Samuel Holland , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Luke Nelson , Xi Wang , Eric Biggers , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765383226; l=35513; i=thecharlesjenkins@gmail.com; s=20240124; h=from:subject:message-id; bh=MwDMgRQUj9IYUhivKXBxMhq2adjFQkiajg5twmoVRzo=; b=q1v3m9t/Zk143QzjSCsWMf9uV/IXAWQqc0YzQmcRkBGOb5m0iBtl6V3Fx4xfaeR2YlRO92/aJ 4nCfsZjRpmcDpoe+lvFV9qO3WLGBapF6cdpUGvNk5edkzNCMdqb4Vev X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=eVndo3OHViAjwuqHqbJB4ZtzJzzvk/r6fUf84tZ3rw4= Use a tristate for CONFIG_RISCV_ISA_* to signal the three states: - y -> Hardware will be assumed to support the extension. - m -> The kernel will detect at boot if the extension is supported by the hardware. - n -> Hardware will be assumed to not support the extension. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.extensions | 259 ++++++++++++++---= ---- arch/riscv/include/asm/asm-prototypes.h | 2 +- arch/riscv/include/asm/barrier.h | 2 +- arch/riscv/include/asm/cmpxchg.h | 2 +- arch/riscv/include/asm/hugetlb.h | 2 +- arch/riscv/include/asm/kgdb.h | 2 +- arch/riscv/include/asm/kvm_vcpu_vector.h | 2 +- arch/riscv/include/asm/mmu.h | 2 +- arch/riscv/include/asm/mmu_context.h | 4 +- arch/riscv/include/asm/page.h | 2 +- arch/riscv/include/asm/pgtable-64.h | 2 +- arch/riscv/include/asm/processor.h | 2 +- arch/riscv/include/asm/simd.h | 2 +- arch/riscv/include/asm/uprobes.h | 2 +- arch/riscv/include/asm/vector.h | 2 +- arch/riscv/include/asm/xor.h | 2 +- arch/riscv/kernel/Makefile | 6 +- arch/riscv/kernel/head.S | 2 +- arch/riscv/kernel/kgdb.c | 2 +- arch/riscv/kernel/probes/decode-insn.c | 2 +- arch/riscv/kernel/probes/uprobes.c | 2 +- arch/riscv/kernel/process.c | 2 +- arch/riscv/kernel/ptrace.c | 12 +- arch/riscv/kernel/signal.c | 2 +- arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S | 6 +- arch/riscv/kvm/vcpu_vector.c | 2 +- arch/riscv/lib/Makefile | 14 +- arch/riscv/lib/strcmp.S | 2 +- arch/riscv/lib/strlen.S | 2 +- arch/riscv/lib/strncmp.S | 2 +- arch/riscv/lib/uaccess.S | 4 +- arch/riscv/mm/hugetlbpage.c | 2 +- lib/raid6/Makefile | 4 +- lib/raid6/algos.c | 4 +- 34 files changed, 229 insertions(+), 134 deletions(-) diff --git a/arch/riscv/Kconfig.extensions b/arch/riscv/Kconfig.extensions index c9433209117d..e3ca147765b1 100644 --- a/arch/riscv/Kconfig.extensions +++ b/arch/riscv/Kconfig.extensions @@ -7,6 +7,11 @@ =20 # Base extensions =20 +config TOOLCHAIN_HAS_C + def_bool y + help + Platform supports compressed instructions + config RISCV_ISA_C bool "Emit compressed instructions when building Linux" default y @@ -17,21 +22,50 @@ config RISCV_ISA_C =20 If you don't know what to do here, say Y. =20 +config TOOLCHAIN_HAS_F + bool + default y + depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64imaf) + depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32imaf) + depends on AS_HAS_OPTION_ARCH + +config TOOLCHAIN_HAS_D + bool + default y + depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64imad) + depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32imad) + depends on AS_HAS_OPTION_ARCH + config FPU bool "FPU support" default y + depends on TOOLCHAIN_HAS_F + depends on TOOLCHAIN_HAS_D + select RISCV_ISA_F + select RISCV_ISA_D help Say N here if you want to disable all floating-point related procedure in the kernel. =20 If you don't know what to do here, say Y. =20 +config RISCV_ISA_F + def_bool n + help + Platform supports F + +config RISCV_ISA_D + def_bool n + help + Platform supports D + # Standard extensions =20 config RISCV_ISA_SUPM - bool "Supm extension for userspace pointer masking" + tristate "Supm extension for userspace pointer masking" depends on 64BIT - default y + depends on NONPORTABLE || m + default m help Add support for pointer masking in userspace (Supm) when the underlying hardware extension (Smnpm or Ssnpm) is detected at boot. @@ -39,15 +73,18 @@ config RISCV_ISA_SUPM If this option is disabled, userspace will be unable to use the prctl(PR_{SET,GET}_TAGGED_ADDR_CTRL) API. =20 + Select "m" for boot-time detection for portability. + + Select "y" for compile-time optimization. Only available with NONPORTAB= LE. + + If you don't know what to do here, say m. + config RISCV_ISA_SVNAPOT - bool "Svnapot extension support for supervisor mode NAPOT pages" + tristate "Svnapot extension support for supervisor mode NAPOT pages" depends on 64BIT && MMU - depends on RISCV_ALTERNATIVE - default y + depends on NONPORTABLE || m + default m help - Allow kernel to detect the Svnapot ISA-extension dynamically at boot - time and enable its usage. - The Svnapot extension is used to mark contiguous PTEs as a range of contiguous virtual-to-physical translations for a naturally aligned power-of-2 (NAPOT) granularity larger than the base 4KB page @@ -56,30 +93,35 @@ config RISCV_ISA_SVNAPOT When optimizing for low memory consumption and for platforms without the Svnapot extension, it may be better to say N here. =20 - If you don't know what to do here, say Y. + Select "m" for boot-time detection for portability. + + Select "y" for compile-time optimization. Only available with NONPORTAB= LE. + + If you don't know what to do here, say m. =20 config RISCV_ISA_SVPBMT - bool "Svpbmt extension support for supervisor mode page-based memory type= s" + tristate "Svpbmt extension support for supervisor mode page-based memory = types" depends on 64BIT && MMU - depends on RISCV_ALTERNATIVE - default y + depends on NONPORTABLE || m + default m help - Adds support to dynamically detect the presence of the Svpbmt - ISA-extension (Supervisor-mode: page-based memory types) and - enable its usage. + The memory type for a page contains a combination of attributes + that indicate the cacheability, idempotency, and ordering + properties for access to that page. + + The Svpbmt extension is only available on 64-bit cpus. + + Select "m" for boot-time detection for portability. =20 - The memory type for a page contains a combination of attributes - that indicate the cacheability, idempotency, and ordering - properties for access to that page. + Select "y" for compile-time optimization. Only available with NONPORTAB= LE. =20 - The Svpbmt extension is only available on 64-bit cpus. + If you don't know what to do here, say m. =20 - If you don't know what to do here, say Y. =20 config RISCV_ISA_ZAWRS - bool "Zawrs extension support for more efficient busy waiting" - depends on RISCV_ALTERNATIVE - default y + tristate "Zawrs extension support for more efficient busy waiting" + depends on NONPORTABLE || m + default m help The Zawrs extension defines instructions to be used in polling loops which allow a hart to enter a low-power state or to trap to the @@ -95,15 +137,19 @@ config TOOLCHAIN_HAS_ZABHA depends on AS_HAS_OPTION_ARCH =20 config RISCV_ISA_ZABHA - bool "Zabha extension support for atomic byte/halfword operations" + tristate "Zabha extension support for atomic byte/halfword operations" depends on TOOLCHAIN_HAS_ZABHA - depends on RISCV_ALTERNATIVE - default y + depends on NONPORTABLE || m + default m help Enable the use of the Zabha ISA-extension to implement kernel - byte/halfword atomic memory operations when it is detected at boot. + byte/halfword atomic memory operations. =20 - If you don't know what to do here, say Y. + Select "m" for boot-time detection for portability. + + Select "y" for compile-time optimization. Only available with NONPORTAB= LE. + + If you don't know what to do here, say m. =20 config TOOLCHAIN_HAS_ZACAS bool @@ -113,15 +159,19 @@ config TOOLCHAIN_HAS_ZACAS depends on AS_HAS_OPTION_ARCH =20 config RISCV_ISA_ZACAS - bool "Zacas extension support for atomic CAS" + tristate "Zacas extension support for atomic CAS" depends on TOOLCHAIN_HAS_ZACAS - depends on RISCV_ALTERNATIVE - default y + depends on NONPORTABLE || m + default m help Enable the use of the Zacas ISA-extension to implement kernel atomic - cmpxchg operations when it is detected at boot. + cmpxchg operations. =20 - If you don't know what to do here, say Y. + Select "m" for boot-time detection for portability. + + Select "y" for compile-time optimization. Only available with NONPORTAB= LE. + + If you don't know what to do here, say m. =20 config TOOLCHAIN_HAS_ZBA bool @@ -132,16 +182,18 @@ config TOOLCHAIN_HAS_ZBA depends on AS_HAS_OPTION_ARCH =20 config RISCV_ISA_ZBA - bool "Zba extension support for bit manipulation instructions" - default y + tristate "Zba extension support for bit manipulation instructions" + depends on NONPORTABLE || m + default m help - Add support for enabling optimisations in the kernel when the Zba - extension is detected at boot. + The Zba extension provides instructions to accelerate the generation + of addresses that index into arrays of basic data types. =20 - The Zba extension provides instructions to accelerate the generation - of addresses that index into arrays of basic data types. + Select "m" for boot-time detection for portability. =20 - If you don't know what to do here, say Y. + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + + If you don't know what to do here, say m. =20 config TOOLCHAIN_HAS_ZBB bool @@ -152,18 +204,19 @@ config TOOLCHAIN_HAS_ZBB depends on AS_HAS_OPTION_ARCH =20 config RISCV_ISA_ZBB - bool "Zbb extension support for bit manipulation instructions" - depends on RISCV_ALTERNATIVE - default y + tristate "Zbb extension support for bit manipulation instructions" + depends on NONPORTABLE || m + default m help - Adds support to dynamically detect the presence of the ZBB - extension (basic bit manipulation) and enable its usage. + The Zbb extension provides instructions to accelerate a number + of bit-specific operations (count bit population, sign extending, + bitrotation, etc). + + Select "m" for boot-time detection for portability. =20 - The Zbb extension provides instructions to accelerate a number - of bit-specific operations (count bit population, sign extending, - bitrotation, etc). + Select "y" for compile-time optimization. Only available with NONPORTAB= LE. =20 - If you don't know what to do here, say Y. + If you don't know what to do here, say m. =20 config TOOLCHAIN_HAS_ZBC bool @@ -174,17 +227,18 @@ config TOOLCHAIN_HAS_ZBC depends on AS_HAS_OPTION_ARCH =20 config RISCV_ISA_ZBC - bool "Zbc extension support for carry-less multiplication instructions" - depends on RISCV_ALTERNATIVE - default y + tristate "Zbc extension support for carry-less multiplication instruction= s" + depends on NONPORTABLE || m + default m help - Adds support to dynamically detect the presence of the Zbc - extension (carry-less multiplication) and enable its usage. + The Zbc extension could accelerate CRC (cyclic redundancy check) + calculations. + + Select "m" for boot-time detection for portability. =20 - The Zbc extension could accelerate CRC (cyclic redundancy check) - calculations. + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. =20 - If you don't know what to do here, say Y. + If you don't know what to do here, say m. =20 config TOOLCHAIN_HAS_ZBKB bool @@ -196,61 +250,87 @@ config TOOLCHAIN_HAS_ZBKB =20 config RISCV_ISA_ZBKB tristate "Zbkb extension support for bit manipulation instructions" - depends on RISCV_ALTERNATIVE depends on NONPORTABLE || m default m help - Adds support to dynamically detect the presence of the ZBKB - extension (bit manipulation for cryptography) and enable its usage. + The Zbkb extension provides instructions to accelerate a number + of common cryptography operations (pack, zip, etc). =20 - The Zbkb extension provides instructions to accelerate a number - of common cryptography operations (pack, zip, etc). + Select "m" for boot-time detection for portability. =20 - If you don't know what to do here, say Y. + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + + If you don't know what to do here, say m. =20 config RISCV_ISA_ZICBOM bool "Zicbom extension support for non-coherent DMA operation" depends on MMU - depends on RISCV_ALTERNATIVE - default y + depends on NONPORTABLE || m + default m select RISCV_DMA_NONCOHERENT select DMA_DIRECT_REMAP help - Adds support to dynamically detect the presence of the ZICBOM - extension (Cache Block Management Operations) and enable its - usage. + The Zicbom extension can be used to handle for example + non-coherent DMA support on devices that need it. + + Select "m" for boot-time detection for portability. =20 - The Zicbom extension can be used to handle for example - non-coherent DMA support on devices that need it. + Select "y" for compile-time optimization. Only available with NONPORTAB= LE. =20 - If you don't know what to do here, say Y. + If you don't know what to do here, say m. =20 config RISCV_ISA_ZICBOZ bool "Zicboz extension support for faster zeroing of memory" - depends on RISCV_ALTERNATIVE - default y + depends on NONPORTABLE || m + default m help - Enable the use of the Zicboz extension (cbo.zero instruction) - when available. + Enable the use of the Zicboz extension (cbo.zero instruction) + when available. + + The Zicboz extension is used for faster zeroing of memory. =20 - The Zicboz extension is used for faster zeroing of memory. + Select "m" for boot-time detection for portability. =20 - If you don't know what to do here, say Y. + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + + If you don't know what to do here, say m. =20 config RISCV_ISA_ZICBOP bool "Zicbop extension support for cache block prefetch" depends on MMU - depends on RISCV_ALTERNATIVE - default y + depends on NONPORTABLE || m + default m help - Adds support to dynamically detect the presence of the ZICBOP - extension (Cache Block Prefetch Operations) and enable its - usage. - The Zicbop extension can be used to prefetch cache blocks for read/write fetch. =20 - If you don't know what to do here, say Y. + Select "m" for boot-time detection for portability. + + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + + If you don't know what to do here, say m. + +## Required extensions + +config TOOLCHAIN_HAS_ZICSR + def_bool y + help + Platform supports explicit Zicsr + +config RISCV_ISA_ZICSR + def_bool y + help + Platform supports explicit Zicsr + +config TOOLCHAIN_HAS_ZIFENCEI + def_bool y + help + Platform supports explicit Zifencei + +config RISCV_ISA_ZIFENCEI + def_bool y + help + Platform supports explicit Zifencei =20 ## Vector options =20 @@ -263,16 +343,21 @@ config TOOLCHAIN_HAS_V depends on AS_HAS_OPTION_ARCH =20 config RISCV_ISA_V - bool "VECTOR extension support" + tristate "VECTOR extension support" depends on TOOLCHAIN_HAS_V depends on FPU select DYNAMIC_SIGFRAME - default y + depends on NONPORTABLE || m + default m help Say N here if you want to disable all vector related procedure in the kernel. =20 - If you don't know what to do here, say Y. + Select "m" for boot-time detection for portability. + + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + + If you don't know what to do here, say m. =20 config RISCV_ISA_V_DEFAULT_ENABLE bool "Enable userspace Vector by default" diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/a= sm/asm-prototypes.h index a9988bf21ec8..7896f24c9119 100644 --- a/arch/riscv/include/asm/asm-prototypes.h +++ b/arch/riscv/include/asm/asm-prototypes.h @@ -9,7 +9,7 @@ long long __lshrti3(long long a, int b); long long __ashrti3(long long a, int b); long long __ashlti3(long long a, int b); =20 -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) =20 #ifdef CONFIG_MMU asmlinkage int enter_vector_usercopy(void *dst, void *src, size_t n, bool = enable_sum); diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barr= ier.h index 700ba3f922cb..64e91500d316 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -66,7 +66,7 @@ do { \ ___p1; \ }) =20 -#ifdef CONFIG_RISCV_ISA_ZAWRS +#if IS_ENABLED(CONFIG_RISCV_ISA_ZAWRS) #define smp_cond_load_relaxed(ptr, cond_expr) ({ \ typeof(ptr) __PTR =3D (ptr); \ __unqual_scalar_typeof(*ptr) VAL; \ diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpx= chg.h index 8712cf9c69dc..0fee37752098 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -356,7 +356,7 @@ union __u128_halves { =20 #endif /* CONFIG_64BIT && CONFIG_RISCV_ISA_ZACAS && CONFIG_TOOLCHAIN_HAS_Z= ACAS */ =20 -#ifdef CONFIG_RISCV_ISA_ZAWRS +#if IS_ENABLED(CONFIG_RISCV_ISA_ZAWRS) /* * Despite wrs.nto being "WRS-with-no-timeout", in the absence of changes = to * @val we expect it to still terminate within a "reasonable" amount of ti= me diff --git a/arch/riscv/include/asm/hugetlb.h b/arch/riscv/include/asm/huge= tlb.h index 0872d43fc0c0..f2d8c33e3fea 100644 --- a/arch/riscv/include/asm/hugetlb.h +++ b/arch/riscv/include/asm/hugetlb.h @@ -16,7 +16,7 @@ bool arch_hugetlb_migration_supported(struct hstate *h); #define arch_hugetlb_migration_supported arch_hugetlb_migration_supported #endif =20 -#ifdef CONFIG_RISCV_ISA_SVNAPOT +#if IS_ENABLED(CONFIG_RISCV_ISA_SVNAPOT) #define __HAVE_ARCH_HUGE_PTE_CLEAR void huge_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep, unsigned long sz); diff --git a/arch/riscv/include/asm/kgdb.h b/arch/riscv/include/asm/kgdb.h index 78b18e2fd771..123d0c8ec15b 100644 --- a/arch/riscv/include/asm/kgdb.h +++ b/arch/riscv/include/asm/kgdb.h @@ -15,7 +15,7 @@ #define BUFMAX 2048 static_assert(BUFMAX > NUMREGBYTES, "As per KGDB documentation, BUFMAX must be larger than NUMREGBYTES"= ); -#ifdef CONFIG_RISCV_ISA_C +#if IS_ENABLED(CONFIG_RISCV_ISA_C) #define BREAK_INSTR_SIZE 2 #else #define BREAK_INSTR_SIZE 4 diff --git a/arch/riscv/include/asm/kvm_vcpu_vector.h b/arch/riscv/include/= asm/kvm_vcpu_vector.h index 57a798a4cb0d..6f6f646f9086 100644 --- a/arch/riscv/include/asm/kvm_vcpu_vector.h +++ b/arch/riscv/include/asm/kvm_vcpu_vector.h @@ -12,7 +12,7 @@ =20 #include =20 -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) #include #include =20 diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h index cf8e6eac77d5..14ce156c9ede 100644 --- a/arch/riscv/include/asm/mmu.h +++ b/arch/riscv/include/asm/mmu.h @@ -27,7 +27,7 @@ typedef struct { unsigned long interp_fdpic_loadmap; #endif unsigned long flags; -#ifdef CONFIG_RISCV_ISA_SUPM +#if IS_ENABLED(CONFIG_RISCV_ISA_SUPM) u8 pmlen; #endif } mm_context_t; diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/= mmu_context.h index 8c4bc49a3a0f..83de55a905a6 100644 --- a/arch/riscv/include/asm/mmu_context.h +++ b/arch/riscv/include/asm/mmu_context.h @@ -20,7 +20,7 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *= next, static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next) { -#ifdef CONFIG_RISCV_ISA_SUPM +#if IS_ENABLED(CONFIG_RISCV_ISA_SUPM) next->context.pmlen =3D 0; #endif switch_mm(prev, next, NULL); @@ -40,7 +40,7 @@ static inline int init_new_context(struct task_struct *ts= k, =20 DECLARE_STATIC_KEY_FALSE(use_asid_allocator); =20 -#ifdef CONFIG_RISCV_ISA_SUPM +#if IS_ENABLED(CONFIG_RISCV_ISA_SUPM) #define mm_untag_mask mm_untag_mask static inline unsigned long mm_untag_mask(struct mm_struct *mm) { diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h index ffe213ad65a4..7bf143d68374 100644 --- a/arch/riscv/include/asm/page.h +++ b/arch/riscv/include/asm/page.h @@ -43,7 +43,7 @@ =20 #ifndef __ASSEMBLER__ =20 -#ifdef CONFIG_RISCV_ISA_ZICBOZ +#if IS_ENABLED(CONFIG_RISCV_ISA_ZICBOZ) void clear_page(void *page); #else #define clear_page(pgaddr) memset((pgaddr), 0, PAGE_SIZE) diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/p= gtable-64.h index 6e789fa58514..af949a2ae66e 100644 --- a/arch/riscv/include/asm/pgtable-64.h +++ b/arch/riscv/include/asm/pgtable-64.h @@ -106,7 +106,7 @@ enum napot_cont_order { #define napot_cont_mask(order) (~(napot_cont_size(order) - 1UL)) #define napot_pte_num(order) BIT(order) =20 -#ifdef CONFIG_RISCV_ISA_SVNAPOT +#if IS_ENABLED(CONFIG_RISCV_ISA_SVNAPOT) #define HUGE_MAX_HSTATE (2 + (NAPOT_ORDER_MAX - NAPOT_CONT_ORDER_BASE)) #else #define HUGE_MAX_HSTATE 2 diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index da5426122d28..b22feac304f1 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -190,7 +190,7 @@ extern int arch_dup_task_struct(struct task_struct *dst= , struct task_struct *src =20 extern unsigned long signal_minsigstksz __ro_after_init; =20 -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) /* Userspace interface for PR_RISCV_V_{SET,GET}_VS prctl()s: */ #define RISCV_V_SET_CONTROL(arg) riscv_v_vstate_ctrl_set_current(arg) #define RISCV_V_GET_CONTROL() riscv_v_vstate_ctrl_get_current() diff --git a/arch/riscv/include/asm/simd.h b/arch/riscv/include/asm/simd.h index adb50f3ec205..7730e4de1d4e 100644 --- a/arch/riscv/include/asm/simd.h +++ b/arch/riscv/include/asm/simd.h @@ -16,7 +16,7 @@ =20 #include =20 -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) /* * may_use_simd - whether it is allowable at this time to issue vector * instructions or access the vector register file diff --git a/arch/riscv/include/asm/uprobes.h b/arch/riscv/include/asm/upro= bes.h index 5008f76cdc27..b00d8ed95403 100644 --- a/arch/riscv/include/asm/uprobes.h +++ b/arch/riscv/include/asm/uprobes.h @@ -9,7 +9,7 @@ =20 #define MAX_UINSN_BYTES 8 =20 -#ifdef CONFIG_RISCV_ISA_C +#if IS_ENABLED(CONFIG_RISCV_ISA_C) #define UPROBE_SWBP_INSN __BUG_INSN_16 #define UPROBE_SWBP_INSN_SIZE 2 #else diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vecto= r.h index b61786d43c20..7a506c780874 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -9,7 +9,7 @@ #include #include =20 -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) =20 #include #include diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h index 96011861e46b..c2b7cd7cfde4 100644 --- a/arch/riscv/include/asm/xor.h +++ b/arch/riscv/include/asm/xor.h @@ -5,7 +5,7 @@ =20 #include #include -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) #include #include #include diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index f60fce69b725..a52f58810f16 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -80,8 +80,10 @@ obj-$(CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS) +=3D v= ec-copy-unaligned.o =20 obj-$(CONFIG_FPU) +=3D fpu.o obj-$(CONFIG_FPU) +=3D kernel_mode_fpu.o -obj-$(CONFIG_RISCV_ISA_V) +=3D vector.o -obj-$(CONFIG_RISCV_ISA_V) +=3D kernel_mode_vector.o +ifneq ($(filter y m,$(CONFIG_RISCV_ISA_V)),) +obj-y +=3D vector.o +obj-y +=3D kernel_mode_vector.o +endif obj-$(CONFIG_SMP) +=3D smpboot.o obj-$(CONFIG_SMP) +=3D smp.o obj-$(CONFIG_SMP) +=3D cpu_ops.o diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index bdf3352acf4c..61fec769ff3d 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -446,7 +446,7 @@ SYM_CODE_START_LOCAL(reset_regs) .Lreset_regs_done_fpu: #endif /* CONFIG_FPU */ =20 -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) csrr t0, CSR_MISA li t1, COMPAT_HWCAP_ISA_V and t0, t0, t1 diff --git a/arch/riscv/kernel/kgdb.c b/arch/riscv/kernel/kgdb.c index 15fec5d1e6de..147fe3a24eb9 100644 --- a/arch/riscv/kernel/kgdb.c +++ b/arch/riscv/kernel/kgdb.c @@ -366,7 +366,7 @@ void kgdb_arch_exit(void) /* * Global data */ -#ifdef CONFIG_RISCV_ISA_C +#if IS_ENABLED(CONFIG_RISCV_ISA_C) const struct kgdb_arch arch_kgdb_ops =3D { .gdb_bpt_instr =3D {0x02, 0x90}, /* c.ebreak */ }; diff --git a/arch/riscv/kernel/probes/decode-insn.c b/arch/riscv/kernel/pro= bes/decode-insn.c index 65d9590bfb9f..685a0be6542b 100644 --- a/arch/riscv/kernel/probes/decode-insn.c +++ b/arch/riscv/kernel/probes/decode-insn.c @@ -28,7 +28,7 @@ riscv_probe_decode_insn(probe_opcode_t *addr, struct arch= _probe_insn *api) * Simulate instructions list: * TODO: the REJECTED ones below need to be implemented */ -#ifdef CONFIG_RISCV_ISA_C +#if IS_ENABLED(CONFIG_RISCV_ISA_C) RISCV_INSN_REJECTED(c_jal, insn); RISCV_INSN_REJECTED(c_ebreak, insn); =20 diff --git a/arch/riscv/kernel/probes/uprobes.c b/arch/riscv/kernel/probes/= uprobes.c index cc15f7ca6cc1..133f646019f1 100644 --- a/arch/riscv/kernel/probes/uprobes.c +++ b/arch/riscv/kernel/probes/uprobes.c @@ -11,7 +11,7 @@ =20 bool is_swbp_insn(uprobe_opcode_t *insn) { -#ifdef CONFIG_RISCV_ISA_C +#if IS_ENABLED(CONFIG_RISCV_ISA_C) return (*insn & 0xffff) =3D=3D UPROBE_SWBP_INSN; #else return *insn =3D=3D UPROBE_SWBP_INSN; diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 31a392993cb4..e3e501001916 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -176,7 +176,7 @@ void flush_thread(void) fstate_off(current, task_pt_regs(current)); memset(¤t->thread.fstate, 0, sizeof(current->thread.fstate)); #endif -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) /* Reset vector state */ riscv_v_vstate_ctrl_init(current); riscv_v_vstate_off(task_pt_regs(current)); diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index 8e86305831ea..02e310e7e2a2 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -25,10 +25,10 @@ enum riscv_regset { #ifdef CONFIG_FPU REGSET_F, #endif -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) REGSET_V, #endif -#ifdef CONFIG_RISCV_ISA_SUPM +#if IS_ENABLED(CONFIG_RISCV_ISA_SUPM) REGSET_TAGGED_ADDR_CTRL, #endif }; @@ -87,7 +87,7 @@ static int riscv_fpr_set(struct task_struct *target, } #endif =20 -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) static int riscv_vr_get(struct task_struct *target, const struct user_regset *regset, struct membuf to) @@ -155,7 +155,7 @@ static int riscv_vr_set(struct task_struct *target, } #endif =20 -#ifdef CONFIG_RISCV_ISA_SUPM +#if IS_ENABLED(CONFIG_RISCV_ISA_SUPM) static int tagged_addr_ctrl_get(struct task_struct *target, const struct user_regset *regset, struct membuf to) @@ -203,7 +203,7 @@ static const struct user_regset riscv_user_regset[] =3D= { .set =3D riscv_fpr_set, }, #endif -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) [REGSET_V] =3D { USER_REGSET_NOTE_TYPE(RISCV_VECTOR), .align =3D 16, @@ -214,7 +214,7 @@ static const struct user_regset riscv_user_regset[] =3D= { .set =3D riscv_vr_set, }, #endif -#ifdef CONFIG_RISCV_ISA_SUPM +#if IS_ENABLED(CONFIG_RISCV_ISA_SUPM) [REGSET_TAGGED_ADDR_CTRL] =3D { USER_REGSET_NOTE_TYPE(RISCV_TAGGED_ADDR_CTRL), .n =3D 1, diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 08378fea3a11..532d64f2f539 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -68,7 +68,7 @@ static long save_fp_state(struct pt_regs *regs, #define restore_fp_state(task, regs) (0) #endif =20 -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) =20 static long save_v_state(struct pt_regs *regs, void __user **sc_vec) { diff --git a/arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S b/arch/risc= v/kernel/tests/kprobes/test-kprobes-asm.S index b951d0f12482..0a94826726be 100644 --- a/arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S +++ b/arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S @@ -100,7 +100,7 @@ test_kprobes_branch_addr8: .option pop SYM_FUNC_END(test_kprobes_branch) =20 -#ifdef CONFIG_RISCV_ISA_C +#if IS_ENABLED(CONFIG_RISCV_ISA_C) =20 SYM_FUNC_START(test_kprobes_c_j) li a0, 0 @@ -196,7 +196,7 @@ SYM_DATA_START(test_kprobes_addresses) RISCV_PTR test_kprobes_branch_addr6 RISCV_PTR test_kprobes_branch_addr7 RISCV_PTR test_kprobes_branch_addr8 -#ifdef CONFIG_RISCV_ISA_C +#if IS_ENABLED(CONFIG_RISCV_ISA_C) RISCV_PTR test_kprobes_branch_c_j_addr1 RISCV_PTR test_kprobes_branch_c_j_addr2 RISCV_PTR test_kprobes_c_jr_addr1 @@ -218,7 +218,7 @@ SYM_DATA_START(test_kprobes_functions) RISCV_PTR test_kprobes_jalr RISCV_PTR test_kprobes_auipc RISCV_PTR test_kprobes_branch -#ifdef CONFIG_RISCV_ISA_C +#if IS_ENABLED(CONFIG_RISCV_ISA_C) RISCV_PTR test_kprobes_c_j RISCV_PTR test_kprobes_c_jr RISCV_PTR test_kprobes_c_jalr diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c index 05f3cc2d8e31..562e0a727423 100644 --- a/arch/riscv/kvm/vcpu_vector.c +++ b/arch/riscv/kvm/vcpu_vector.c @@ -15,7 +15,7 @@ #include #include =20 -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu) { unsigned long *isa =3D vcpu->arch.isa; diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index bbc031124974..0df8ba0d3b77 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -10,11 +10,17 @@ lib-y +=3D strncmp.o endif lib-y +=3D csum.o ifeq ($(CONFIG_MMU), y) -lib-$(CONFIG_RISCV_ISA_V) +=3D uaccess_vector.o +ifneq ($(filter y m,$(CONFIG_RISCV_ISA_V)),) +lib-y +=3D uaccess_vector.o +endif endif lib-$(CONFIG_MMU) +=3D uaccess.o lib-$(CONFIG_64BIT) +=3D tishift.o -lib-$(CONFIG_RISCV_ISA_ZICBOZ) +=3D clear_page.o +ifneq ($(filter y m,$(CONFIG_RISCV_ISA_ZICBOZ)),) +lib-y +=3D clear_page.o +endif obj-$(CONFIG_FUNCTION_ERROR_INJECTION) +=3D error-inject.o -lib-$(CONFIG_RISCV_ISA_V) +=3D xor.o -lib-$(CONFIG_RISCV_ISA_V) +=3D riscv_v_helpers.o +ifneq ($(filter y m,$(CONFIG_RISCV_ISA_V)),) +lib-y +=3D xor.o +lib-y +=3D riscv_v_helpers.o +endif diff --git a/arch/riscv/lib/strcmp.S b/arch/riscv/lib/strcmp.S index 65027e742af1..82ea8807f8b8 100644 --- a/arch/riscv/lib/strcmp.S +++ b/arch/riscv/lib/strcmp.S @@ -44,7 +44,7 @@ SYM_FUNC_START(strcmp) * The code was published as part of the bitmanip manual * in Appendix A. */ -#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) +#if IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZB= B) strcmp_zbb: =20 .option push diff --git a/arch/riscv/lib/strlen.S b/arch/riscv/lib/strlen.S index eb4d2b7ed22b..ec2082991933 100644 --- a/arch/riscv/lib/strlen.S +++ b/arch/riscv/lib/strlen.S @@ -34,7 +34,7 @@ SYM_FUNC_START(strlen) /* * Variant of strlen using the ZBB extension if available */ -#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) +#if IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZB= B) strlen_zbb: =20 #ifdef CONFIG_CPU_BIG_ENDIAN diff --git a/arch/riscv/lib/strncmp.S b/arch/riscv/lib/strncmp.S index 062000c468c8..06bcc33f4529 100644 --- a/arch/riscv/lib/strncmp.S +++ b/arch/riscv/lib/strncmp.S @@ -47,7 +47,7 @@ SYM_FUNC_START(strncmp) /* * Variant of strncmp using the ZBB extension if available */ -#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) +#if IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZB= B) strncmp_zbb: =20 .option push diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index 4efea1b3326c..4579196fce6c 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -13,7 +13,7 @@ .endm =20 SYM_FUNC_START(__asm_copy_to_user) -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_ZVE32X,= CONFIG_RISCV_ISA_V) REG_L t0, riscv_v_usercopy_threshold bltu a2, t0, fallback_scalar_usercopy @@ -41,7 +41,7 @@ SYM_FUNC_START(fallback_scalar_usercopy) SYM_FUNC_END(fallback_scalar_usercopy) =20 SYM_FUNC_START(__asm_copy_to_user_sum_enabled) -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) ALTERNATIVE("j fallback_scalar_usercopy_sum_enabled", "nop", 0, RISCV_ISA= _EXT_ZVE32X, CONFIG_RISCV_ISA_V) REG_L t0, riscv_v_usercopy_threshold bltu a2, t0, fallback_scalar_usercopy_sum_enabled diff --git a/arch/riscv/mm/hugetlbpage.c b/arch/riscv/mm/hugetlbpage.c index 375dd96bb4a0..c15ca4769406 100644 --- a/arch/riscv/mm/hugetlbpage.c +++ b/arch/riscv/mm/hugetlbpage.c @@ -2,7 +2,7 @@ #include #include =20 -#ifdef CONFIG_RISCV_ISA_SVNAPOT +#if IS_ENABLED(CONFIG_RISCV_ISA_SVNAPOT) pte_t huge_ptep_get(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { unsigned long pte_num; diff --git a/lib/raid6/Makefile b/lib/raid6/Makefile index 5be0a4e60ab1..e71e86f8f0db 100644 --- a/lib/raid6/Makefile +++ b/lib/raid6/Makefile @@ -10,7 +10,9 @@ raid6_pq-$(CONFIG_ALTIVEC) +=3D altivec1.o altivec2.o alt= ivec4.o altivec8.o \ raid6_pq-$(CONFIG_KERNEL_MODE_NEON) +=3D neon.o neon1.o neon2.o neon4.o ne= on8.o recov_neon.o recov_neon_inner.o raid6_pq-$(CONFIG_S390) +=3D s390vx8.o recov_s390xc.o raid6_pq-$(CONFIG_LOONGARCH) +=3D loongarch_simd.o recov_loongarch_simd.o -raid6_pq-$(CONFIG_RISCV_ISA_V) +=3D rvv.o recov_rvv.o +ifneq ($(filter y m,$(CONFIG_RISCV_ISA_V)),) +raid6_pq-y +=3D rvv.o recov_rvv.o +endif =20 hostprogs +=3D mktables =20 diff --git a/lib/raid6/algos.c b/lib/raid6/algos.c index 799e0e5eac26..6830202249db 100644 --- a/lib/raid6/algos.c +++ b/lib/raid6/algos.c @@ -74,7 +74,7 @@ const struct raid6_calls * const raid6_algos[] =3D { &raid6_lsx, #endif #endif -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) &raid6_rvvx1, &raid6_rvvx2, &raid6_rvvx4, @@ -113,7 +113,7 @@ const struct raid6_recov_calls *const raid6_recov_algos= [] =3D { &raid6_recov_lsx, #endif #endif -#ifdef CONFIG_RISCV_ISA_V +#if IS_ENABLED(CONFIG_RISCV_ISA_V) &raid6_recov_rvv, #endif &raid6_recov_intx1, --=20 2.43.0 From nobody Tue Dec 16 16:37:33 2025 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94B7630EF69 for ; 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[123.225.39.221]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f283d4733sm10364600c88.17.2025.12.10.08.13.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 08:14:01 -0800 (PST) From: Charlie Jenkins X-Google-Original-From: Charlie Jenkins Date: Wed, 10 Dec 2025 08:13:42 -0800 Subject: [PATCH RFC 05/10] riscv: kconfig: Add zve32x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-profiles-v1-5-315a6ff2ca5a@gmail.com> References: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> In-Reply-To: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Samuel Holland , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Luke Nelson , Xi Wang , Eric Biggers , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765383226; l=1267; i=thecharlesjenkins@gmail.com; s=20240124; h=from:subject:message-id; bh=9M10GOO0wPEhtE1SP1x63n71s2lNJna47O4qmUwYiKQ=; b=28t6i9wcH+p48IMmANOO6dGSWTsicxZlvL4RUCZcLWJXBOifTOA6LWtXCBLQgkZP+a/7/X34W XnSzAobaK+aCyGv8eYPcN60Dt7lQjhIMOjx10YerZrpSmX75F2ZVURi X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=eVndo3OHViAjwuqHqbJB4ZtzJzzvk/r6fUf84tZ3rw4= Add zve32x since has_vector() checks for vector support by looking for this extension. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.extensions | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/riscv/Kconfig.extensions b/arch/riscv/Kconfig.extensions index e3ca147765b1..e400fd5574f7 100644 --- a/arch/riscv/Kconfig.extensions +++ b/arch/riscv/Kconfig.extensions @@ -347,6 +347,7 @@ config RISCV_ISA_V depends on TOOLCHAIN_HAS_V depends on FPU select DYNAMIC_SIGFRAME + select RISCV_ISA_ZVE32X depends on NONPORTABLE || m default m help @@ -359,6 +360,19 @@ config RISCV_ISA_V =20 If you don't know what to do here, say m. =20 +config RISCV_ISA_ZVE32X + tristate "zve32x extension support" + depends on NONPORTABLE || m + default m + help + zve23x is a subset of the vector extension. Can be enabled for minimal = vector support. + + Select "m" for boot-time detection for portability. + + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + + If you don't know what to do here, say m. + config RISCV_ISA_V_DEFAULT_ENABLE bool "Enable userspace Vector by default" depends on RISCV_ISA_V --=20 2.43.0 From nobody Tue Dec 16 16:37:33 2025 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA3ED30DED1 for ; Wed, 10 Dec 2025 16:14:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765383251; cv=none; b=Jcxjvpuid4KZ02v2WY9hR8QisyhILuroK3Ce07ElMMLLqccjLUD30YL5OKBFUqf/QcvMoDuPiU39ALrLXRwfNtIxU6Bcf3I6EkCrBKPT7zHAPpPZY5YiFgZPRzQl8pYGUpcFlvy6DNTC4ErZ2i2KI1vbp0qwnoIm843YWudf6iI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765383251; c=relaxed/simple; bh=PXm4AG2hGsdYLwwyM2sQFSEI0LSfo1j2CNnPg+fTqTA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lxHv0QHZ79211jRvFuxf9fmoQQDeho+Ezl+utnWWJWDmSlIt4l2hviefGuhmcfSjPbCuSh3JDZ5aXRkp6uuO5a0fVwaFfw4le1XNy1u5pGtZ2EXOLlqMQSE//7VGEti/eH7sllrCIZRAp9HExWtwefrRzROYToju6MRF4oQB3Rk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc.com header.i=@rivosinc.com header.b=MKtYkhzY; arc=none smtp.client-ip=209.85.210.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc.com header.i=@rivosinc.com header.b="MKtYkhzY" Received: by mail-pf1-f178.google.com with SMTP id d2e1a72fcca58-7aa2170adf9so5901191b3a.0 for ; Wed, 10 Dec 2025 08:14:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc.com; s=google; t=1765383245; x=1765988045; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jTeBxOv2SMEIJm2X1dOR2xoggDwy3sZYySAZ+VrtZTc=; b=MKtYkhzYB8WGecu/DLdUnYrZru02lVpEl5++RCZ71oxE+oWBb4OJ3HTj8but1J/nVF ytMdAdpX3Ot/9f9CEplMIJSeGOZytIlFHRYlpq40zCzuDZj2fJMy7kTVKq1rzY1psrBq GKo1h1L1WPinXhG4uY3ExGxlweAhfO7CbsTdt/po1GuyzltKL5cXaQg3I8k3mSbzldVj 9K8bAUEhqmH/r4Q2B/9NICp5oBSxfF5+Fjmz0QQz+blY+DMEm/7srkJz7dPvhWd4RgLb +k12RLFo/BKuVIydXXMHwcnlW+wqjFCM4N2S+s00XlDkkG3Xhgr3uYyo/UZHyBEU+oHa RwZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765383245; x=1765988045; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=jTeBxOv2SMEIJm2X1dOR2xoggDwy3sZYySAZ+VrtZTc=; b=Kfz1BghDwpVORUA1P4mMLNIcPsly9GtPiGcYcewHFmhiiny52nmyI0zL62ONNioNgt iW2OZtq4oW5UonXV4cNX0eDb1FyU1lkMd485mfY6QtRIxAgJtzsZzuX6LXgaGp4RqDbr fA11CDazhjqt6SDI3ozcQXFiYR9/gMGuNv9SxmCgEJakRC0eejE/g7Jba0Bpx2AV7ma4 bsiKdZ2UItBWFxnAsaaYdXEjtsHS4zC2ZN6lwQ2jpUjFtAd8ecaKk3duD500b9Qi5lbp GW8f/WHmSgAQBZX1oLQ1BPHqGQNqmemWDsgMLrHxeMARyQVG2O+0lQuv6ylA8H0RYz8h gPbw== X-Forwarded-Encrypted: i=1; AJvYcCXA+WTa02anojbKgxQzq8g/+lx5TuMyij4QTE8YCW5QoXJbmp9YLh+VU2xeFylTUR1fxPQn1M+A+cFxNDU=@vger.kernel.org X-Gm-Message-State: AOJu0YyIfeC7vOwBCXhI6FoN/jMzHk5+uyzeJiKWYuURCiAkeRm3bOiF WcnJuP8ga6zj7E8tgBiAiJePlMJJcR0q5AXynWbqzpnwv/WpNEYTjG2Yozbywvlu5gE= X-Gm-Gg: ASbGnctw+iPRtIjSkGhcfkRAivUoSgaHVLu+0PjYvugrAx6OOW30gnuWxSXjphgW2lz npKHBx/mt3SmzopPPDdXxGDIyw+2r1PTN2pC2z9m6Aom0tM6swlz3ZlqXPxOKAf/vLYMTHlUGR2 BkOsxZCuhabKQQ7PbsuaBYDnGb8hWFXvNdH1yZzrma32v3VIQjaOEYuQ1ZTc/beoZXyS9cuqCAA jxvua8A6t8aoGLvAsuN8Zlq7AY7kPa7Ti/XOygHo4xRpD11LTH9sFbUwEbFjIOBOvCop+WXcT8x vGjsV6ON1Z3UdZVPpRdh/Aw7qX7SF9ASm/oqFh1vrxEGHVXbvJ0bmi3Wj0vbr0yCau0eVGkv9t4 SPMGwpSfFWF1zodcdkcw04Yqmrwby7qw+CO6rExAH2qrS1bLBw90aQCEABWEmG4UiDu3EAOINn3 hR1aRJrQnR8gVh7DtrEfSOD/PPe5pTaHR3B6b8P+YNDnf/szyz+gRfazF/FviU4uX3hFsP9WVW2 MJXcoPGufkZ X-Google-Smtp-Source: AGHT+IEnH2JCzQBXPTwYTipTGasI37dEmVRsGwF2tVJaArwKUp9ryzfhwoIxbl9WMS+Ke/jAN7fjLA== X-Received: by 2002:a05:7022:6289:b0:11b:9e5e:1a40 with SMTP id a92af1059eb24-11f2967d192mr2057361c88.15.1765383244756; Wed, 10 Dec 2025 08:14:04 -0800 (PST) Received: from [127.0.1.1] (p7838222-ipoefx.ipoe.ocn.ne.jp. [123.225.39.221]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f283d4733sm10364600c88.17.2025.12.10.08.14.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 08:14:04 -0800 (PST) From: Charlie Jenkins X-Google-Original-From: Charlie Jenkins Date: Wed, 10 Dec 2025 08:13:43 -0800 Subject: [PATCH RFC 06/10] riscv: Makefile: Add enabled extensions to compiler flags Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-profiles-v1-6-315a6ff2ca5a@gmail.com> References: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> In-Reply-To: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Samuel Holland , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Luke Nelson , Xi Wang , Eric Biggers , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765383226; l=7578; i=thecharlesjenkins@gmail.com; s=20240124; h=from:subject:message-id; bh=PXm4AG2hGsdYLwwyM2sQFSEI0LSfo1j2CNnPg+fTqTA=; b=0kvyOA3UMAW8IGwuP4q/SaToDXNlSkfb6ktLVtbx8kmnGX7Cnn9oikqQ51/0sCC+HvEusUnER HzDVolRAfIsAveQLbAR9G8+jDUiBSxWBDEXdwGEg/9W6pYn//C48M0u X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=eVndo3OHViAjwuqHqbJB4ZtzJzzvk/r6fUf84tZ3rw4= Build an optimized kernel with all extensions that the hardware is expected to support. Extensions that might be supported by hardware and will be detected at runtime will be added to the assembler flags but not to the compiler flags. Signed-off-by: Charlie Jenkins --- arch/riscv/Makefile | 135 ++++++++++++++++++++++++++++++++++++++++++++----= ---- 1 file changed, 116 insertions(+), 19 deletions(-) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index ef1a7b1bffe8..efe43537e984 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -57,37 +57,134 @@ ifeq ($(CONFIG_SHADOW_CALL_STACK),y) KBUILD_LDFLAGS +=3D --no-relax-gp endif =20 -# ISA string setting -riscv-march-y :=3D $(CONFIG_ARCH) -riscv-march-$(CONFIG_FPU) :=3D $(riscv-march-y)fd -riscv-march-$(CONFIG_RISCV_ISA_C) :=3D $(riscv-march-y)c -riscv-march-$(CONFIG_RISCV_ISA_V) :=3D $(riscv-march-y)v +# Handling of riscv extensions +# There are a couple of considerations when enabling extensions: +# 1. Does the toolchain support the extension? +# 2. Is the extension supported by the hardware the kernel will run on? +# 3. Does the extension have registers that need to be save/restored= on +# a context switch? +# 4. Is this extension emitted by the compiler or only by hand-coded +# assembly? +# +# This section has helpers to support extensions with varying answers to t= hese questions. +# +# The compiler will be allowed to emit an extension if all of the following +# are satisfied: +# - The extension is a "stateless" extension (i.e. doesn't introduce= additional +# registers) +# - The extension is supported by the toolchain (selected by CONFIG_TOOLCH= AIN_HAS_*) +# - The extension is enabled for use in the kernel (selected by CONFIG_RIS= CV_ISA_*=3Dy) +# +# Assembler support for the instruction will be added if the extension is +# supported by the assembler (selected by CONFIG_TOOLCHAIN_HAS_*). + +# Extensions that the compiler is allowed to emit anywhere. +riscv-march-standard :=3D $(CONFIG_ARCH) + +# Extensions that the compiler is allowed to emit in FPU contexts. +# This should riscv-march-standard plus the FPU-specific extensions. +riscv-march-fpu :=3D $(CONFIG_ARCH) + +# All extensions supported by the kernel. Some of these extensions require +# special care so they cannot be arbitrarily emitted by the compiler. +riscv-march-full :=3D $(CONFIG_ARCH) + +# Returns the instruction if it is supported, returns the empty string oth= erwise. +# An instruction is only "supported" if RISCV_ISA_*!=3Dn. +# An instruction that is "supported" can be emitted through alternatives, = but an instruction that is +# "enabled" can be emitted arbitrarily by the compiler. +# Arguments: +# $1 - name of extension +# $2 - extension delimiter. Should be empty for base extensions and +# underscore otherwise +extension_supported=3D$(if $(and $(or $(filter $(CONFIG_RISCV_ISA_$(shell = echo $1 | tr a-z A-Z)),m), $(filter $(CONFIG_RISCV_ISA_$(shell echo $1 | tr= a-z A-Z)),y)), $(filter $(CONFIG_TOOLCHAIN_HAS_$(shell echo $1 | tr a-z A-= Z)),y)),$2$1) + +# Returns the instruction if it is enabled, returns the empty string other= wise. +# An instruction is only "enabled" if RISCV_ISA_*=3Dy. +# An instruction that is "supported" can be emitted through alternatives, = but an instruction that is +# "enabled" can be emitted arbitrarily by the compiler. +# Arguments: +# $1 - name of extension +# $2 - extension delimiter. Should be empty for base extensions and +# underscore otherwise +extension_enabled=3D$(if $(and $(filter $(CONFIG_RISCV_ISA_$(shell echo $1= | tr a-z A-Z)),y), $(filter $(CONFIG_TOOLCHAIN_HAS_$(shell echo $1 | tr a-= z A-Z)),y)),$2$1) + +# Use this macro to add support for an extension that is stateless. +# A "stateless" extension is one that does not add additional registers. +# +# Arguments: +# $1 - name of extension +# $2 - extension delimiter. Should be empty for base extensions and +# underscore otherwise +define add_stateless_extension +$(eval riscv-march-standard=3D$(riscv-march-standard)$(call extension_enab= led,$1,$2)) +$(eval riscv-march-fpu=3D$(riscv-march-fpu)$(call extension_enabled,$1,$2)) +$(eval riscv-march-full=3D$(riscv-march-full)$(call extension_supported,$1= ,$2)) +endef =20 -ifneq ($(CONFIG_RISCV_ISA_C),y) - KBUILD_RUSTFLAGS +=3D -Ctarget-feature=3D-c -endif +# Use this macro to add support for a floating point extension. +# Floating point extensions are not able to be used in all contexts, so th= ey +# are kept separate. +# +# Arguments: +# $1 - name of extension +# $2 - extension delimiter. Should be empty for base extensions and +# underscore otherwise +define add_fpu_extension +$(eval riscv-march-fpu=3D$(riscv-march-fpu)$(call extension_enabled,$1,$2)) +$(eval riscv-march-full=3D$(riscv-march-full)$(call extension_supported,$1= ,$2)) +endef + +# Use this macro to add support for an extension that is stateful. +# A "stateful" extension is one that adds additional registers, or requires +# hand-coded assembly (instead of being arbitrarily emitted by the compile= r). +# +# Arguments: +# $1 - name of extension +# $2 - extension delimiter. Should be empty for base extensions and +# underscore otherwise +define add_stateful_extension +$(eval riscv-march-full=3D$(riscv-march-full)$(call extension_supported,$1= ,$2)) +endef + +# Extensions must be added in the canonical ISA string order + +# Base extensions +$(call add_fpu_extension,f) +$(call add_fpu_extension,d) +$(call add_stateless_extension,c) +$(call add_stateful_extension,v) =20 ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC KBUILD_CFLAGS +=3D -Wa,-misa-spec=3D2.2 KBUILD_AFLAGS +=3D -Wa,-misa-spec=3D2.2 else -riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) :=3D $(riscv= -march-y)_zicsr_zifencei +$(call add_stateless_extension,zicsr,_) +$(call add_stateless_extension,zifencei,_) endif =20 -# Check if the toolchain supports Zacas -riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) :=3D $(riscv-march-y)_zacas +# Standard extensions +$(call add_stateless_extension,zabha,_) +$(call add_stateless_extension,zacas,_) +$(call add_stateless_extension,zba,_) +$(call add_stateless_extension,zbb,_) +$(call add_stateless_extension,zbc,_) +$(call add_stateless_extension,zbkb,_) =20 -# Check if the toolchain supports Zabha -riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZABHA) :=3D $(riscv-march-y)_zabha +ifneq ($(CONFIG_RISCV_ISA_C),y) + KBUILD_RUSTFLAGS +=3D -Ctarget-feature=3D-c +endif =20 -# Remove F,D,V from isa string for all. Keep extensions between "fd" and "= v" by -# matching non-v and non-multi-letter extensions out with the filter ([^v_= ]*) -KBUILD_CFLAGS +=3D -march=3D$(shell echo $(riscv-march-y) | sed -E 's/(rv3= 2ima|rv64ima)fd([^v_]*)v?/\1\2/') +# Only include extensions that do not introduce additional state. This +# "additional state" most often means extra registers. +KBUILD_CFLAGS +=3D -march=3D$(riscv-march-standard) =20 -KBUILD_AFLAGS +=3D -march=3D$(riscv-march-y) +# Make all instructions available to the assembler +KBUILD_AFLAGS +=3D -march=3D$(riscv-march-full) =20 -# For C code built with floating-point support, exclude V but keep F and D. -CC_FLAGS_FPU :=3D -march=3D$(shell echo $(riscv-march-y) | sed -E 's/(rv3= 2ima|rv64ima)([^v_]*)v?/\1\2/') +# As an extension of the "standard" march string, include any extensions t= hat +# are able to be used when the FPU is enabled. +CC_FLAGS_FPU :=3D -march=3D$(riscv-march-fpu) =20 KBUILD_CFLAGS +=3D -mno-save-restore =20 --=20 2.43.0 From nobody Tue Dec 16 16:37:33 2025 Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 240442D321B for ; Wed, 10 Dec 2025 16:14:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[123.225.39.221]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f283d4733sm10364600c88.17.2025.12.10.08.14.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 08:14:07 -0800 (PST) From: Charlie Jenkins X-Google-Original-From: Charlie Jenkins Date: Wed, 10 Dec 2025 08:13:44 -0800 Subject: [PATCH RFC 07/10] riscv: kconfig: Make vendor extensions tristate Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-profiles-v1-7-315a6ff2ca5a@gmail.com> References: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> In-Reply-To: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Samuel Holland , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Luke Nelson , Xi Wang , Eric Biggers , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765383226; l=3908; i=thecharlesjenkins@gmail.com; s=20240124; h=from:subject:message-id; bh=oW54abbRysZHDMCyrE264IqhApYvMrvVoe7o3AdfEeo=; b=A2kGAVqVMr9wlv2Sb6EOoVmU3H2XBDyOEevuJaXq2h60+M/QGKVqHoFbj1fYiEmEFHrJZNmpb cNjKpYZs9+wCrNUE+zxNnJ2VpNB1Ny3yB+T8TQSEk7e59UdSxzTs6DL X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=eVndo3OHViAjwuqHqbJB4ZtzJzzvk/r6fUf84tZ3rw4= Adjust the vendor extensions to use the same tristate selection as the standard extensions. This will allow the vendor extensions to use the same code paths as the standard extensions for discovery and optimization. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.vendor | 25 ++++++++++++++++++++++--- arch/riscv/kernel/vendor_extensions/Makefile | 22 +++++++++++++++------- drivers/perf/Kconfig | 2 +- 3 files changed, 38 insertions(+), 11 deletions(-) diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index 3c1f92e406c3..74155c5b642f 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -14,6 +14,20 @@ config RISCV_ISA_VENDOR_EXT_ANDES requested by hardware probing to be ignored. =20 If you don't know what to do here, say Y. + +config RISCV_ISA_XANDESPMU + tristate "xandespmu extension support" + depends on NONPORTABLE || m + default m + help + The Andes cores implement the PMU overflow extension very + similar to the standard Sscofpmf and Smcntrpmf extension. + + Select "m" for boot-time detection for portability. + + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + + If you don't know what to do here, say m. endmenu =20 menu "MIPS" @@ -55,17 +69,22 @@ config RISCV_ISA_VENDOR_EXT_THEAD If you don't know what to do here, say Y. =20 config RISCV_ISA_XTHEADVECTOR - bool "xtheadvector extension support" + tristate "xtheadvector extension support" depends on RISCV_ISA_VENDOR_EXT_THEAD depends on RISCV_ISA_V depends on FPU - default y + depends on NONPORTABLE || m + default m help Say N here if you want to disable all xtheadvector related procedures in the kernel. This will disable vector for any T-Head board that contains xtheadvector rather than the standard vector. =20 - If you don't know what to do here, say Y. + Select "m" for boot-time detection for portability. + + Select "y" for compile-time detection for optimization. Only available= with NONPORTABLE. + + If you don't know what to do here, say m. endmenu =20 endmenu diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kern= el/vendor_extensions/Makefile index bf116c82b6bd..e5ef5219a050 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -1,9 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only =20 -obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) +=3D andes.o -obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS) +=3D mips.o -obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS) +=3D mips_hwprobe.o -obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) +=3D sifive.o -obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) +=3D sifive_hwprobe.o -obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead.o -obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead_hwprobe.o +ifneq ($(filter y m,$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES)),) +obj-y +=3D andes.o +endif +ifneq ($(filter y m,$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS)),) +obj-y +=3D mips.o +obj-y +=3D mips_hwprobe.o +endif +ifneq ($(filter y m,$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)),) +obj-y +=3D sifive.o +obj-y +=3D sifive_hwprobe.o +endif +ifneq ($(filter y m,$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD)),) +obj-y +=3D thead.o +obj-y +=3D thead_hwprobe.o +endif diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 638321fc9800..dfbd02d28c3f 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -117,7 +117,7 @@ config STARFIVE_STARLINK_PMU =20 config ANDES_CUSTOM_PMU bool "Andes custom PMU support" - depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI + depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI && RISCV_IS= A_XANDESPMU default y help The Andes cores implement the PMU overflow extension very --=20 2.43.0 From nobody Tue Dec 16 16:37:33 2025 Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52D9C2C11C6 for ; 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[123.225.39.221]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f283d4733sm10364600c88.17.2025.12.10.08.14.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 08:14:09 -0800 (PST) From: Charlie Jenkins X-Google-Original-From: Charlie Jenkins Date: Wed, 10 Dec 2025 08:13:45 -0800 Subject: [PATCH RFC 08/10] riscv: Optimize cpufeature macros for extension assumptions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-profiles-v1-8-315a6ff2ca5a@gmail.com> References: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> In-Reply-To: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Samuel Holland , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Luke Nelson , Xi Wang , Eric Biggers , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765383226; l=40935; i=thecharlesjenkins@gmail.com; s=20240124; h=from:subject:message-id; bh=9Yg7eiHbbMZ97dsT8VHvna+aVc6IjSnWR+fQ05yjHVk=; b=y1deecj3NNapOGbWLEuPBFoCBQliBa2EOcR3LX7oavNutDeqP4AeJjwFcb+33KWWihxDcdVt+ bVMgcYQIoMDC9P2W0po2ZJNxohQ+34reM44iw9rZ1RJUCVfj51ak4Uh X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=eVndo3OHViAjwuqHqbJB4ZtzJzzvk/r6fUf84tZ3rw4= When an extension is compiled into the kernel as "y" in Kconfig, the runtime alternative patching, along with the nops required for that, can be removed. Refactor the riscv_has_extension* functions and macros to be able to account for an extension being selected as "y", "m", or "n" and emit the optimal code in each case. The functions are converted into macros so that only code for the selected "y"/"m"/"n" case will be emited. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/arch_hweight.h | 4 +- arch/riscv/include/asm/archrandom.h | 2 +- arch/riscv/include/asm/bitops.h | 8 +- arch/riscv/include/asm/checksum.h | 2 +- arch/riscv/include/asm/cmpxchg.h | 12 +-- arch/riscv/include/asm/cpufeature-macros.h | 136 +++++++++++++++++++------= ---- arch/riscv/include/asm/cpufeature.h | 42 ++++----- arch/riscv/include/asm/pgtable.h | 6 +- arch/riscv/include/asm/swab.h | 2 +- arch/riscv/include/asm/switch_to.h | 4 +- arch/riscv/include/asm/uaccess.h | 2 +- arch/riscv/include/asm/vector.h | 5 +- arch/riscv/include/asm/vendor_extensions.h | 113 +++++++++++++----------- arch/riscv/kernel/cpufeature.c | 6 +- arch/riscv/kernel/pi/archrandom_early.c | 1 + arch/riscv/kernel/process.c | 8 +- arch/riscv/kernel/suspend.c | 8 +- arch/riscv/kvm/tlb.c | 2 +- arch/riscv/kvm/vcpu.c | 10 +-- arch/riscv/kvm/vcpu_onereg.c | 6 +- arch/riscv/lib/csum.c | 6 +- arch/riscv/mm/pgtable.c | 2 +- arch/riscv/mm/tlbflush.c | 2 +- arch/riscv/net/bpf_jit.h | 2 +- drivers/perf/riscv_pmu_sbi.c | 3 +- lib/crc/riscv/crc-t10dif.h | 2 +- lib/crc/riscv/crc32.h | 8 +- lib/crc/riscv/crc64.h | 4 +- 28 files changed, 228 insertions(+), 180 deletions(-) diff --git a/arch/riscv/include/asm/arch_hweight.h b/arch/riscv/include/asm= /arch_hweight.h index f3c0831beefc..95fda1d4e1ac 100644 --- a/arch/riscv/include/asm/arch_hweight.h +++ b/arch/riscv/include/asm/arch_hweight.h @@ -21,7 +21,7 @@ static __always_inline unsigned int __arch_hweight32(unsi= gned int w) { if (!(IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && - riscv_has_extension_likely(RISCV_ISA_EXT_ZBB))) + riscv_has_extension_likely(ZBB))) return __sw_hweight32(w); =20 asm (".option push\n" @@ -48,7 +48,7 @@ static __always_inline unsigned long __arch_hweight64(__u= 64 w) { if (!(IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && - riscv_has_extension_likely(RISCV_ISA_EXT_ZBB))) + riscv_has_extension_likely(ZBB))) return __sw_hweight64(w); =20 asm (".option push\n" diff --git a/arch/riscv/include/asm/archrandom.h b/arch/riscv/include/asm/a= rchrandom.h index 5345360adfb9..44e97115afd6 100644 --- a/arch/riscv/include/asm/archrandom.h +++ b/arch/riscv/include/asm/archrandom.h @@ -63,7 +63,7 @@ static inline size_t __must_check arch_get_random_seed_lo= ngs(unsigned long *v, s * If Zkr is supported and csr_seed_long succeeds, we return one long * worth of entropy. */ - if (riscv_has_extension_likely(RISCV_ISA_EXT_ZKR) && csr_seed_long(v)) + if (riscv_has_extension_likely(ZKR) && csr_seed_long(v)) return 1; =20 return 0; diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitop= s.h index 238092125c11..52271507598a 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -47,7 +47,7 @@ =20 static __always_inline __attribute_const__ unsigned long variable__ffs(uns= igned long word) { - if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + if (!riscv_has_extension_likely(ZBB)) return generic___ffs(word); =20 asm volatile (".option push\n" @@ -72,7 +72,7 @@ static __always_inline __attribute_const__ unsigned long = variable__ffs(unsigned =20 static __always_inline __attribute_const__ unsigned long variable__fls(uns= igned long word) { - if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + if (!riscv_has_extension_likely(ZBB)) return generic___fls(word); =20 asm volatile (".option push\n" @@ -97,7 +97,7 @@ static __always_inline __attribute_const__ unsigned long = variable__fls(unsigned =20 static __always_inline __attribute_const__ int variable_ffs(int x) { - if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + if (!riscv_has_extension_likely(ZBB)) return generic_ffs(x); =20 if (!x) @@ -125,7 +125,7 @@ static __always_inline __attribute_const__ int variable= _ffs(int x) =20 static __always_inline int variable_fls(unsigned int x) { - if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + if (!riscv_has_extension_likely(ZBB)) return generic_fls(x); =20 if (!x) diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/che= cksum.h index 945cce34be92..e747af23eea2 100644 --- a/arch/riscv/include/asm/checksum.h +++ b/arch/riscv/include/asm/checksum.h @@ -51,7 +51,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsig= ned int ihl) */ if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && - riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) { + riscv_has_extension_likely(ZBB)) { unsigned long fold_temp; =20 if (IS_ENABLED(CONFIG_32BIT)) { diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpx= chg.h index 0fee37752098..7ee50741c4dd 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -20,7 +20,7 @@ swap_append, r, p, n) \ ({ \ if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA) && \ - riscv_has_extension_unlikely(RISCV_ISA_EXT_ZABHA)) { \ + riscv_has_extension_unlikely(ZABHA)) { \ __asm__ __volatile__ ( \ prepend \ " amoswap" swap_sfx " %0, %z2, %1\n" \ @@ -135,8 +135,8 @@ if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA) && \ IS_ENABLED(CONFIG_RISCV_ISA_ZACAS) && \ IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZACAS) && \ - riscv_has_extension_unlikely(RISCV_ISA_EXT_ZABHA) && \ - riscv_has_extension_unlikely(RISCV_ISA_EXT_ZACAS)) { \ + riscv_has_extension_unlikely(ZABHA) && \ + riscv_has_extension_unlikely(ZACAS)) { \ r =3D o; \ \ __asm__ __volatile__ ( \ @@ -183,7 +183,7 @@ ({ \ if (IS_ENABLED(CONFIG_RISCV_ISA_ZACAS) && \ IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZACAS) && \ - riscv_has_extension_unlikely(RISCV_ISA_EXT_ZACAS)) { \ + riscv_has_extension_unlikely(ZACAS)) { \ r =3D o; \ \ __asm__ __volatile__ ( \ @@ -320,7 +320,7 @@ =20 #if defined(CONFIG_64BIT) && defined(CONFIG_RISCV_ISA_ZACAS) && defined(CO= NFIG_TOOLCHAIN_HAS_ZACAS) =20 -#define system_has_cmpxchg128() riscv_has_extension_unlikely(RISCV_= ISA_EXT_ZACAS) +#define system_has_cmpxchg128() riscv_has_extension_unlikely(ZACAS) =20 union __u128_halves { u128 full; @@ -373,7 +373,7 @@ static __always_inline void __cmpwait(volatile void *pt= r, u32 *__ptr32b; ulong __s, __val, __mask; =20 - if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZAWRS)) { + if (!riscv_has_extension_likely(ZAWRS)) { ALT_RISCV_PAUSE(); return; } diff --git a/arch/riscv/include/asm/cpufeature-macros.h b/arch/riscv/includ= e/asm/cpufeature-macros.h index a8103edbf51f..d16bbbeb6a44 100644 --- a/arch/riscv/include/asm/cpufeature-macros.h +++ b/arch/riscv/include/asm/cpufeature-macros.h @@ -9,58 +9,100 @@ #include #include =20 +#include + #define STANDARD_EXT 0 =20 +#define _RISCV_EXTENSION_BEHAVIOR_MODULE_RET_1(vendor, ext, id, fallback, = alternative) \ + ({ \ + __label__ alt, done; \ + __typeof__(fallback) ret; \ + asm goto(ALTERNATIVE("j %l[alt]", "nop", vendor, id, 1) : : : : alt); \ + ret =3D fallback; \ + goto done; \ +alt: \ + ret =3D alternative; \ +done: \ + ret; \ + }) + +#define _RISCV_EXTENSION_BEHAVIOR_MODULE_RET_0(vendor, ext, id, fallback, = alternative) \ + ({ \ + __label__ alt, done; \ + __typeof__(fallback) ret; \ + asm goto(ALTERNATIVE("nop", "j %l[alt]", vendor, id, 1) : : : : alt); \ + ret =3D fallback; \ + goto done; \ +alt: \ + ret =3D alternative; \ +done: \ + ret; \ + }) + +/* Check if extension is required */ +#define _RISCV_DISPATCH_BUILTIN_1(vendor, ext, id, fallback, alternative, = likely, suffix) alternative + +#define _RISCV_DISPATCH_BUILTIN_0(vendor, ext, id, fallback, alternative, = likely, suffix) \ + _RISCV_DISPATCH_MODULE_CHECK(vendor, ext, id, fallback, alternative, like= ly, suffix) + +/* Check if extension is optional */ +#define _RISCV_DISPATCH_MODULE_CHECK(vendor, ext, id, fallback, alternativ= e, likely, suffix) \ + CONCATENATE(_RISCV_DISPATCH_MODULE_, IS_MODULE(CONFIG_RISCV_ISA_##ext))( = \ + vendor, ext, id, fallback, alternative, likely, suffix) + +#define _RISCV_DISPATCH_MODULE_1(vendor, ext, id, fallback, alternative, l= ikely, suffix) \ + _RISCV_EXTENSION_BEHAVIOR_MODULE_##suffix##likely(vendor, ext, id, fallba= ck, alternative) + +/* Extension is not selected, use the fallback */ +#define _RISCV_DISPATCH_MODULE_0(vendor, ext, id, fallback, alternative, l= ikely, suffix) fallback + +/* + * Three possibilities: + * 1. Kernel is compiled with RISCV_ISA_EXT_ext=3Dy --> "alternative" will= be used + * 2. Kernel is compiled with RISCV_ISA_EXT_ext=3Dm --> "alternative" will= be + * used if extension detected at boot, otherwise "fallback" will be use= d. + * 3. Kernel is compiled with RISCV_ISA_EXT_ext=3Dn --> "fallback" will be= used. + */ +#define _RISCV_HAS_EXTENSION_ALTERNATIVE_RET(vendor, ext, id, likely) = \ + CONCATENATE(_RISCV_DISPATCH_BUILTIN_, IS_BUILTIN(CONFIG_RISCV_ISA_##ext))= ( \ + vendor, ext, id, false, true, likely, RET_) + bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsi= gned int bit); #define riscv_isa_extension_available(isa_bitmap, ext) \ __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) =20 -static __always_inline bool __riscv_has_extension_likely(const unsigned lo= ng vendor, - const unsigned long ext) -{ - asm goto(ALTERNATIVE("j %l[l_no]", "nop", %[vendor], %[ext], 1) - : - : [vendor] "i" (vendor), [ext] "i" (ext) - : - : l_no); - - return true; -l_no: - return false; -} - -static __always_inline bool __riscv_has_extension_unlikely(const unsigned = long vendor, - const unsigned long ext) -{ - asm goto(ALTERNATIVE("nop", "j %l[l_yes]", %[vendor], %[ext], 1) - : - : [vendor] "i" (vendor), [ext] "i" (ext) - : - : l_yes); - - return false; -l_yes: - return true; -} - -static __always_inline bool riscv_has_extension_unlikely(const unsigned lo= ng ext) -{ - compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_= MAX"); - - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) - return __riscv_has_extension_unlikely(STANDARD_EXT, ext); - - return __riscv_isa_extension_available(NULL, ext); -} - -static __always_inline bool riscv_has_extension_likely(const unsigned long= ext) -{ - compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_= MAX"); - - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) - return __riscv_has_extension_likely(STANDARD_EXT, ext); - - return __riscv_isa_extension_available(NULL, ext); -} +#define __riscv_has_extension_likely(vendor, ext, id) \ + _RISCV_HAS_EXTENSION_ALTERNATIVE_RET(vendor, ext, id, 1) + +#define __riscv_has_extension_unlikely(vendor, ext, id) \ + _RISCV_HAS_EXTENSION_ALTERNATIVE_RET(vendor, ext, id, 0) + +#define riscv_has_extension_unlikely(ext) \ + ({ \ + bool has_extension; \ + compiletime_assert(RISCV_ISA_EXT_##ext < RISCV_ISA_EXT_MAX, \ + "ext must be < RISCV_ISA_EXT_MAX"); \ + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) \ + has_extension =3D __riscv_has_extension_unlikely(STANDARD_EXT, ext, \ + RISCV_ISA_EXT_##ext); \ + else \ + has_extension =3D \ + __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_##ext); \ + has_extension; \ + }) + +#define riscv_has_extension_likely(ext) \ + ({ \ + bool has_extension; \ + compiletime_assert(RISCV_ISA_EXT_##ext < RISCV_ISA_EXT_MAX, \ + "ext must be < RISCV_ISA_EXT_MAX"); \ + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) \ + has_extension =3D __riscv_has_extension_likely(STANDARD_EXT, ext, \ + RISCV_ISA_EXT_##ext); \ + else \ + has_extension =3D \ + __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_##ext); \ + has_extension; \ + }) =20 #endif /* _ASM_CPUFEATURE_MACROS_H */ diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 62837fa981e8..e7903f52bbc5 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -130,26 +130,26 @@ extern const size_t riscv_isa_ext_count; extern bool riscv_isa_fallback; =20 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); -static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const = unsigned long ext) -{ - compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_= MAX"); - - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && - __riscv_has_extension_likely(STANDARD_EXT, ext)) - return true; - - return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); -} - -static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, cons= t unsigned long ext) -{ - compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_= MAX"); - - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && - __riscv_has_extension_unlikely(STANDARD_EXT, ext)) - return true; - - return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); -} +#define riscv_cpu_has_extension_likely(cpu, ext) \ + ({ \ + bool has_extension; \ + compiletime_assert(RISCV_ISA_EXT_##ext < RISCV_ISA_EXT_MAX, \ + "ext must be < RISCV_ISA_EXT_MAX"); \ + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && \ + __riscv_has_extension_likely(STANDARD_EXT, ext, RISCV_ISA_EXT_##ext)= ) \ + return true; \ + return __riscv_isa_extension_available(hart_isa[cpu].isa, RISCV_ISA_EXT_= ##ext); \ + }) + +#define riscv_cpu_has_extension_unlikely(cpu, ext) \ + ({ \ + bool has_extension; \ + compiletime_assert(RISCV_ISA_EXT_##ext < RISCV_ISA_EXT_MAX, \ + "ext must be < RISCV_ISA_EXT_MAX"); \ + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && \ + __riscv_has_extension_unlikely(STANDARD_EXT, ext, RISCV_ISA_EXT_##ex= t)) \ + return true; \ + return __riscv_isa_extension_available(hart_isa[cpu].isa, RISCV_ISA_EXT_= ##ext); \ + }) =20 #endif diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index 45b2021eb2c1..85dd7d5e5278 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -293,7 +293,7 @@ static inline pte_t pud_pte(pud_t pud) =20 static __always_inline bool has_svnapot(void) { - return riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT); + return riscv_has_extension_likely(SVNAPOT); } =20 static inline unsigned long pte_napot(pte_t pte) @@ -501,7 +501,7 @@ static inline void update_mmu_cache_range(struct vm_fau= lt *vmf, * a bounded timeframe, so when the uarch does not cache invalid * entries, we don't have to do anything. */ - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVVPTC)) + if (riscv_has_extension_unlikely(SVVPTC)) return; =20 /* @@ -663,7 +663,7 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _pr= ot) #define arch_has_hw_pte_young arch_has_hw_pte_young static inline bool arch_has_hw_pte_young(void) { - return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); + return riscv_has_extension_unlikely(SVADU); } =20 /* diff --git a/arch/riscv/include/asm/swab.h b/arch/riscv/include/asm/swab.h index c1da22aa1326..c87be2477ff4 100644 --- a/arch/riscv/include/asm/swab.h +++ b/arch/riscv/include/asm/swab.h @@ -35,7 +35,7 @@ ({ \ unsigned long x =3D value; \ \ - if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) { \ + if (riscv_has_extension_likely(ZBB)) { \ asm volatile (".option push\n" \ ".option arch,+zbb\n" \ "rev8 %0, %1\n" \ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index ff35a4d04f85..a2cf333097cd 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -60,8 +60,8 @@ static inline void __switch_to_fpu(struct task_struct *pr= ev, =20 static __always_inline bool has_fpu(void) { - return riscv_has_extension_likely(RISCV_ISA_EXT_F) || - riscv_has_extension_likely(RISCV_ISA_EXT_D); + return riscv_has_extension_likely(F) || + riscv_has_extension_likely(D); } #else static __always_inline bool has_fpu(void) { return false; } diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uacc= ess.h index f5f4f7f85543..4a07ee5d3084 100644 --- a/arch/riscv/include/asm/uaccess.h +++ b/arch/riscv/include/asm/uaccess.h @@ -15,7 +15,7 @@ #ifdef CONFIG_RISCV_ISA_SUPM static inline unsigned long __untagged_addr_remote(struct mm_struct *mm, u= nsigned long addr) { - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SUPM)) { + if (riscv_has_extension_unlikely(SUPM)) { u8 pmlen =3D mm->context.pmlen; =20 /* Virtual addresses are sign-extended; physical addresses are zero-exte= nded. */ diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vecto= r.h index 7a506c780874..3788ba060c1e 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -59,7 +59,7 @@ static inline u32 riscv_v_flags(void) =20 static __always_inline bool has_vector(void) { - return riscv_has_extension_unlikely(RISCV_ISA_EXT_ZVE32X); + return riscv_has_extension_unlikely(ZVE32X); } =20 static __always_inline bool has_xtheadvector_no_alternatives(void) @@ -73,8 +73,7 @@ static __always_inline bool has_xtheadvector_no_alternati= ves(void) static __always_inline bool has_xtheadvector(void) { if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) - return riscv_has_vendor_extension_unlikely(THEAD_VENDOR_ID, - RISCV_ISA_VENDOR_EXT_XTHEADVECTOR); + return riscv_has_vendor_extension_unlikely(THEAD_VENDOR_ID, XTHEADVECTOR= ); else return false; } diff --git a/arch/riscv/include/asm/vendor_extensions.h b/arch/riscv/includ= e/asm/vendor_extensions.h index 7437304a71b9..e536d8342878 100644 --- a/arch/riscv/include/asm/vendor_extensions.h +++ b/arch/riscv/include/asm/vendor_extensions.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright 2024 Rivos, Inc + * Copyright 2024-2025 Rivos, Inc */ =20 #ifndef _ASM_VENDOR_EXTENSIONS_H @@ -48,57 +48,64 @@ bool __riscv_isa_vendor_extension_available(int cpu, un= signed long vendor, unsig __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, \ RISCV_ISA_VENDOR_EXT_##ext) =20 -static __always_inline bool riscv_has_vendor_extension_likely(const unsign= ed long vendor, - const unsigned long ext) -{ - if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) - return false; - - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) - return __riscv_has_extension_likely(vendor, - ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); - - return __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor= , ext); -} - -static __always_inline bool riscv_has_vendor_extension_unlikely(const unsi= gned long vendor, - const unsigned long ext) -{ - if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) - return false; - - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) - return __riscv_has_extension_unlikely(vendor, - ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); - - return __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor= , ext); -} - -static __always_inline bool riscv_cpu_has_vendor_extension_likely(const un= signed long vendor, - int cpu, const unsigned long ext) -{ - if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) - return false; - - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && - __riscv_has_extension_likely(vendor, ext + RISCV_VENDOR_EXT_ALTERNATI= VES_BASE)) - return true; - - return __riscv_isa_vendor_extension_available(cpu, vendor, ext); -} - -static __always_inline bool riscv_cpu_has_vendor_extension_unlikely(const = unsigned long vendor, - int cpu, - const unsigned long ext) -{ - if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) - return false; - - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && - __riscv_has_extension_unlikely(vendor, ext + RISCV_VENDOR_EXT_ALTERNA= TIVES_BASE)) - return true; - - return __riscv_isa_vendor_extension_available(cpu, vendor, ext); -} +#define riscv_has_vendor_extension_likely(vendor, ext) = \ + ({ = \ + bool has_extension; = \ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) = \ + return false; = \ + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) = \ + has_extension =3D __riscv_has_extension_likely( = \ + vendor, ext, \ + RISCV_ISA_VENDOR_EXT_##ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); \ + else = \ + has_extension =3D __riscv_isa_vendor_extension_available( = \ + VENDOR_EXT_ALL_CPUS, vendor, RISCV_ISA_VENDOR_EXT_##ext); \ + has_extension = \ + }) + +#define riscv_has_vendor_extension_unlikely(vendor, ext) = \ + ({ = \ + bool has_extension; = \ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) = \ + return false; = \ + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) = \ + has_extension =3D __riscv_has_extension_unlikely( = \ + vendor, ext, \ + RISCV_ISA_VENDOR_EXT_##ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); \ + else = \ + has_extension =3D __riscv_isa_vendor_extension_available( = \ + VENDOR_EXT_ALL_CPUS, vendor, RISCV_ISA_VENDOR_EXT_##ext); \ + has_extension; = \ + }) + +#define riscv_cpu_has_vendor_extension_likely(vendor, cpu, ext) = \ + ({ = \ + bool has_extension; = \ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) = \ + return false; = \ + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) = \ + has_extension =3D __riscv_has_extension_likely( = \ + vendor, ext, \ + RISCV_ISA_VENDOR_EXT_##ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); \ + else = \ + has_extension =3D __riscv_isa_vendor_extension_available( = \ + cpu, vendor, RISCV_ISA_VENDOR_EXT_##ext); \ + has_extension; = \ + }) + +#define riscv_cpu_has_vendor_extension_unlikely(vendor, cpu, ext) = \ + ({ = \ + if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) = \ + return false; = \ + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) = \ + has_extension =3D __riscv_has_extension_unlikely( = \ + vendor, ext, \ + RISCV_ISA_VENDOR_EXT_##ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); \ + = \ + else = \ + has_extension =3D __riscv_isa_vendor_extension_available( = \ + cpu, vendor, RISCV_ISA_VENDOR_EXT_##ext); \ + has_extension; = \ + }) =20 #endif /* _ASM_VENDOR_EXTENSIONS_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 47612e9ca1c6..8913fcd6652e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -1120,17 +1120,17 @@ unsigned long riscv_get_elf_hwcap(void) =20 void __init riscv_user_isa_enable(void) { - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ)) + if (riscv_has_extension_unlikely(ZICBOZ)) current->thread.envcfg |=3D ENVCFG_CBZE; else if (any_cpu_has_zicboz) pr_warn("Zicboz disabled as it is unavailable on some harts\n"); =20 - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOM)) + if (riscv_has_extension_unlikely(ZICBOM)) current->thread.envcfg |=3D ENVCFG_CBCFE; else if (any_cpu_has_zicbom) pr_warn("Zicbom disabled as it is unavailable on some harts\n"); =20 - if (!riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOP) && + if (!riscv_has_extension_unlikely(ZICBOP) && any_cpu_has_zicbop) pr_warn("Zicbop disabled as it is unavailable on some harts\n"); } diff --git a/arch/riscv/kernel/pi/archrandom_early.c b/arch/riscv/kernel/pi= /archrandom_early.c index 3f05d3cf3b7b..0949a44d272a 100644 --- a/arch/riscv/kernel/pi/archrandom_early.c +++ b/arch/riscv/kernel/pi/archrandom_early.c @@ -10,6 +10,7 @@ * for the functions that won't be included. */ #undef riscv_has_extension_unlikely +#undef riscv_has_extension_likely #define riscv_has_extension_likely(...) false #undef pr_err_once #define pr_err_once(...) diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e3e501001916..7b46db8f4009 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -185,7 +185,7 @@ void flush_thread(void) clear_tsk_thread_flag(current, TIF_RISCV_V_DEFER_RESTORE); #endif #ifdef CONFIG_RISCV_ISA_SUPM - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SUPM)) + if (riscv_has_extension_unlikely(SUPM)) envcfg_update_bits(current, ENVCFG_PMM, ENVCFG_PMM_PMLEN_0); #endif } @@ -290,7 +290,7 @@ long set_tagged_addr_ctrl(struct task_struct *task, uns= igned long arg) unsigned long pmm; u8 pmlen; =20 - if (!riscv_has_extension_unlikely(RISCV_ISA_EXT_SUPM)) + if (!riscv_has_extension_unlikely(SUPM)) return -EINVAL; =20 if (is_compat_thread(ti)) @@ -348,7 +348,7 @@ long get_tagged_addr_ctrl(struct task_struct *task) struct thread_info *ti =3D task_thread_info(task); long ret =3D 0; =20 - if (!riscv_has_extension_unlikely(RISCV_ISA_EXT_SUPM)) + if (!riscv_has_extension_unlikely(SUPM)) return -EINVAL; =20 if (is_compat_thread(ti)) @@ -399,7 +399,7 @@ static const struct ctl_table tagged_addr_sysctl_table[= ] =3D { =20 static int __init tagged_addr_init(void) { - if (!riscv_has_extension_unlikely(RISCV_ISA_EXT_SUPM)) + if (!riscv_has_extension_unlikely(SUPM)) return 0; =20 /* diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index 24b3f57d467f..ea9547bfc6d7 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -14,7 +14,7 @@ =20 void suspend_save_csrs(struct suspend_context *context) { - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_XLINUXENVCFG)) + if (riscv_has_extension_unlikely(XLINUXENVCFG)) context->envcfg =3D csr_read(CSR_ENVCFG); context->tvec =3D csr_read(CSR_TVEC); context->ie =3D csr_read(CSR_IE); @@ -30,7 +30,7 @@ void suspend_save_csrs(struct suspend_context *context) */ =20 #ifdef CONFIG_MMU - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SSTC)) { + if (riscv_has_extension_unlikely(SSTC)) { context->stimecmp =3D csr_read(CSR_STIMECMP); #if __riscv_xlen < 64 context->stimecmph =3D csr_read(CSR_STIMECMPH); @@ -44,13 +44,13 @@ void suspend_save_csrs(struct suspend_context *context) void suspend_restore_csrs(struct suspend_context *context) { csr_write(CSR_SCRATCH, 0); - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_XLINUXENVCFG)) + if (riscv_has_extension_unlikely(XLINUXENVCFG)) csr_write(CSR_ENVCFG, context->envcfg); csr_write(CSR_TVEC, context->tvec); csr_write(CSR_IE, context->ie); =20 #ifdef CONFIG_MMU - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SSTC)) { + if (riscv_has_extension_unlikely(SSTC)) { csr_write(CSR_STIMECMP, context->stimecmp); #if __riscv_xlen < 64 csr_write(CSR_STIMECMPH, context->stimecmph); diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c index 3c5a70a2b927..50796c4ee8b6 100644 --- a/arch/riscv/kvm/tlb.c +++ b/arch/riscv/kvm/tlb.c @@ -18,7 +18,7 @@ #include #include =20 -#define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) +#define has_svinval() riscv_has_extension_unlikely(SVINVAL) =20 void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, gpa_t gpa, gpa_t gpsz, diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 5ce35aba6069..91556a897bb5 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -561,7 +561,7 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu= *vcpu) !riscv_isa_extension_available(isa, SVADE)) cfg->henvcfg |=3D ENVCFG_ADUE; =20 - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { + if (riscv_has_extension_unlikely(SMSTATEEN)) { cfg->hstateen0 |=3D SMSTATEEN0_HSENVCFG; if (riscv_isa_extension_available(isa, SSAIA)) cfg->hstateen0 |=3D SMSTATEEN0_AIA_IMSIC | @@ -596,7 +596,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) nacl_csr_write(nsh, CSR_HENVCFG, cfg->henvcfg); if (IS_ENABLED(CONFIG_32BIT)) nacl_csr_write(nsh, CSR_HENVCFGH, cfg->henvcfg >> 32); - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { + if (riscv_has_extension_unlikely(SMSTATEEN)) { nacl_csr_write(nsh, CSR_HSTATEEN0, cfg->hstateen0); if (IS_ENABLED(CONFIG_32BIT)) nacl_csr_write(nsh, CSR_HSTATEEN0H, cfg->hstateen0 >> 32); @@ -615,7 +615,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) csr_write(CSR_HENVCFG, cfg->henvcfg); if (IS_ENABLED(CONFIG_32BIT)) csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32); - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { + if (riscv_has_extension_unlikely(SMSTATEEN)) { csr_write(CSR_HSTATEEN0, cfg->hstateen0); if (IS_ENABLED(CONFIG_32BIT)) csr_write(CSR_HSTATEEN0H, cfg->hstateen0 >> 32); @@ -754,7 +754,7 @@ static __always_inline void kvm_riscv_vcpu_swap_in_gues= t_state(struct kvm_vcpu * =20 vcpu->arch.host_scounteren =3D csr_swap(CSR_SCOUNTEREN, csr->scounteren); vcpu->arch.host_senvcfg =3D csr_swap(CSR_SENVCFG, csr->senvcfg); - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) && + if (riscv_has_extension_unlikely(SMSTATEEN) && (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0)) vcpu->arch.host_sstateen0 =3D csr_swap(CSR_SSTATEEN0, smcsr->sstateen0); @@ -768,7 +768,7 @@ static __always_inline void kvm_riscv_vcpu_swap_in_host= _state(struct kvm_vcpu *v =20 csr->scounteren =3D csr_swap(CSR_SCOUNTEREN, vcpu->arch.host_scounteren); csr->senvcfg =3D csr_swap(CSR_SENVCFG, vcpu->arch.host_senvcfg); - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) && + if (riscv_has_extension_unlikely(SMSTATEEN) && (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0)) smcsr->sstateen0 =3D csr_swap(CSR_SSTATEEN0, vcpu->arch.host_sstateen0); diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index b6f5d1a74aec..e77779666463 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -240,7 +240,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned= long ext) return false; /* Extensions which can be disabled using Smstateen */ case KVM_RISCV_ISA_EXT_SSAIA: - return riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN); + return riscv_has_extension_unlikely(SMSTATEEN); case KVM_RISCV_ISA_EXT_SVADE: /* * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. @@ -592,7 +592,7 @@ static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *= vcpu, break; case KVM_REG_RISCV_CSR_SMSTATEEN: rc =3D -EINVAL; - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) + if (riscv_has_extension_unlikely(SMSTATEEN)) rc =3D kvm_riscv_vcpu_smstateen_get_csr(vcpu, reg_num, ®_val); break; @@ -637,7 +637,7 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *= vcpu, break; case KVM_REG_RISCV_CSR_SMSTATEEN: rc =3D -EINVAL; - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) + if (riscv_has_extension_unlikely(SMSTATEEN)) rc =3D kvm_riscv_vcpu_smstateen_set_csr(vcpu, reg_num, reg_val); break; diff --git a/arch/riscv/lib/csum.c b/arch/riscv/lib/csum.c index 75bd0abffd63..4db35dd698eb 100644 --- a/arch/riscv/lib/csum.c +++ b/arch/riscv/lib/csum.c @@ -42,7 +42,7 @@ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, =20 if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && - riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) { + riscv_has_extension_likely(ZBB)) { unsigned long fold_temp; =20 asm(".option push \n\ @@ -145,7 +145,7 @@ do_csum_with_alignment(const unsigned char *buff, int l= en) #ifdef CC_HAS_ASM_GOTO_TIED_OUTPUT if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && - riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) { + riscv_has_extension_likely(ZBB)) { unsigned long fold_temp; =20 #ifdef CONFIG_32BIT @@ -217,7 +217,7 @@ do_csum_no_alignment(const unsigned char *buff, int len) =20 if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && - riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) { + riscv_has_extension_likely(ZBB)) { unsigned long fold_temp; =20 #ifdef CONFIG_32BIT diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c index 807c0a0de182..68fa589d2d11 100644 --- a/arch/riscv/mm/pgtable.c +++ b/arch/riscv/mm/pgtable.c @@ -9,7 +9,7 @@ int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, pte_t *ptep, pte_t entry, int dirty) { - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVVPTC)) { + if (riscv_has_extension_unlikely(SVVPTC)) { if (!pte_same(ptep_get(ptep), entry)) { __set_pte_at(vma->vm_mm, ptep, entry); /* Here only not svadu is impacted */ diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 8404530ec00f..f92b2428f0e8 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -9,7 +9,7 @@ #include #include =20 -#define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) +#define has_svinval() riscv_has_extension_unlikely(SVINVAL) =20 static inline void local_sfence_inval_ir(void) { diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h index 632ced07bca4..34d0d9c44dfc 100644 --- a/arch/riscv/net/bpf_jit.h +++ b/arch/riscv/net/bpf_jit.h @@ -15,7 +15,7 @@ =20 /* verify runtime detection extension status */ #define rv_ext_enabled(ext) \ - (IS_ENABLED(CONFIG_RISCV_ISA_##ext) && riscv_has_extension_likely(RISCV_I= SA_EXT_##ext)) + (IS_ENABLED(CONFIG_RISCV_ISA_##ext) && riscv_has_extension_likely(ext)) =20 static inline bool rvc_enabled(void) { diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 7dd282da67ce..25bbb64a22a8 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -1204,8 +1204,7 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, = struct platform_device *pde riscv_cached_mimpid(0) =3D=3D 0) { riscv_pmu_irq_num =3D THEAD_C9XX_RV_IRQ_PMU; riscv_pmu_use_irq =3D true; - } else if (riscv_has_vendor_extension_unlikely(ANDES_VENDOR_ID, - RISCV_ISA_VENDOR_EXT_XANDESPMU) && + } else if (riscv_has_vendor_extension_unlikely(ANDES_VENDOR_ID, XANDESPMU= ) && IS_ENABLED(CONFIG_ANDES_CUSTOM_PMU)) { riscv_pmu_irq_num =3D ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMOVI; riscv_pmu_use_irq =3D true; diff --git a/lib/crc/riscv/crc-t10dif.h b/lib/crc/riscv/crc-t10dif.h index cd6136cbfda1..749eb577dd32 100644 --- a/lib/crc/riscv/crc-t10dif.h +++ b/lib/crc/riscv/crc-t10dif.h @@ -12,7 +12,7 @@ =20 static inline u16 crc_t10dif_arch(u16 crc, const u8 *p, size_t len) { - if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBC)) + if (riscv_has_extension_likely(ZBC)) return crc16_msb_clmul(crc, p, len, &crc16_msb_0x8bb7_consts); return crc_t10dif_generic(crc, p, len); } diff --git a/lib/crc/riscv/crc32.h b/lib/crc/riscv/crc32.h index 3ec6eee98afa..e2581cd6e179 100644 --- a/lib/crc/riscv/crc32.h +++ b/lib/crc/riscv/crc32.h @@ -12,7 +12,7 @@ =20 static inline u32 crc32_le_arch(u32 crc, const u8 *p, size_t len) { - if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBC)) + if (riscv_has_extension_likely(ZBC)) return crc32_lsb_clmul(crc, p, len, &crc32_lsb_0xedb88320_consts); return crc32_le_base(crc, p, len); @@ -20,7 +20,7 @@ static inline u32 crc32_le_arch(u32 crc, const u8 *p, siz= e_t len) =20 static inline u32 crc32_be_arch(u32 crc, const u8 *p, size_t len) { - if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBC)) + if (riscv_has_extension_likely(ZBC)) return crc32_msb_clmul(crc, p, len, &crc32_msb_0x04c11db7_consts); return crc32_be_base(crc, p, len); @@ -28,7 +28,7 @@ static inline u32 crc32_be_arch(u32 crc, const u8 *p, siz= e_t len) =20 static inline u32 crc32c_arch(u32 crc, const u8 *p, size_t len) { - if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBC)) + if (riscv_has_extension_likely(ZBC)) return crc32_lsb_clmul(crc, p, len, &crc32_lsb_0x82f63b78_consts); return crc32c_base(crc, p, len); @@ -36,7 +36,7 @@ static inline u32 crc32c_arch(u32 crc, const u8 *p, size_= t len) =20 static inline u32 crc32_optimizations_arch(void) { - if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBC)) + if (riscv_has_extension_likely(ZBC)) return CRC32_LE_OPTIMIZATION | CRC32_BE_OPTIMIZATION | CRC32C_OPTIMIZATION; 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[123.225.39.221]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f283d4733sm10364600c88.17.2025.12.10.08.14.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 08:14:12 -0800 (PST) From: Charlie Jenkins X-Google-Original-From: Charlie Jenkins Date: Wed, 10 Dec 2025 08:13:46 -0800 Subject: [PATCH RFC 09/10] riscv: kconfig: Add rva23 config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-profiles-v1-9-315a6ff2ca5a@gmail.com> References: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> In-Reply-To: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Samuel Holland , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Luke Nelson , Xi Wang , Eric Biggers , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765383226; l=11094; i=thecharlesjenkins@gmail.com; s=20240124; h=from:subject:message-id; bh=RdRZS0aP9TmGcChwbptIjsJMmOhoTpCnwW+G44c9f0A=; b=IxfntaSVfKQG8mLj1Qg1BmULOJOUaqqxjrNfFM7iWIebYybkydjxxDeZvtPVrQlWiqqf6BwNa oJXKJHlMZP6ASp0Is8JSk4m5EzcUU0w1LDBYaWNWOEZnvxntHRQJn13 X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=eVndo3OHViAjwuqHqbJB4ZtzJzzvk/r6fUf84tZ3rw4= Add CONFIG_RISCV_ISA_RVA23 to select all rva23 mandatory extensions. This also introduces a new class of kernel binaries, portable rva23 compatible binaries. This option does not require NONPORTABLE because profiles are expected to be portable between systems. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.extensions | 99 ++++++++++++++++++++++++++++++---------= ---- 1 file changed, 70 insertions(+), 29 deletions(-) diff --git a/arch/riscv/Kconfig.extensions b/arch/riscv/Kconfig.extensions index e400fd5574f7..38b655e480a8 100644 --- a/arch/riscv/Kconfig.extensions +++ b/arch/riscv/Kconfig.extensions @@ -4,6 +4,33 @@ # see Documentation/kbuild/kconfig-language.rst. # =20 +# Profiles + +config RISCV_ISA_RVA23 + bool "Enable rva23 extensions" + default n + select RISCV_ISA_SUPM + select RISCV_ISA_SVNAPOT + select RISCV_ISA_SVPBMT + select RISCV_ISA_ZAWRS + select RISCV_ISA_ZBA + select RISCV_ISA_ZBB + select RISCV_ISA_ZBC + select RISCV_ISA_ZBKB + select RISCV_ISA_ZICBOM + select RISCV_ISA_ZICBOZ + select RISCV_ISA_ZICBOP + select RISCV_ISA_V + help + The RVA23 profile is a grouping of extensions that are expected to be + available on server and application CPUs. + + Enabling this config will cause the kernel to fail to boot on platforms + that are not rva23 compliant. + + Say "y" here to optimize the kernel for rva23 compliant platforms. + + If you don't know what to do here, say "n". =20 # Base extensions =20 @@ -64,7 +91,7 @@ config RISCV_ISA_D config RISCV_ISA_SUPM tristate "Supm extension for userspace pointer masking" depends on 64BIT - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help Add support for pointer masking in userspace (Supm) when the @@ -75,14 +102,15 @@ config RISCV_ISA_SUPM =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time optimization. Only available with NONPORTAB= LE. + Select "y" for compile-time optimization. Only available with NONPORTAB= LE + or CONFIG_RISCV_ISA_RVA23. =20 If you don't know what to do here, say m. =20 config RISCV_ISA_SVNAPOT tristate "Svnapot extension support for supervisor mode NAPOT pages" depends on 64BIT && MMU - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help The Svnapot extension is used to mark contiguous PTEs as a range @@ -95,14 +123,15 @@ config RISCV_ISA_SVNAPOT =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time optimization. Only available with NONPORTAB= LE. + Select "y" for compile-time optimization. Only available with NONPORTAB= LE + or CONFIG_RISCV_ISA_RVA23. =20 If you don't know what to do here, say m. =20 config RISCV_ISA_SVPBMT tristate "Svpbmt extension support for supervisor mode page-based memory = types" depends on 64BIT && MMU - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help The memory type for a page contains a combination of attributes @@ -113,14 +142,15 @@ config RISCV_ISA_SVPBMT =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time optimization. Only available with NONPORTAB= LE. + Select "y" for compile-time optimization. Only available with NONPORTAB= LE + or CONFIG_RISCV_ISA_RVA23. =20 If you don't know what to do here, say m. =20 =20 config RISCV_ISA_ZAWRS tristate "Zawrs extension support for more efficient busy waiting" - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help The Zawrs extension defines instructions to be used in polling loops @@ -139,7 +169,7 @@ config TOOLCHAIN_HAS_ZABHA config RISCV_ISA_ZABHA tristate "Zabha extension support for atomic byte/halfword operations" depends on TOOLCHAIN_HAS_ZABHA - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help Enable the use of the Zabha ISA-extension to implement kernel @@ -147,7 +177,8 @@ config RISCV_ISA_ZABHA =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time optimization. Only available with NONPORTAB= LE. + Select "y" for compile-time optimization. Only available with NONPORTAB= LE + or CONFIG_RISCV_ISA_RVA23. =20 If you don't know what to do here, say m. =20 @@ -161,7 +192,7 @@ config TOOLCHAIN_HAS_ZACAS config RISCV_ISA_ZACAS tristate "Zacas extension support for atomic CAS" depends on TOOLCHAIN_HAS_ZACAS - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help Enable the use of the Zacas ISA-extension to implement kernel atomic @@ -169,7 +200,8 @@ config RISCV_ISA_ZACAS =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time optimization. Only available with NONPORTAB= LE. + Select "y" for compile-time optimization. Only available with NONPORTAB= LE + or CONFIG_RISCV_ISA_RVA23. =20 If you don't know what to do here, say m. =20 @@ -183,7 +215,7 @@ config TOOLCHAIN_HAS_ZBA =20 config RISCV_ISA_ZBA tristate "Zba extension support for bit manipulation instructions" - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help The Zba extension provides instructions to accelerate the generation @@ -191,7 +223,8 @@ config RISCV_ISA_ZBA =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE + or CONFIG_RISCV_ISA_RVA23. =20 If you don't know what to do here, say m. =20 @@ -205,7 +238,7 @@ config TOOLCHAIN_HAS_ZBB =20 config RISCV_ISA_ZBB tristate "Zbb extension support for bit manipulation instructions" - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help The Zbb extension provides instructions to accelerate a number @@ -214,7 +247,8 @@ config RISCV_ISA_ZBB =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time optimization. Only available with NONPORTAB= LE. + Select "y" for compile-time optimization. Only available with NONPORTAB= LE + or CONFIG_RISCV_ISA_RVA23. =20 If you don't know what to do here, say m. =20 @@ -228,7 +262,7 @@ config TOOLCHAIN_HAS_ZBC =20 config RISCV_ISA_ZBC tristate "Zbc extension support for carry-less multiplication instruction= s" - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help The Zbc extension could accelerate CRC (cyclic redundancy check) @@ -236,7 +270,8 @@ config RISCV_ISA_ZBC =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE + or CONFIG_RISCV_ISA_RVA23. =20 If you don't know what to do here, say m. =20 @@ -250,7 +285,7 @@ config TOOLCHAIN_HAS_ZBKB =20 config RISCV_ISA_ZBKB tristate "Zbkb extension support for bit manipulation instructions" - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help The Zbkb extension provides instructions to accelerate a number @@ -258,14 +293,15 @@ config RISCV_ISA_ZBKB =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE + or CONFIG_RISCV_ISA_RVA23. =20 If you don't know what to do here, say m. =20 config RISCV_ISA_ZICBOM bool "Zicbom extension support for non-coherent DMA operation" depends on MMU - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m select RISCV_DMA_NONCOHERENT select DMA_DIRECT_REMAP @@ -275,13 +311,14 @@ config RISCV_ISA_ZICBOM =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time optimization. Only available with NONPORTAB= LE. + Select "y" for compile-time optimization. Only available with NONPORTAB= LE + or CONFIG_RISCV_ISA_RVA23. =20 If you don't know what to do here, say m. =20 config RISCV_ISA_ZICBOZ bool "Zicboz extension support for faster zeroing of memory" - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help Enable the use of the Zicboz extension (cbo.zero instruction) @@ -291,14 +328,15 @@ config RISCV_ISA_ZICBOZ =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE + or CONFIG_RISCV_ISA_RVA23. =20 If you don't know what to do here, say m. =20 config RISCV_ISA_ZICBOP bool "Zicbop extension support for cache block prefetch" depends on MMU - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help The Zicbop extension can be used to prefetch cache blocks for @@ -306,7 +344,8 @@ config RISCV_ISA_ZICBOP =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE + or CONFIG_RISCV_ISA_RVA23. =20 If you don't know what to do here, say m. =20 @@ -348,7 +387,7 @@ config RISCV_ISA_V depends on FPU select DYNAMIC_SIGFRAME select RISCV_ISA_ZVE32X - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help Say N here if you want to disable all vector related procedure @@ -356,20 +395,22 @@ config RISCV_ISA_V =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE + or CONFIG_RISCV_ISA_RVA23. =20 If you don't know what to do here, say m. =20 config RISCV_ISA_ZVE32X tristate "zve32x extension support" - depends on NONPORTABLE || m + depends on NONPORTABLE || RISCV_ISA_RVA23 || m default m help zve23x is a subset of the vector extension. Can be enabled for minimal = vector support. =20 Select "m" for boot-time detection for portability. =20 - Select "y" for compile-time detection for optimization. Only available = with NONPORTABLE. + Select "y" for compile-time detection for optimization. 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[123.225.39.221]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f283d4733sm10364600c88.17.2025.12.10.08.14.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 08:14:15 -0800 (PST) From: Charlie Jenkins X-Google-Original-From: Charlie Jenkins Date: Wed, 10 Dec 2025 08:13:47 -0800 Subject: [PATCH RFC 10/10] riscv: csum: Remove inline assembly Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-profiles-v1-10-315a6ff2ca5a@gmail.com> References: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> In-Reply-To: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Samuel Holland , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Luke Nelson , Xi Wang , Eric Biggers , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765383226; l=5947; i=thecharlesjenkins@gmail.com; s=20240124; h=from:subject:message-id; bh=XhAElkNP1R/DcELUvrMdV1p/6w1v1sH1Jk8z4m0bNMI=; b=pxIq6ajzNKubSjM7RdllJJijS2wCrpEZXpA1x4QQMEnDZVGZuxtBr8aQtNDmwYiPizWboWhVH IjYN7tCROtVD/oQO+TCuKuAd3k5RFZBGcW5djCTgtBiowOuufXAUanA X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=eVndo3OHViAjwuqHqbJB4ZtzJzzvk/r6fUf84tZ3rw4= When the kernel is set to have zbb enabled by default, the compiler generates better code than is possible with the inline assembly. Removing the inline assembly will greatly simplify the checksumming code and improve the performance when zbb is enabled. However, performance will be decreased on kernels where only runtime discovery is enabled. Moving towards this performance model of optimizing for compiled-in extensions will help to keep the kernel code from spinning out of control with the vast amount of extensions that are available to riscv. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/checksum.h | 32 ------------- arch/riscv/lib/csum.c | 94 -----------------------------------= ---- 2 files changed, 126 deletions(-) diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/che= cksum.h index e747af23eea2..ecc4779209b9 100644 --- a/arch/riscv/include/asm/checksum.h +++ b/arch/riscv/include/asm/checksum.h @@ -45,38 +45,6 @@ static inline __sum16 ip_fast_csum(const void *iph, unsi= gned int ihl) csum +=3D csum < ((const unsigned int *)iph)[pos]; } while (++pos < ihl); =20 - /* - * ZBB only saves three instructions on 32-bit and five on 64-bit so not - * worth checking if supported without Alternatives. - */ - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && - IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && - riscv_has_extension_likely(ZBB)) { - unsigned long fold_temp; - - if (IS_ENABLED(CONFIG_32BIT)) { - asm(".option push \n\ - .option arch,+zbb \n\ - not %[fold_temp], %[csum] \n\ - rori %[csum], %[csum], 16 \n\ - sub %[csum], %[fold_temp], %[csum] \n\ - .option pop" - : [csum] "+r" (csum), [fold_temp] "=3D&r" (fold_temp)); - } else { - asm(".option push \n\ - .option arch,+zbb \n\ - rori %[fold_temp], %[csum], 32 \n\ - add %[csum], %[fold_temp], %[csum] \n\ - srli %[csum], %[csum], 32 \n\ - not %[fold_temp], %[csum] \n\ - roriw %[csum], %[csum], 16 \n\ - subw %[csum], %[fold_temp], %[csum] \n\ - .option pop" - : [csum] "+r" (csum), [fold_temp] "=3D&r" (fold_temp)); - } - return (__force __sum16)(csum >> 16); - } - #ifndef CONFIG_32BIT csum +=3D ror64(csum, 32); csum >>=3D 32; diff --git a/arch/riscv/lib/csum.c b/arch/riscv/lib/csum.c index 4db35dd698eb..93c073f2b883 100644 --- a/arch/riscv/lib/csum.c +++ b/arch/riscv/lib/csum.c @@ -40,24 +40,6 @@ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, uproto =3D (__force unsigned int)htonl(proto); sum +=3D uproto; =20 - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && - IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && - riscv_has_extension_likely(ZBB)) { - unsigned long fold_temp; - - asm(".option push \n\ - .option arch,+zbb \n\ - rori %[fold_temp], %[sum], 32 \n\ - add %[sum], %[fold_temp], %[sum] \n\ - srli %[sum], %[sum], 32 \n\ - not %[fold_temp], %[sum] \n\ - roriw %[sum], %[sum], 16 \n\ - subw %[sum], %[fold_temp], %[sum] \n\ - .option pop" - : [sum] "+r" (sum), [fold_temp] "=3D&r" (fold_temp)); - return (__force __sum16)(sum >> 16); - } - sum +=3D ror64(sum, 32); sum >>=3D 32; return csum_fold((__force __wsum)sum); @@ -142,51 +124,6 @@ do_csum_with_alignment(const unsigned char *buff, int = len) end =3D (const unsigned long *)(buff + len); csum =3D do_csum_common(ptr, end, data); =20 -#ifdef CC_HAS_ASM_GOTO_TIED_OUTPUT - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && - IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && - riscv_has_extension_likely(ZBB)) { - unsigned long fold_temp; - -#ifdef CONFIG_32BIT - asm_goto_output(".option push \n\ - .option arch,+zbb \n\ - rori %[fold_temp], %[csum], 16 \n\ - andi %[offset], %[offset], 1 \n\ - add %[csum], %[fold_temp], %[csum] \n\ - beq %[offset], zero, %l[end] \n\ - rev8 %[csum], %[csum] \n\ - .option pop" - : [csum] "+r" (csum), [fold_temp] "=3D&r" (fold_temp) - : [offset] "r" (offset) - : - : end); - - return (unsigned short)csum; -#else /* !CONFIG_32BIT */ - asm_goto_output(".option push \n\ - .option arch,+zbb \n\ - rori %[fold_temp], %[csum], 32 \n\ - add %[csum], %[fold_temp], %[csum] \n\ - srli %[csum], %[csum], 32 \n\ - roriw %[fold_temp], %[csum], 16 \n\ - addw %[csum], %[fold_temp], %[csum] \n\ - andi %[offset], %[offset], 1 \n\ - beq %[offset], zero, %l[end] \n\ - rev8 %[csum], %[csum] \n\ - .option pop" - : [csum] "+r" (csum), [fold_temp] "=3D&r" (fold_temp) - : [offset] "r" (offset) - : - : end); - - return (csum << 16) >> 48; -#endif /* !CONFIG_32BIT */ -end: - return csum >> 16; - } - -#endif /* CC_HAS_ASM_GOTO_TIED_OUTPUT */ #ifndef CONFIG_32BIT csum +=3D ror64(csum, 32); csum >>=3D 32; @@ -215,37 +152,6 @@ do_csum_no_alignment(const unsigned char *buff, int le= n) end =3D (const unsigned long *)(buff + len); csum =3D do_csum_common(ptr, end, data); =20 - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && - IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && - riscv_has_extension_likely(ZBB)) { - unsigned long fold_temp; - -#ifdef CONFIG_32BIT - asm (".option push \n\ - .option arch,+zbb \n\ - rori %[fold_temp], %[csum], 16 \n\ - add %[csum], %[fold_temp], %[csum] \n\ - .option pop" - : [csum] "+r" (csum), [fold_temp] "=3D&r" (fold_temp) - : - : ); - -#else /* !CONFIG_32BIT */ - asm (".option push \n\ - .option arch,+zbb \n\ - rori %[fold_temp], %[csum], 32 \n\ - add %[csum], %[fold_temp], %[csum] \n\ - srli %[csum], %[csum], 32 \n\ - roriw %[fold_temp], %[csum], 16 \n\ - addw %[csum], %[fold_temp], %[csum] \n\ - .option pop" - : [csum] "+r" (csum), [fold_temp] "=3D&r" (fold_temp) - : - : ); -#endif /* !CONFIG_32BIT */ - return csum >> 16; - } - #ifndef CONFIG_32BIT csum +=3D ror64(csum, 32); csum >>=3D 32; --=20 2.43.0