From nobody Wed Dec 17 03:47:09 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EC243246FF for ; Wed, 10 Dec 2025 12:36:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765370210; cv=none; b=HvlhOWcBy7/QgR9xHZwjWF83Ky3Rj0reBZtKc22EvCruPviLCipMJlphjwexOi0Yh1CjavCytY+YwC6LyQfbAO6Q7nSXgvBNgpIs6LoC6ZLDZjOGIbJiTlNtwB0h5GjRepIlMmWvOMpf8WLBG1tUdB/oA8viG18aXoezdQ6Y1m4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765370210; c=relaxed/simple; bh=n3SYjY/tgJrPi71n+s6qipgCP7hon8fBzgqFwbvNnLE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AyN4iBvZrNfewjbtU+mr0VvbkheXOF+p2iFm7YD0OHqgoX6GggMeFb/wWpoYFRVbZrC2YYSloqd/L9nON3b3CkyvvQOuAN4TWsJlO6Q82f5RatYMoQkUZ5qFivSUt17TjugVH/2h7sTsKrZVy9/gBqqsuA8XKDPHXlePCX35ffQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=OqZa9B3m; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Cam7PJjb; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="OqZa9B3m"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Cam7PJjb" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BAASYw41802668 for ; Wed, 10 Dec 2025 12:36:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= GBWzeL40xxhTu4y8uSaxDGrN6sq/Gpl8VBf9jRUaV6M=; b=OqZa9B3mTQ7LCrds vV/hha/JCkg4yd1k9x7HO/Gu49U8FjGTujngPC5wRe9l76zu4vii1Hhia0A/TaBc Lkoho4Qq9g78ww9uElCXloQjiY6iV2EuoC5VdHeQ/LYHgzLPPAss/nJr31rjXM52 RiIX5CAXgh/P5V/qT0Zfr2f7w6eS6/jiKXeXZNQdnnGdbNpDKJjacFMKX0Qzj6pC fupJhKxuzraEvSc5i9Ar7omg9QFrdwKkQSTMPMoUHS5oC4hIrdDK0rKvqaKFIK/y /zuMMpaB8OA/hSUaYojUvib9boZaDzhcczkPBse4ZuPQ7Ygjhtn9G97cVL2ZLelI NCm7/g== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ay753rab8-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 10 Dec 2025 12:36:46 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-295592eb5dbso126559205ad.0 for ; Wed, 10 Dec 2025 04:36:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1765370205; x=1765975005; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GBWzeL40xxhTu4y8uSaxDGrN6sq/Gpl8VBf9jRUaV6M=; b=Cam7PJjbtUQfjJxN3alpXdgmdjSAy3tOOVqHB9l/HqZhvQbO9iJ+JzAn6PpyzmgFJ2 xpQrjHuVl2+wsYYHdL1BL0n7YHn+MZMRLjqRaagc31R7GgdoFGteUXxHD7XHdQbWZwOr WIom3BkmqQr6z0zNvlh2Iu4ZY9FbgKWmCU5dxwP+XK/QOyBgi/q+yRRDevMgfGLEquU6 69VD6TwVTx4VBlbMUkXTGHiBKVwEarJsHQ8HME6HMoGYw/iLQ+GumAmrR9IPD+z0GRQl vzflJfo6YREF53gP+/bSuCDHYk1BhTcm3QX52Xtqn2C0hBso3lN4y3qsoV7dDsyCfDSH cqgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765370205; x=1765975005; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=GBWzeL40xxhTu4y8uSaxDGrN6sq/Gpl8VBf9jRUaV6M=; b=dyBPf7m6aQdWL2ArIRawd0FT2xOBI3F+Ptbgc9cmmRdgSr91HmNBtIGAP8Y1v+SFDF FS1Vo+oqbveeKMZLKpljBnBdflB37V0z3zmukqXaZboWSJeSy4AdGKZZRAWraACWmmZC TjOR0XQghmOZMnUpzdEyk1XzrHobe84Gbwium4M2979VEWamXT88gAn1oFkDibJbgyJA 13GZj0oQaibqJclDYjywYhldFqWMSvgDnueW2y2hsviG0uHqLZ/2/7hzXMSXFiTv5nYx M1sK31C7WzE+bN+ENSyA66BFviBfOJAPvYkMIXJmLhT+3HoP+CouktlJd1LzVd+0qPr2 g9nQ== X-Forwarded-Encrypted: i=1; AJvYcCUldRKymorK4zmbxUBwxTxJR0TBObtC1MpxisLHM6EvwpbIuYtcmfYp253x6rAPWrgplXbiLyeC9XfeZfA=@vger.kernel.org X-Gm-Message-State: AOJu0YysWTlgwTWRn0GyKvIMGJOFkArso06TJkt98gkwyanD4ME+9fyu iww99bkn97pH5kHqPUklz0NbX1A+xaLy+RKPreVvlRj2x0NYPMurzzBJ9QYVnV0RTaMnSNwllZ0 gwpv5nJ9guXTJjbgu3J+QV1AYIhjwsjNkYni8xMjyd7uQFSxtYopw9y4KLS6VXfY+/ANZzH/khc w= X-Gm-Gg: AY/fxX5XtGjgtF8xanIO8xscZSQb0yWMED1FYkHkSmLsUa47rk3ELf6+pJMnE//Uq9L FYUPiHw0sdxfVXw8/oXTm1IBAPJl7dwVcVcauOnWc0qC2FPejG4yAMxzcYRiQ0Tghdh8Ov13n0k 0davZ2/pfHMMNw9rmgJ6mUaNNArEqDdW5bUuFcejsI27nbdxL884bv1z5eFe877oq/M+jix6ZrN 1cqFzN3grONv8VOJfa8EZRpwJ4mfe1zn2EPDT+9NyzVhSC9RPR94iMve3XO9y1HRpopD6oy1Ar4 46F7mh08yoiZjWFgzfX/2p0eULsapDyy7DZUxTAe+TsSGORZlZDlZo+ESX02laWzgPCxxn2oeY3 qv6BmZZoTIGkBmkP+FQXKBx2AOvZj17x3KNvImk/pyLsx X-Received: by 2002:a17:902:cecc:b0:295:9a46:a1d0 with SMTP id d9443c01a7336-29ec27bb1e5mr20183255ad.45.1765370205357; Wed, 10 Dec 2025 04:36:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IF/2nNXqCs8LPc+lM3UoNM0a2pPtjvRH/DL7FNnII9dO+DyLkKkJtUAAxJtKHEtwh9xzWbjIA== X-Received: by 2002:a17:902:cecc:b0:295:9a46:a1d0 with SMTP id d9443c01a7336-29ec27bb1e5mr20183065ad.45.1765370204730; Wed, 10 Dec 2025 04:36:44 -0800 (PST) Received: from hu-vgarodia-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29daeaab9c0sm185434615ad.68.2025.12.10.04.36.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 04:36:44 -0800 (PST) From: Vikash Garodia Date: Wed, 10 Dec 2025 18:06:04 +0530 Subject: [PATCH v4 6/6] media: iris: Introduce vpu ops for vpu4 with necessary hooks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-knp_video-v4-6-8d11d840358a@oss.qualcomm.com> References: <20251210-knp_video-v4-0-8d11d840358a@oss.qualcomm.com> In-Reply-To: <20251210-knp_video-v4-0-8d11d840358a@oss.qualcomm.com> To: Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Dmitry Baryshkov , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vishnu Reddy , Vikash Garodia X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765370172; l=15222; i=vikash.garodia@oss.qualcomm.com; s=20241104; h=from:subject:message-id; bh=n3SYjY/tgJrPi71n+s6qipgCP7hon8fBzgqFwbvNnLE=; b=867Evf1q4XbC5YG6EoQ03chcnuvE5tTDZOoA3R3yop7FDLCPUcddw6P7Ud9C1ZHiSY5/Ha/JB 1AQ55Jjy+6fC+dKc4xfQgI6x/5yNo4XAYA7pQp7x0PV2BgTF8ZfZyC4 X-Developer-Key: i=vikash.garodia@oss.qualcomm.com; a=ed25519; pk=LY9Eqp4KiHWxzGNKGHbwRFEJOfRCSzG/rxQNmvZvaKE= X-Authority-Analysis: v=2.4 cv=cYjfb3DM c=1 sm=1 tr=0 ts=6939695e cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=UhFlbVm-_xg1FUzKVQEA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: tWKSmjgFLZtweQb4GZinuG0830ihMBZ8 X-Proofpoint-GUID: tWKSmjgFLZtweQb4GZinuG0830ihMBZ8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEwMDEwMCBTYWx0ZWRfX2eyaFAJDnb56 lTliv2TqP1CmnLPrV5MqxOSiVQbbntjUMFjBY4bwVhrbSv/x2INRCIFw85hv+0LfbsFvWCkRzjW C6W29Exjvh8Gm5xI7mpJoGJLmim+NKzcx1qHzbfX59rmtPqncHYuVvtlS/0U7m3o1KJZ1UYs/48 viMAAZ6VbhAPYW0TQUM6rXUV9+Ftc0g9cf48Xq/70M5b5x3zEKAzCtc8ET0htMfNEDFjLSjTkyX 0JXGJWTB6Z7SSu6Z5NyDWWd6OP9x1Irr9h1vBB6LIJAswN/9zgN5zBFLrtHCNvEGl4GK1VjAChw jzl3MU96tQ3jPVA4aiMpp1JFcLKtQ7YtN0oguJgavijt8g9l84DdngczCP+nTK1VytNDD/gF2fW vzxW/Jc/tlgIW5FTqW2PGTzZmW+oGw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-09_05,2025-12-09_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 spamscore=0 suspectscore=0 clxscore=1015 impostorscore=0 phishscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512100100 Add power sequence for vpu4 by reusing from previous generation wherever possible. Hook up vpu4 op with vpu4 specific implemtation or resue from earlier generation wherever feasible, like clock calculation in this case. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/Makefile | 1 + .../platform/qcom/iris/iris_platform_common.h | 7 + drivers/media/platform/qcom/iris/iris_vpu4x.c | 369 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + 4 files changed, 378 insertions(+) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index fad3be044e5fe783db697a592b4f09de4d42d0d2..2abbd3aeb4af07e52bf372a4b2f= 352463529c92c 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -22,6 +22,7 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_venc.o \ iris_vpu2.o \ iris_vpu3x.o \ + iris_vpu4x.o \ iris_vpu_buffer.o \ iris_vpu_common.o \ =20 diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 29900c3ea9b9ebbab614c804a249b08ba6001494..bc78cf7c77718666ddac86d6913= b4d380991018f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -57,6 +57,10 @@ enum platform_clk_type { IRIS_AXI1_CLK, IRIS_CTRL_FREERUN_CLK, IRIS_HW_FREERUN_CLK, + IRIS_BSE_HW_CLK, + IRIS_VPP0_HW_CLK, + IRIS_VPP1_HW_CLK, + IRIS_APV_HW_CLK, }; =20 struct platform_clk_data { @@ -191,6 +195,9 @@ struct icc_vote_data { enum platform_pm_domain_type { IRIS_CTRL_POWER_DOMAIN, IRIS_HW_POWER_DOMAIN, + IRIS_VPP0_HW_POWER_DOMAIN, + IRIS_VPP1_HW_POWER_DOMAIN, + IRIS_APV_HW_POWER_DOMAIN, }; =20 struct iris_platform_data { diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/= platform/qcom/iris/iris_vpu4x.c new file mode 100644 index 0000000000000000000000000000000000000000..a8db02ce5c5ec583c4027166b34= ce51d3d683b4e --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +#include "iris_instance.h" +#include "iris_vpu_common.h" +#include "iris_vpu_register_defines.h" + +#define AON_WRAPPER_MVP_NOC_RESET_SYNCRST (AON_MVP_NOC_RESET + 0x08) +#define CPU_CS_APV_BRIDGE_SYNC_RESET (CPU_BASE_OFFS + 0x174) +#define MVP_NOC_RESET_REQ_MASK 0x70103 +#define VPU_IDLE_BITS 0x7103 +#define WRAPPER_EFUSE_MONITOR (WRAPPER_BASE_OFFS + 0x08) + +#define APV_CLK_HALT BIT(1) +#define CORE_CLK_HALT BIT(0) +#define CORE_PWR_ON BIT(1) +#define DISABLE_VIDEO_APV_BIT BIT(27) +#define DISABLE_VIDEO_VPP1_BIT BIT(28) +#define DISABLE_VIDEO_VPP0_BIT BIT(29) + +static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mod= e, u32 efuse_value) +{ + int ret; + + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], hw_mode); + if (ret) + return ret; + + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs + [IRIS_VPP0_HW_POWER_DOMAIN], hw_mode); + if (ret) + goto restore_hw_domain_mode; + } + + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs + [IRIS_VPP1_HW_POWER_DOMAIN], hw_mode); + if (ret) + goto restore_vpp0_domain_mode; + } + + if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) { + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs + [IRIS_APV_HW_POWER_DOMAIN], hw_mode); + if (ret) + goto restore_vpp1_domain_mode; + } + + return 0; + +restore_vpp1_domain_mode: + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP1_HW_POWER_D= OMAIN], + !hw_mode); +restore_vpp0_domain_mode: + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_D= OMAIN], + !hw_mode); +restore_hw_domain_mode: + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]= , !hw_mode); + + return ret; +} + +static int iris_vpu4x_power_on_apv(struct iris_core *core) +{ + int ret; + + ret =3D iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_APV_HW_CLK); + if (ret) + goto disable_apv_hw_power_domain; + + return 0; + +disable_apv_hw_power_domain: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_= POWER_DOMAIN]); + + return ret; +} + +static void iris_vpu4x_power_off_apv(struct iris_core *core) +{ + bool handshake_done, handshake_busy; + u32 value, count =3D 0; + int ret; + + value =3D readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + if (value & APV_CLK_HALT) + writel(0x0, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + do { + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CON= TROL); + usleep_range(10, 20); + value =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); + + handshake_done =3D value & NOC_LPI_STATUS_DONE; + handshake_busy =3D value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE); + + if (handshake_done || !handshake_busy) + break; + + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + usleep_range(10, 20); + + } while (++count < 1000); + + if (!handshake_done && handshake_busy) + dev_err(core->dev, "LPI handshake timeout\n"); + + writel(0x080200, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, + value, value & 0x080200, 200, 2000); + if (ret) + goto disable_clocks_and_power; + + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_SYNCRST); + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, + value, value =3D=3D 0x0, 200, 2000); + if (ret) + goto disable_clocks_and_power; + + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_bas= e + + CPU_CS_APV_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_APV_BRIDGE_S= YNC_RESET); + writel(0x0, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET); + +disable_clocks_and_power: + iris_disable_unprepare_clock(core, IRIS_APV_HW_CLK); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_= POWER_DOMAIN]); +} + +static void iris_vpu4x_ahb_sync_reset_apv(struct iris_core *core) +{ + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_bas= e + + CPU_CS_APV_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_APV_BRIDGE_S= YNC_RESET); + writel(0x0, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET); +} + +static void iris_vpu4x_ahb_sync_reset_hardware(struct iris_core *core) +{ + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_bas= e + + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_S= YNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); +} + +static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 e= fuse_value) +{ + int ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_AXI_CLK); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); + if (ret) + goto disable_axi_clock; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); + if (ret) + goto disable_hw_free_run_clock; + + ret =3D iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); + if (ret) + goto disable_hw_clock; + + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { + ret =3D iris_prepare_enable_clock(core, IRIS_VPP0_HW_CLK); + if (ret) + goto disable_bse_hw_clock; + } + + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { + ret =3D iris_prepare_enable_clock(core, IRIS_VPP1_HW_CLK); + if (ret) + goto disable_vpp0_hw_clock; + } + + return 0; + +disable_vpp0_hw_clock: + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) + iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK); +disable_bse_hw_clock: + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); +disable_hw_clock: + iris_disable_unprepare_clock(core, IRIS_HW_CLK); +disable_hw_free_run_clock: + iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); +disable_axi_clock: + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + + return ret; +} + +static void iris_vpu4x_disable_hardware_clocks(struct iris_core *core, u32= efuse_value) +{ + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) + iris_disable_unprepare_clock(core, IRIS_VPP1_HW_CLK); + + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) + iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK); + + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); +} + +static int iris_vpu4x_power_on_hardware(struct iris_core *core) +{ + u32 efuse_value =3D readl(core->reg_base + WRAPPER_EFUSE_MONITOR); + int ret; + + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); + if (ret) + return ret; + + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP0_HW_POWER_DOMAIN]); + if (ret) + goto disable_hw_power_domain; + } + + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP1_HW_POWER_DOMAIN]); + if (ret) + goto disable_vpp0_power_domain; + } + + ret =3D iris_vpu4x_enable_hardware_clocks(core, efuse_value); + if (ret) + goto disable_vpp1_power_domain; + + if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) { + ret =3D iris_vpu4x_power_on_apv(core); + if (ret) + goto disable_hw_clocks; + + iris_vpu4x_ahb_sync_reset_apv(core); + } + + iris_vpu4x_ahb_sync_reset_hardware(core); + + ret =3D iris_vpu4x_genpd_set_hwmode(core, true, efuse_value); + if (ret) + goto disable_apv_power_domain; + + return 0; + +disable_apv_power_domain: + if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) + iris_vpu4x_power_off_apv(core); +disable_hw_clocks: + iris_vpu4x_disable_hardware_clocks(core, efuse_value); +disable_vpp1_power_domain: + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP1_HW_POWER_DOMAIN]); +disable_vpp0_power_domain: + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP0_HW_POWER_DOMAIN]); +disable_hw_power_domain: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + + return ret; +} + +static void iris_vpu4x_power_off_hardware(struct iris_core *core) +{ + u32 efuse_value =3D readl(core->reg_base + WRAPPER_EFUSE_MONITOR); + bool handshake_done, handshake_busy; + u32 value, count =3D 0; + int ret; + + iris_vpu4x_genpd_set_hwmode(core, false, efuse_value); + + if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) + iris_vpu4x_power_off_apv(core); + + value =3D readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); + + if (!(value & CORE_PWR_ON)) + goto disable_clocks_and_power; + + value =3D readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + if (value & CORE_CLK_HALT) + writel(0x0, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN, value, + value & VPU_IDLE_BITS, 2000, 20000); + + do { + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CON= TROL); + usleep_range(10, 20); + value =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); + + handshake_done =3D value & NOC_LPI_STATUS_DONE; + handshake_busy =3D value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE); + + if (handshake_done || !handshake_busy) + break; + + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + usleep_range(10, 20); + + } while (++count < 1000); + + if (!handshake_done && handshake_busy) + dev_err(core->dev, "LPI handshake timeout\n"); + + writel(MVP_NOC_RESET_REQ_MASK, core->reg_base + AON_WRAPPER_MVP_NOC_RESET= _REQ); + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, + value, value & MVP_NOC_RESET_REQ_MASK, 200, 2000); + if (ret) + goto disable_clocks_and_power; + + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_SYNCRST); + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, + value, value =3D=3D 0x0, 200, 2000); + if (ret) + goto disable_clocks_and_power; + + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_bas= e + + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_S= YNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + +disable_clocks_and_power: + iris_vpu4x_disable_hardware_clocks(core, efuse_value); + + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP1_HW_POWER_DOMAIN]); + + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP0_HW_POWER_DOMAIN]); + + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); +} + +const struct vpu_ops iris_vpu4x_ops =3D { + .power_off_hw =3D iris_vpu4x_power_off_hardware, + .power_on_hw =3D iris_vpu4x_power_on_hardware, + .power_off_controller =3D iris_vpu35_vpu4x_power_off_controller, + .power_on_controller =3D iris_vpu35_vpu4x_power_on_controller, + .program_bootup_registers =3D iris_vpu35_vpu4x_program_bootup_registers, + .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, +}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 7cf4304604cca590544a938c7e811c202cea3d93..f6dffc613b822341fb21e12de6b= 1395202f62cde 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -12,6 +12,7 @@ extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; +extern const struct vpu_ops iris_vpu4x_ops; =20 struct vpu_ops { void (*power_off_hw)(struct iris_core *core); --=20 2.34.1