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Wed, 10 Dec 2025 04:36:30 -0800 (PST) Received: from hu-vgarodia-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29daeaab9c0sm185434615ad.68.2025.12.10.04.36.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 04:36:30 -0800 (PST) From: Vikash Garodia Date: Wed, 10 Dec 2025 18:06:01 +0530 Subject: [PATCH v4 3/6] media: iris: Introduce buffer size calculations for vpu4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-knp_video-v4-3-8d11d840358a@oss.qualcomm.com> References: <20251210-knp_video-v4-0-8d11d840358a@oss.qualcomm.com> In-Reply-To: <20251210-knp_video-v4-0-8d11d840358a@oss.qualcomm.com> To: Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Dmitry Baryshkov , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vishnu Reddy , Vikash Garodia X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765370172; l=19337; i=vikash.garodia@oss.qualcomm.com; s=20241104; h=from:subject:message-id; bh=MsAbpGG/bpYt/SELt7d1HSQlPaN/m6PVcKRtnM/GuYM=; b=xmTkouHRbnVJRL1CG8IzFw6Ut5Sb1ZYnUQlfn8akv/4SaFJN2q4iDByVVEJm4b21isuXr3tNV qwUWYPx1SQUBKYuuywEV465irMJopHEZeBCz5Q0/9s5enyzO3vWTBqa X-Developer-Key: i=vikash.garodia@oss.qualcomm.com; a=ed25519; pk=LY9Eqp4KiHWxzGNKGHbwRFEJOfRCSzG/rxQNmvZvaKE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEwMDEwMCBTYWx0ZWRfXxwtFqBtCM8pk xGzC0gGfsFhLIdPcX5B8nAKO7sIUuEEl6O/5GQajXiW8C54DgQph0XoCxmwk/0AhADzlVgwlB3b 67iXHE+9i2IaGhotiSc53C8OEyEdGsompftDHH0SGJN1Kl2JxbMx09shztdrZU4rAcXx/KLE8dS lYcFx5N1WBWB6lYytW8e3vCKQt9iLrUZu29HZDVJzLsSANaHcdf0W0dih4QaVsoNum19RkEc4zt gSlAroMTvaRwSjWZ3qy2gBOtYPIfheA6uHqNnoLUyJdMP769HkTn7+WlZE2n+Q4GE0lMtX+hiCT wqKT13SC+iVKfCwXCLGViFbT8VhjuvCeooKstCLg8Nlfh6PW53+TAJkJLf7NerQ5A+h8vM08pNB FT+mjVU0n1PlbIcKXXyAn4VCoLQViQ== X-Proofpoint-ORIG-GUID: iBoMsZNbcUTiUEitsU86LaRhaxBoko1U X-Proofpoint-GUID: iBoMsZNbcUTiUEitsU86LaRhaxBoko1U X-Authority-Analysis: v=2.4 cv=F/lat6hN c=1 sm=1 tr=0 ts=69396950 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=cGz8g7xL8HyzlM8u-pkA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-09_05,2025-12-09_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 adultscore=0 spamscore=0 priorityscore=1501 phishscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512100100 Introduces vp4 buffer size calculation for both encoder and decoder. Reuse the buffer size calculation which are common, while adding the vpu4 ones separately. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 342 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 24 ++ 2 files changed, 366 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index 4463be05ce165adef6b152eb0c155d2e6a7b3c36..30d037e38cf2c6dc711c2a4a6c8= 8c5156a58607b 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -1408,6 +1408,304 @@ static u32 iris_vpu_enc_vpss_size(struct iris_inst = *inst) return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0); } =20 +static inline u32 size_dpb_opb(u32 height, u32 lcu_size) +{ + u32 max_tile_height =3D ((height + lcu_size - 1) / lcu_size) * lcu_size += 8; + u32 dpb_opb =3D 3 * ((max_tile_height >> 3) * DMA_ALIGNMENT); + u32 num_luma_chrome_plane =3D 2; + + return ALIGN(dpb_opb, DMA_ALIGNMENT) * num_luma_chrome_plane; +} + +static u32 hfi_vpu4x_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 n= um_vpp_pipes) +{ + u32 vp9_top_lb, vp9_fe_left_lb, vp9_se_left_lb, dpb_opb, vp9d_qp, num_lcu= _per_pipe; + u32 lcu_size =3D 64; + + vp9_top_lb =3D ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height), DMA= _ALIGNMENT); + vp9_top_lb +=3D ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height)= , DMA_ALIGNMENT); + vp9_top_lb +=3D max3(DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_16_BYTES)= * + MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE, + DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_32_BYTES) * + MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE, + DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_64_BYTES) * + MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE); + vp9_top_lb =3D ALIGN(vp9_top_lb, DMA_ALIGNMENT); + vp9_top_lb +=3D ALIGN((DMA_ALIGNMENT * DIV_ROUND_UP(frame_width, lcu_size= )), + DMA_ALIGNMENT) * FE_TOP_CTRL_LINE_NUMBERS; + vp9_top_lb +=3D ALIGN(DMA_ALIGNMENT * 8 * DIV_ROUND_UP(frame_width, lcu_s= ize), + DMA_ALIGNMENT) * (FE_TOP_DATA_LUMA_LINE_NUMBERS + + FE_TOP_DATA_CHROMA_LINE_NUMBERS); + + num_lcu_per_pipe =3D (DIV_ROUND_UP(frame_height, lcu_size) / num_vpp_pipe= s) + + (DIV_ROUND_UP(frame_height, lcu_size) % num_vpp_pipes); + vp9_fe_left_lb =3D ALIGN((DMA_ALIGNMENT * num_lcu_per_pipe), DMA_ALIGNMEN= T) * + FE_LFT_CTRL_LINE_NUMBERS; + vp9_fe_left_lb +=3D ((ALIGN((DMA_ALIGNMENT * 8 * num_lcu_per_pipe), DMA_A= LIGNMENT) * + FE_LFT_DB_DATA_LINE_NUMBERS) + + ALIGN((DMA_ALIGNMENT * 3 * num_lcu_per_pipe), DMA_ALIGNMENT) + + ALIGN((DMA_ALIGNMENT * 4 * num_lcu_per_pipe), DMA_ALIGNMENT) + + (ALIGN((DMA_ALIGNMENT * 24 * num_lcu_per_pipe), DMA_ALIGNMENT) * + FE_LFT_LR_DATA_LINE_NUMBERS)); + vp9_fe_left_lb =3D vp9_fe_left_lb * num_vpp_pipes; + + vp9_se_left_lb =3D ALIGN(size_vpxd_lb_se_left_ctrl(frame_width, frame_hei= ght), + DMA_ALIGNMENT); + dpb_opb =3D size_dpb_opb(frame_height, lcu_size); + vp9d_qp =3D ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT); + + return vp9_top_lb + vp9_fe_left_lb + (vp9_se_left_lb * num_vpp_pipes) + + (dpb_opb * num_vpp_pipes) + vp9d_qp; +} + +static u32 hfi_vpu4x_buffer_line_vp9d(u32 frame_width, u32 frame_height, u= 32 _yuv_bufcount_min, + bool is_opb, u32 num_vpp_pipes) +{ + u32 lb_size =3D hfi_vpu4x_vp9d_lb_size(frame_width, frame_height, num_vpp= _pipes); + u32 dpb_obp_size =3D 0, lcu_size =3D 64; + + if (is_opb) + dpb_obp_size =3D size_dpb_opb(frame_height, lcu_size) * num_vpp_pipes; + + return lb_size + dpb_obp_size; +} + +static u32 iris_vpu4x_dec_line_size(struct iris_inst *inst) +{ + u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; + u32 out_min_count =3D inst->buffers[BUF_OUTPUT].min_count; + struct v4l2_format *f =3D inst->fmt_src; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + bool is_opb =3D false; + + if (iris_split_mode_enabled(inst)) + is_opb =3D true; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_line_h264d(width, height, is_opb, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_line_h265d(width, height, is_opb, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return hfi_vpu4x_buffer_line_vp9d(width, height, out_min_count, is_opb, + num_vpp_pipes); + + return 0; +} + +static u32 hfi_vpu4x_buffer_persist_h265d(u32 rpu_enabled) +{ + return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + H265_NUM_FRM_INF= O * + H265_DISPLAY_BUF_SIZE + (H265_NUM_TILE * sizeof(u32)) + (NUM_HW_PIC_BUF * + (SIZE_SEI_USERDATA + SIZE_H265D_ARP + SIZE_THREE_DIMENSION_USERDATA)) + + rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA), DMA_ALIGNMENT); +} + +static u32 hfi_vpu4x_buffer_persist_vp9d(void) +{ + return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, DMA_ALI= GNMENT) + + (ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) * 2) + + ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT) + + ALIGN(VP9_UDC_HEADER_BUF_SIZE, DMA_ALIGNMENT) + + ALIGN(VP9_NUM_FRAME_INFO_BUF * CCE_TILE_OFFSET_SIZE, DMA_ALIGNMENT) + + ALIGN(VP9_NUM_FRAME_INFO_BUF * VP9_FRAME_INFO_BUF_SIZE_VPU4X, DMA_ALIGNM= ENT) + + HDR10_HIST_EXTRADATA_SIZE; +} + +static u32 iris_vpu4x_dec_persist_size(struct iris_inst *inst) +{ + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_persist_h264d(); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_vpu4x_buffer_persist_h265d(0); + else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return hfi_vpu4x_buffer_persist_vp9d(); + + return 0; +} + +static u32 size_se_lb(u32 standard, u32 num_vpp_pipes_enc, + u32 frame_width_coded, u32 frame_height_coded) +{ + u32 se_tlb_size =3D ALIGN(frame_width_coded, DMA_ALIGNMENT); + u32 se_llb_size =3D (standard =3D=3D HFI_CODEC_ENCODE_HEVC) ? + ((frame_height_coded + BUFFER_ALIGNMENT_32_BYTES - 1) / + BUFFER_ALIGNMENT_32_BYTES) * LOG2_16 * LLB_UNIT_SIZE : + ((frame_height_coded + BUFFER_ALIGNMENT_16_BYTES - 1) / + BUFFER_ALIGNMENT_16_BYTES) * LOG2_32 * LLB_UNIT_SIZE; + + se_llb_size =3D ALIGN(se_llb_size, BUFFER_ALIGNMENT_32_BYTES); + + if (num_vpp_pipes_enc > 1) + se_llb_size =3D ALIGN(se_llb_size + BUFFER_ALIGNMENT_512_BYTES, + DMA_ALIGNMENT) * num_vpp_pipes_enc; + + return ALIGN(se_tlb_size + se_llb_size, DMA_ALIGNMENT); +} + +static u32 size_te_lb(bool is_ten_bit, u32 num_vpp_pipes_enc, u32 width_in= _lcus, + u32 frame_height_coded, u32 frame_width_coded) +{ + u32 num_pixel_10_bit =3D 3, num_pixel_8_bit =3D 2, num_pixel_te_llb =3D 3; + u32 te_llb_col_rc_size =3D ALIGN(32 * width_in_lcus / num_vpp_pipes_enc, + DMA_ALIGNMENT) * num_vpp_pipes_enc; + u32 te_tlb_recon_data_size =3D ALIGN((is_ten_bit ? num_pixel_10_bit : num= _pixel_8_bit) * + frame_width_coded, DMA_ALIGNMENT); + u32 te_llb_recon_data_size =3D ((1 + is_ten_bit) * num_pixel_te_llb * fra= me_height_coded + + num_vpp_pipes_enc - 1) / num_vpp_pipes_enc; + te_llb_recon_data_size =3D ALIGN(te_llb_recon_data_size, DMA_ALIGNMENT) *= num_vpp_pipes_enc; + + return ALIGN(te_llb_recon_data_size + te_llb_col_rc_size + te_tlb_recon_d= ata_size, + DMA_ALIGNMENT); +} + +static inline u32 calc_fe_tlb_size(u32 size_per_lcu, bool is_ten_bit) +{ + u32 num_pixels_fe_tlb_10_bit =3D 128, num_pixels_fe_tlb_8_bit =3D 64; + + return is_ten_bit ? (num_pixels_fe_tlb_10_bit * (size_per_lcu + 1)) : + (size_per_lcu * num_pixels_fe_tlb_8_bit); +} + +static u32 size_fe_lb(bool is_ten_bit, u32 standard, u32 num_vpp_pipes_enc, + u32 frame_height_coded, u32 frame_width_coded) +{ + u32 log2_lcu_size, num_cu_in_height_pipe, num_cu_in_width, + fb_llb_db_ctrl_size, fb_llb_db_luma_size, fb_llb_db_chroma_size, + fb_tlb_db_ctrl_size, fb_tlb_db_luma_size, fb_tlb_db_chroma_size, + fb_llb_sao_ctrl_size, fb_llb_sao_luma_size, fb_llb_sao_chroma_size, + fb_tlb_sao_ctrl_size, fb_tlb_sao_luma_size, fb_tlb_sao_chroma_size, + fb_lb_top_sdc_size, fb_lb_se_ctrl_size, fe_tlb_size, size_per_lcu; + + log2_lcu_size =3D (standard =3D=3D HFI_CODEC_ENCODE_HEVC) ? 5 : 4; + num_cu_in_height_pipe =3D ((frame_height_coded >> log2_lcu_size) + num_vp= p_pipes_enc - 1) / + num_vpp_pipes_enc; + num_cu_in_width =3D frame_width_coded >> log2_lcu_size; + + size_per_lcu =3D 2; + fe_tlb_size =3D calc_fe_tlb_size(size_per_lcu, 1); + fb_llb_db_ctrl_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_hei= ght_pipe; + fb_llb_db_ctrl_size =3D ALIGN(fb_llb_db_ctrl_size, DMA_ALIGNMENT) * num_v= pp_pipes_enc; + + size_per_lcu =3D (1 << (log2_lcu_size - 3)); + fe_tlb_size =3D calc_fe_tlb_size(size_per_lcu, is_ten_bit); + fb_llb_db_luma_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_hei= ght_pipe; + fb_llb_db_luma_size =3D ALIGN(fb_llb_db_luma_size, DMA_ALIGNMENT) * num_v= pp_pipes_enc; + + size_per_lcu =3D ((1 << (log2_lcu_size - 4)) * 2); + fe_tlb_size =3D calc_fe_tlb_size(size_per_lcu, is_ten_bit); + fb_llb_db_chroma_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_h= eight_pipe; + fb_llb_db_chroma_size =3D ALIGN(fb_llb_db_chroma_size, DMA_ALIGNMENT) * n= um_vpp_pipes_enc; + + size_per_lcu =3D 1; + fe_tlb_size =3D calc_fe_tlb_size(size_per_lcu, 1); + fb_tlb_db_ctrl_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_wid= th; + fb_llb_sao_ctrl_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_he= ight_pipe; + fb_llb_sao_ctrl_size =3D fb_llb_sao_ctrl_size * num_vpp_pipes_enc; + fb_tlb_sao_ctrl_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_wi= dth; + + size_per_lcu =3D ((1 << (log2_lcu_size - 3)) + 1); + fe_tlb_size =3D calc_fe_tlb_size(size_per_lcu, is_ten_bit); + fb_tlb_db_luma_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_wid= th; + + size_per_lcu =3D (2 * ((1 << (log2_lcu_size - 4)) + 1)); + fe_tlb_size =3D calc_fe_tlb_size(size_per_lcu, is_ten_bit); + fb_tlb_db_chroma_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_w= idth; + + fb_llb_sao_luma_size =3D BUFFER_ALIGNMENT_256_BYTES * num_vpp_pipes_enc; + fb_llb_sao_chroma_size =3D BUFFER_ALIGNMENT_256_BYTES * num_vpp_pipes_enc; + fb_tlb_sao_luma_size =3D BUFFER_ALIGNMENT_256_BYTES; + fb_tlb_sao_chroma_size =3D BUFFER_ALIGNMENT_256_BYTES; + fb_lb_top_sdc_size =3D ALIGN((FE_SDC_DATA_PER_BLOCK * (frame_width_coded = >> 5)), + DMA_ALIGNMENT); + fb_lb_se_ctrl_size =3D ALIGN((SE_CTRL_DATA_PER_BLOCK * (frame_width_coded= >> 5)), + DMA_ALIGNMENT); + + return fb_llb_db_ctrl_size + fb_llb_db_luma_size + fb_llb_db_chroma_size + + fb_tlb_db_ctrl_size + fb_tlb_db_luma_size + fb_tlb_db_chroma_size + + fb_llb_sao_ctrl_size + fb_llb_sao_luma_size + fb_llb_sao_chroma_size + + fb_tlb_sao_ctrl_size + fb_tlb_sao_luma_size + fb_tlb_sao_chroma_size + + fb_lb_top_sdc_size + fb_lb_se_ctrl_size; +} + +static u32 size_md_lb(u32 standard, u32 frame_width_coded, + u32 frame_height_coded, u32 num_vpp_pipes_enc) +{ + u32 md_tlb_size =3D ALIGN(frame_width_coded, DMA_ALIGNMENT); + u32 md_llb_size =3D (standard =3D=3D HFI_CODEC_ENCODE_HEVC) ? + ((frame_height_coded + BUFFER_ALIGNMENT_32_BYTES - 1) / + BUFFER_ALIGNMENT_32_BYTES) * LOG2_16 * LLB_UNIT_SIZE : + ((frame_height_coded + BUFFER_ALIGNMENT_16_BYTES - 1) / + BUFFER_ALIGNMENT_16_BYTES) * LOG2_32 * LLB_UNIT_SIZE; + + md_llb_size =3D ALIGN(md_llb_size, BUFFER_ALIGNMENT_32_BYTES); + + if (num_vpp_pipes_enc > 1) + md_llb_size =3D ALIGN(md_llb_size + BUFFER_ALIGNMENT_512_BYTES, + DMA_ALIGNMENT) * num_vpp_pipes_enc; + + md_llb_size =3D ALIGN(md_llb_size, DMA_ALIGNMENT); + + return ALIGN(md_tlb_size + md_llb_size, DMA_ALIGNMENT); +} + +static u32 size_dma_opb_lb(u32 num_vpp_pipes_enc, u32 frame_width_coded, + u32 frame_height_coded) +{ + u32 opb_packet_bytes =3D 128, opb_bpp =3D 128, opb_size_per_row =3D 6; + u32 dma_opb_wr_tlb_y_size =3D DIV_ROUND_UP(frame_width_coded, 16) * opb_p= acket_bytes; + u32 dma_opb_wr_tlb_uv_size =3D DIV_ROUND_UP(frame_width_coded, 16) * opb_= packet_bytes; + u32 dma_opb_wr2_tlb_y_size =3D ALIGN((opb_bpp * opb_size_per_row * frame_= height_coded / 8), + DMA_ALIGNMENT) * num_vpp_pipes_enc; + u32 dma_opb_wr2_tlb_uv_size =3D ALIGN((opb_bpp * opb_size_per_row * frame= _height_coded / 8), + DMA_ALIGNMENT) * num_vpp_pipes_enc; + + dma_opb_wr2_tlb_y_size =3D max(dma_opb_wr2_tlb_y_size, dma_opb_wr_tlb_y_s= ize << 1); + dma_opb_wr2_tlb_uv_size =3D max(dma_opb_wr2_tlb_uv_size, dma_opb_wr_tlb_u= v_size << 1); + + return ALIGN(dma_opb_wr_tlb_y_size + dma_opb_wr_tlb_uv_size + dma_opb_wr2= _tlb_y_size + + dma_opb_wr2_tlb_uv_size, DMA_ALIGNMENT); +} + +static u32 hfi_vpu4x_buffer_line_enc(u32 frame_width, u32 frame_height, + bool is_ten_bit, u32 num_vpp_pipes_enc, + u32 lcu_size, u32 standard) +{ + u32 width_in_lcus =3D (frame_width + lcu_size - 1) / lcu_size; + u32 height_in_lcus =3D (frame_height + lcu_size - 1) / lcu_size; + u32 frame_width_coded =3D width_in_lcus * lcu_size; + u32 frame_height_coded =3D height_in_lcus * lcu_size; + + u32 se_lb_size =3D size_se_lb(standard, num_vpp_pipes_enc, frame_width_co= ded, + frame_height_coded); + u32 te_lb_size =3D size_te_lb(is_ten_bit, num_vpp_pipes_enc, width_in_lcu= s, + frame_height_coded, frame_width_coded); + u32 fe_lb_size =3D size_fe_lb(is_ten_bit, standard, num_vpp_pipes_enc, fr= ame_height_coded, + frame_width_coded); + u32 md_lb_size =3D size_md_lb(standard, frame_width_coded, frame_height_c= oded, + num_vpp_pipes_enc); + u32 dma_opb_lb_size =3D size_dma_opb_lb(num_vpp_pipes_enc, frame_width_co= ded, + frame_height_coded); + u32 dse_lb_size =3D ALIGN((256 + (16 * (frame_width_coded >> 4))), DMA_AL= IGNMENT); + u32 size_vpss_lb_enc =3D size_vpss_line_buf_vpu33(num_vpp_pipes_enc, fram= e_width_coded, + frame_height_coded); + + return se_lb_size + te_lb_size + fe_lb_size + md_lb_size + dma_opb_lb_siz= e + + dse_lb_size + size_vpss_lb_enc; +} + +static u32 iris_vpu4x_enc_line_size(struct iris_inst *inst) +{ + u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; + u32 lcu_size =3D inst->codec =3D=3D V4L2_PIX_FMT_HEVC ? 32 : 16; + struct v4l2_format *f =3D inst->fmt_dst; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + + return hfi_vpu4x_buffer_line_enc(width, height, 0, num_vpp_pipes, + lcu_size, inst->codec); +} + static int output_min_count(struct iris_inst *inst) { int output_min_count =3D 4; @@ -1503,6 +1801,50 @@ u32 iris_vpu33_buf_size(struct iris_inst *inst, enum= iris_buffer_type buffer_typ return size; } =20 +u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buff= er_type) +{ + const struct iris_vpu_buf_type_handle *buf_type_handle_arr =3D NULL; + u32 size =3D 0, buf_type_handle_size =3D 0, i; + + static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle= [] =3D { + {BUF_BIN, iris_vpu_dec_bin_size }, + {BUF_COMV, iris_vpu_dec_comv_size }, + {BUF_NON_COMV, iris_vpu_dec_non_comv_size }, + {BUF_LINE, iris_vpu4x_dec_line_size }, + {BUF_PERSIST, iris_vpu4x_dec_persist_size }, + {BUF_DPB, iris_vpu_dec_dpb_size }, + {BUF_SCRATCH_1, iris_vpu_dec_scratch1_size }, + }; + + static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle= [] =3D { + {BUF_BIN, iris_vpu_enc_bin_size }, + {BUF_COMV, iris_vpu_enc_comv_size }, + {BUF_NON_COMV, iris_vpu_enc_non_comv_size }, + {BUF_LINE, iris_vpu4x_enc_line_size }, + {BUF_ARP, iris_vpu_enc_arp_size }, + {BUF_VPSS, iris_vpu_enc_vpss_size }, + {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size }, + {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size }, + }; + + if (inst->domain =3D=3D DECODER) { + buf_type_handle_size =3D ARRAY_SIZE(dec_internal_buf_type_handle); + buf_type_handle_arr =3D dec_internal_buf_type_handle; + } else if (inst->domain =3D=3D ENCODER) { + buf_type_handle_size =3D ARRAY_SIZE(enc_internal_buf_type_handle); + buf_type_handle_arr =3D enc_internal_buf_type_handle; + } + + for (i =3D 0; i < buf_type_handle_size; i++) { + if (buf_type_handle_arr[i].type =3D=3D buffer_type) { + size =3D buf_type_handle_arr[i].handle(inst); + break; + } + } + + return size; +} + static u32 internal_buffer_count(struct iris_inst *inst, enum iris_buffer_type buffer_type) { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.h index 04f0b7400a1e4e1d274d690a2761b9e57778e8b7..9aaff14c018efe243f524fec12b= 9d09db342ec0d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h @@ -47,7 +47,12 @@ struct iris_inst; #define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4) #define VP9_PROB_TABLE_SIZE (3840) #define VP9_FRAME_INFO_BUF_SIZE (6144) +#define VP9_FRAME_INFO_BUF_SIZE_VPU4X (6400) +#define BUFFER_ALIGNMENT_16_BYTES 16 #define BUFFER_ALIGNMENT_32_BYTES 32 +#define BUFFER_ALIGNMENT_64_BYTES 64 +#define BUFFER_ALIGNMENT_256_BYTES 256 +#define BUFFER_ALIGNMENT_512_BYTES 512 #define CCE_TILE_OFFSET_SIZE ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES) #define MAX_SUPERFRAME_HEADER_LEN (34) #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 @@ -66,6 +71,8 @@ struct iris_inst; #define H265_CABAC_HDR_RATIO_HD_TOT 2 #define H265_CABAC_RES_RATIO_HD_TOT 2 #define SIZE_H265D_VPP_CMD_PER_BUF (256) +#define SIZE_THREE_DIMENSION_USERDATA 768 +#define SIZE_H265D_ARP 9728 =20 #define VPX_DECODER_FRAME_CONCURENCY_LVL (2) #define VPX_DECODER_FRAME_BIN_HDR_BUDGET 1 @@ -76,6 +83,18 @@ struct iris_inst; =20 #define SIZE_H264D_HW_PIC_T (BIT(11)) =20 +#define FE_LFT_CTRL_LINE_NUMBERS 4 +#define FE_LFT_DB_DATA_LINE_NUMBERS 2 +#define FE_LFT_LR_DATA_LINE_NUMBERS 4 +#define FE_TOP_CTRL_LINE_NUMBERS 3 +#define FE_TOP_DATA_LUMA_LINE_NUMBERS 2 +#define FE_TOP_DATA_CHROMA_LINE_NUMBERS 3 +#define FE_SDC_DATA_PER_BLOCK 16 +#define SE_CTRL_DATA_PER_BLOCK 2020 + +#define MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE 96 +#define MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE 192 + #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 #define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16 #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384 @@ -96,6 +115,10 @@ struct iris_inst; =20 #define HFI_BUFFER_ARP_ENC 204800 =20 +#define LOG2_16 4 +#define LOG2_32 5 +#define LLB_UNIT_SIZE 16 + #define MAX_WIDTH 4096 #define MAX_HEIGHT 2304 #define NUM_MBS_4K (DIV_ROUND_UP(MAX_WIDTH, 16) * DIV_ROUND_UP(MAX_HEIGHT,= 16)) @@ -148,6 +171,7 @@ static inline u32 size_h264d_qp(u32 frame_width, u32 fr= ame_height) =20 u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer= _type); u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buff= er_type); +u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buff= er_type); int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffe= r_type); =20 #endif --=20 2.34.1