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Thus far hardware versions up to vpu3x have been clocked by a single source. This adds support for multiple clocks by, - Adding a lookup table - Configuring OPP table for video device with different video clocks - Setting OPP for multiple clocks during dev_pm_opp_set_opp() This patch extends the support for multiple clocks in driver, which would be used in subsequent patch for kaanapali, when the platform data is prepared. Reviewed-by: Bryan O'Donoghue Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- .../media/platform/qcom/iris/iris_platform_common.h | 1 + .../media/platform/qcom/iris/iris_platform_gen1.c | 7 +++++++ .../media/platform/qcom/iris/iris_platform_gen2.c | 9 +++++++++ .../media/platform/qcom/iris/iris_platform_sc7280.h | 5 +++++ drivers/media/platform/qcom/iris/iris_power.c | 2 +- drivers/media/platform/qcom/iris/iris_probe.c | 20 ++++++++--------= ---- drivers/media/platform/qcom/iris/iris_resources.c | 16 ++++++++++++++-- drivers/media/platform/qcom/iris/iris_resources.h | 1 + drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++-- 9 files changed, 48 insertions(+), 17 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 8d8cdb56a3c7722c06287d4d10feed14ba2b254c..f63fb58b2fa87d31407be0f1452= 4c963edd85d68 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -209,6 +209,7 @@ struct iris_platform_data { const char * const *opp_pd_tbl; unsigned int opp_pd_tbl_size; const struct platform_clk_data *clk_tbl; + const char * const *opp_clk_tbl; unsigned int clk_tbl_size; const char * const *clk_rst_tbl; unsigned int clk_rst_tbl_size; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_platform_gen1.c index 34cbeb8f52e248b6aec3e0ee911e14d50df07cce..6092667687bfe34a52f3ec4865f= 99eddeea435a8 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -273,6 +273,11 @@ static const struct platform_clk_data sm8250_clk_table= [] =3D { {IRIS_HW_CLK, "vcodec0_core" }, }; =20 +static const char * const sm8250_opp_clk_table[] =3D { + "vcodec0_core", + NULL, +}; + static struct tz_cp_config tz_cp_config_sm8250 =3D { .cp_start =3D 0, .cp_size =3D 0x25800000, @@ -333,6 +338,7 @@ const struct iris_platform_data sm8250_data =3D { .opp_pd_tbl_size =3D ARRAY_SIZE(sm8250_opp_pd_table), .clk_tbl =3D sm8250_clk_table, .clk_tbl_size =3D ARRAY_SIZE(sm8250_clk_table), + .opp_clk_tbl =3D sm8250_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu-1.0/venus.mbn", @@ -382,6 +388,7 @@ const struct iris_platform_data sc7280_data =3D { .opp_pd_tbl_size =3D ARRAY_SIZE(sc7280_opp_pd_table), .clk_tbl =3D sc7280_clk_table, .clk_tbl_size =3D ARRAY_SIZE(sc7280_clk_table), + .opp_clk_tbl =3D sc7280_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu20_p1.mbn", diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index c1989240c248601c34b84f508f1b72d72f81260a..65860e3f43700ddb70eba617d78= 971c47945d008 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -631,6 +631,11 @@ static const struct platform_clk_data sm8550_clk_table= [] =3D { {IRIS_HW_CLK, "vcodec0_core" }, }; =20 +static const char * const sm8550_opp_clk_table[] =3D { + "vcodec0_core", + NULL, +}; + static struct ubwc_config_data ubwc_config_sm8550 =3D { .max_channels =3D 8, .mal_length =3D 32, @@ -755,6 +760,7 @@ const struct iris_platform_data sm8550_data =3D { .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), .clk_tbl =3D sm8550_clk_table, .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu30_p4.mbn", @@ -847,6 +853,7 @@ const struct iris_platform_data sm8650_data =3D { .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), .clk_tbl =3D sm8550_clk_table, .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu33_p4.mbn", @@ -929,6 +936,7 @@ const struct iris_platform_data sm8750_data =3D { .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), .clk_tbl =3D sm8750_clk_table, .clk_tbl_size =3D ARRAY_SIZE(sm8750_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu35_p4.mbn", @@ -1015,6 +1023,7 @@ const struct iris_platform_data qcs8300_data =3D { .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), .clk_tbl =3D sm8550_clk_table, .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu30_p4_s6.mbn", diff --git a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h b/driv= ers/media/platform/qcom/iris/iris_platform_sc7280.h index f1bef4d4bcfe8e58e2f18cff23c3c067f25d8bc3..0ec8f334df670c3c1548a5ee3b8= 907b333e34db3 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h @@ -23,4 +23,9 @@ static const struct platform_clk_data sc7280_clk_table[] = =3D { {IRIS_HW_AHB_CLK, "vcodec_bus" }, }; =20 +static const char * const sc7280_opp_clk_table[] =3D { + "vcodec_core", + NULL, +}; + #endif diff --git a/drivers/media/platform/qcom/iris/iris_power.c b/drivers/media/= platform/qcom/iris/iris_power.c index dbca42df0910fd3c0fb253dbfabf1afa2c3d32ad..91aa21d4070ebcebbe2ed127a03= e5e49b9a2bd5c 100644 --- a/drivers/media/platform/qcom/iris/iris_power.c +++ b/drivers/media/platform/qcom/iris/iris_power.c @@ -91,7 +91,7 @@ static int iris_set_clocks(struct iris_inst *inst) } =20 core->power.clk_freq =3D freq; - ret =3D dev_pm_opp_set_rate(core->dev, freq); + ret =3D iris_opp_set_rate(core->dev, freq); mutex_unlock(&core->lock); =20 return ret; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 9bc9b34c2576581635fa8d87eed1965657eb3eb3..ddaacda523ecb9990af0dd06401= 96223fbcc2cab 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -40,8 +40,6 @@ static int iris_init_icc(struct iris_core *core) =20 static int iris_init_power_domains(struct iris_core *core) { - const struct platform_clk_data *clk_tbl; - u32 clk_cnt, i; int ret; =20 struct dev_pm_domain_attach_data iris_pd_data =3D { @@ -56,6 +54,11 @@ static int iris_init_power_domains(struct iris_core *cor= e) .pd_flags =3D PD_FLAG_DEV_LINK_ON | PD_FLAG_REQUIRED_OPP, }; =20 + struct dev_pm_opp_config iris_opp_clk_data =3D { + .clk_names =3D core->iris_platform_data->opp_clk_tbl, + .config_clks =3D dev_pm_opp_config_clks_simple, + }; + ret =3D devm_pm_domain_attach_list(core->dev, &iris_pd_data, &core->pmdom= ain_tbl); if (ret < 0) return ret; @@ -64,16 +67,9 @@ static int iris_init_power_domains(struct iris_core *cor= e) if (ret < 0) return ret; =20 - clk_tbl =3D core->iris_platform_data->clk_tbl; - clk_cnt =3D core->iris_platform_data->clk_tbl_size; - - for (i =3D 0; i < clk_cnt; i++) { - if (clk_tbl[i].clk_type =3D=3D IRIS_HW_CLK) { - ret =3D devm_pm_opp_set_clkname(core->dev, clk_tbl[i].clk_name); - if (ret) - return ret; - } - } + ret =3D devm_pm_opp_set_config(core->dev, &iris_opp_clk_data); + if (ret) + return ret; =20 return devm_pm_opp_of_add_table(core->dev); } diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/me= dia/platform/qcom/iris/iris_resources.c index 164490c49c95ee048670981fdab014d20436ef85..773f6548370a257b8ae73322425= 44266cbbd61a9 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -58,11 +59,22 @@ int iris_unset_icc_bw(struct iris_core *core) return icc_bulk_set_bw(core->icc_count, core->icc_tbl); } =20 +int iris_opp_set_rate(struct device *dev, unsigned long freq) +{ + struct dev_pm_opp *opp __free(put_opp); + + opp =3D devfreq_recommended_opp(dev, &freq, 0); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + return dev_pm_opp_set_opp(dev, opp); +} + int iris_enable_power_domains(struct iris_core *core, struct device *pd_de= v) { int ret; =20 - ret =3D dev_pm_opp_set_rate(core->dev, ULONG_MAX); + ret =3D iris_opp_set_rate(core->dev, ULONG_MAX); if (ret) return ret; =20 @@ -77,7 +89,7 @@ int iris_disable_power_domains(struct iris_core *core, st= ruct device *pd_dev) { int ret; =20 - ret =3D dev_pm_opp_set_rate(core->dev, 0); + ret =3D iris_opp_set_rate(core->dev, 0); if (ret) return ret; =20 diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/me= dia/platform/qcom/iris/iris_resources.h index f723dfe5bd81a9c9db22d53bde4e18743d771210..6bfbd2dc6db095ec05e53c894e0= 48285f82446c6 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -8,6 +8,7 @@ =20 struct iris_core; =20 +int iris_opp_set_rate(struct device *dev, unsigned long freq); int iris_enable_power_domains(struct iris_core *core, struct device *pd_de= v); int iris_disable_power_domains(struct iris_core *core, struct device *pd_d= ev); int iris_unset_icc_bw(struct iris_core *core); diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 515dd55a3377e5d4d131e360f361a44a0a92505b..fef192a2de48fa47af421632829= 184c5896326cd 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -270,7 +270,7 @@ void iris_vpu_power_off_hw(struct iris_core *core) =20 void iris_vpu_power_off(struct iris_core *core) { - dev_pm_opp_set_rate(core->dev, 0); + iris_opp_set_rate(core->dev, 0); core->iris_platform_data->vpu_ops->power_off_hw(core); core->iris_platform_data->vpu_ops->power_off_controller(core); iris_unset_icc_bw(core); @@ -368,7 +368,7 @@ int iris_vpu_power_on(struct iris_core *core) freq =3D core->power.clk_freq ? core->power.clk_freq : (u32)ULONG_MAX; =20 - dev_pm_opp_set_rate(core->dev, freq); + iris_opp_set_rate(core->dev, freq); =20 core->iris_platform_data->set_preset_registers(core); =20 --=20 2.34.1