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Thus far hardware versions up to vpu3x have been clocked by a single source. This adds support for multiple clocks by, - Adding a lookup table - Configuring OPP table for video device with different video clocks - Setting OPP for multiple clocks during dev_pm_opp_set_opp() This patch extends the support for multiple clocks in driver, which would be used in subsequent patch for kaanapali, when the platform data is prepared. Reviewed-by: Bryan O'Donoghue Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- .../media/platform/qcom/iris/iris_platform_common.h | 1 + .../media/platform/qcom/iris/iris_platform_gen1.c | 7 +++++++ .../media/platform/qcom/iris/iris_platform_gen2.c | 9 +++++++++ .../media/platform/qcom/iris/iris_platform_sc7280.h | 5 +++++ drivers/media/platform/qcom/iris/iris_power.c | 2 +- drivers/media/platform/qcom/iris/iris_probe.c | 20 ++++++++--------= ---- drivers/media/platform/qcom/iris/iris_resources.c | 16 ++++++++++++++-- drivers/media/platform/qcom/iris/iris_resources.h | 1 + drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++-- 9 files changed, 48 insertions(+), 17 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 8d8cdb56a3c7722c06287d4d10feed14ba2b254c..f63fb58b2fa87d31407be0f1452= 4c963edd85d68 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -209,6 +209,7 @@ struct iris_platform_data { const char * const *opp_pd_tbl; unsigned int opp_pd_tbl_size; const struct platform_clk_data *clk_tbl; + const char * const *opp_clk_tbl; unsigned int clk_tbl_size; const char * const *clk_rst_tbl; unsigned int clk_rst_tbl_size; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_platform_gen1.c index 34cbeb8f52e248b6aec3e0ee911e14d50df07cce..6092667687bfe34a52f3ec4865f= 99eddeea435a8 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -273,6 +273,11 @@ static const struct platform_clk_data sm8250_clk_table= [] =3D { {IRIS_HW_CLK, "vcodec0_core" }, }; =20 +static const char * const sm8250_opp_clk_table[] =3D { + "vcodec0_core", + NULL, +}; + static struct tz_cp_config tz_cp_config_sm8250 =3D { .cp_start =3D 0, .cp_size =3D 0x25800000, @@ -333,6 +338,7 @@ const struct iris_platform_data sm8250_data =3D { .opp_pd_tbl_size =3D ARRAY_SIZE(sm8250_opp_pd_table), .clk_tbl =3D sm8250_clk_table, .clk_tbl_size =3D ARRAY_SIZE(sm8250_clk_table), + .opp_clk_tbl =3D sm8250_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu-1.0/venus.mbn", @@ -382,6 +388,7 @@ const struct iris_platform_data sc7280_data =3D { .opp_pd_tbl_size =3D ARRAY_SIZE(sc7280_opp_pd_table), .clk_tbl =3D sc7280_clk_table, .clk_tbl_size =3D ARRAY_SIZE(sc7280_clk_table), + .opp_clk_tbl =3D sc7280_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu20_p1.mbn", diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index c1989240c248601c34b84f508f1b72d72f81260a..65860e3f43700ddb70eba617d78= 971c47945d008 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -631,6 +631,11 @@ static const struct platform_clk_data sm8550_clk_table= [] =3D { {IRIS_HW_CLK, "vcodec0_core" }, }; =20 +static const char * const sm8550_opp_clk_table[] =3D { + "vcodec0_core", + NULL, +}; + static struct ubwc_config_data ubwc_config_sm8550 =3D { .max_channels =3D 8, .mal_length =3D 32, @@ -755,6 +760,7 @@ const struct iris_platform_data sm8550_data =3D { .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), .clk_tbl =3D sm8550_clk_table, .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu30_p4.mbn", @@ -847,6 +853,7 @@ const struct iris_platform_data sm8650_data =3D { .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), .clk_tbl =3D sm8550_clk_table, .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu33_p4.mbn", @@ -929,6 +936,7 @@ const struct iris_platform_data sm8750_data =3D { .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), .clk_tbl =3D sm8750_clk_table, .clk_tbl_size =3D ARRAY_SIZE(sm8750_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu35_p4.mbn", @@ -1015,6 +1023,7 @@ const struct iris_platform_data qcs8300_data =3D { .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), .clk_tbl =3D sm8550_clk_table, .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu30_p4_s6.mbn", diff --git a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h b/driv= ers/media/platform/qcom/iris/iris_platform_sc7280.h index f1bef4d4bcfe8e58e2f18cff23c3c067f25d8bc3..0ec8f334df670c3c1548a5ee3b8= 907b333e34db3 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h @@ -23,4 +23,9 @@ static const struct platform_clk_data sc7280_clk_table[] = =3D { {IRIS_HW_AHB_CLK, "vcodec_bus" }, }; =20 +static const char * const sc7280_opp_clk_table[] =3D { + "vcodec_core", + NULL, +}; + #endif diff --git a/drivers/media/platform/qcom/iris/iris_power.c b/drivers/media/= platform/qcom/iris/iris_power.c index dbca42df0910fd3c0fb253dbfabf1afa2c3d32ad..91aa21d4070ebcebbe2ed127a03= e5e49b9a2bd5c 100644 --- a/drivers/media/platform/qcom/iris/iris_power.c +++ b/drivers/media/platform/qcom/iris/iris_power.c @@ -91,7 +91,7 @@ static int iris_set_clocks(struct iris_inst *inst) } =20 core->power.clk_freq =3D freq; - ret =3D dev_pm_opp_set_rate(core->dev, freq); + ret =3D iris_opp_set_rate(core->dev, freq); mutex_unlock(&core->lock); =20 return ret; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 9bc9b34c2576581635fa8d87eed1965657eb3eb3..ddaacda523ecb9990af0dd06401= 96223fbcc2cab 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -40,8 +40,6 @@ static int iris_init_icc(struct iris_core *core) =20 static int iris_init_power_domains(struct iris_core *core) { - const struct platform_clk_data *clk_tbl; - u32 clk_cnt, i; int ret; =20 struct dev_pm_domain_attach_data iris_pd_data =3D { @@ -56,6 +54,11 @@ static int iris_init_power_domains(struct iris_core *cor= e) .pd_flags =3D PD_FLAG_DEV_LINK_ON | PD_FLAG_REQUIRED_OPP, }; =20 + struct dev_pm_opp_config iris_opp_clk_data =3D { + .clk_names =3D core->iris_platform_data->opp_clk_tbl, + .config_clks =3D dev_pm_opp_config_clks_simple, + }; + ret =3D devm_pm_domain_attach_list(core->dev, &iris_pd_data, &core->pmdom= ain_tbl); if (ret < 0) return ret; @@ -64,16 +67,9 @@ static int iris_init_power_domains(struct iris_core *cor= e) if (ret < 0) return ret; =20 - clk_tbl =3D core->iris_platform_data->clk_tbl; - clk_cnt =3D core->iris_platform_data->clk_tbl_size; - - for (i =3D 0; i < clk_cnt; i++) { - if (clk_tbl[i].clk_type =3D=3D IRIS_HW_CLK) { - ret =3D devm_pm_opp_set_clkname(core->dev, clk_tbl[i].clk_name); - if (ret) - return ret; - } - } + ret =3D devm_pm_opp_set_config(core->dev, &iris_opp_clk_data); + if (ret) + return ret; =20 return devm_pm_opp_of_add_table(core->dev); } diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/me= dia/platform/qcom/iris/iris_resources.c index 164490c49c95ee048670981fdab014d20436ef85..773f6548370a257b8ae73322425= 44266cbbd61a9 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -58,11 +59,22 @@ int iris_unset_icc_bw(struct iris_core *core) return icc_bulk_set_bw(core->icc_count, core->icc_tbl); } =20 +int iris_opp_set_rate(struct device *dev, unsigned long freq) +{ + struct dev_pm_opp *opp __free(put_opp); + + opp =3D devfreq_recommended_opp(dev, &freq, 0); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + return dev_pm_opp_set_opp(dev, opp); +} + int iris_enable_power_domains(struct iris_core *core, struct device *pd_de= v) { int ret; =20 - ret =3D dev_pm_opp_set_rate(core->dev, ULONG_MAX); + ret =3D iris_opp_set_rate(core->dev, ULONG_MAX); if (ret) return ret; =20 @@ -77,7 +89,7 @@ int iris_disable_power_domains(struct iris_core *core, st= ruct device *pd_dev) { int ret; =20 - ret =3D dev_pm_opp_set_rate(core->dev, 0); + ret =3D iris_opp_set_rate(core->dev, 0); if (ret) return ret; =20 diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/me= dia/platform/qcom/iris/iris_resources.h index f723dfe5bd81a9c9db22d53bde4e18743d771210..6bfbd2dc6db095ec05e53c894e0= 48285f82446c6 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -8,6 +8,7 @@ =20 struct iris_core; =20 +int iris_opp_set_rate(struct device *dev, unsigned long freq); int iris_enable_power_domains(struct iris_core *core, struct device *pd_de= v); int iris_disable_power_domains(struct iris_core *core, struct device *pd_d= ev); int iris_unset_icc_bw(struct iris_core *core); diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 515dd55a3377e5d4d131e360f361a44a0a92505b..fef192a2de48fa47af421632829= 184c5896326cd 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -270,7 +270,7 @@ void iris_vpu_power_off_hw(struct iris_core *core) =20 void iris_vpu_power_off(struct iris_core *core) { - dev_pm_opp_set_rate(core->dev, 0); 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Make the CP configuration as array such that the multiple configuration can be managed per platform. Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_firmware.c | 23 ++++++++++++------= --- .../platform/qcom/iris/iris_platform_common.h | 3 ++- .../media/platform/qcom/iris/iris_platform_gen1.c | 18 +++++++++------- .../media/platform/qcom/iris/iris_platform_gen2.c | 24 ++++++++++++++----= ---- 4 files changed, 41 insertions(+), 27 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/med= ia/platform/qcom/iris/iris_firmware.c index 679444327ed73a40c5cacd36f4156fc94c9ca45f..5f408024e967fd21ade66cc3fa3= 77d8507f9002e 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -64,9 +64,9 @@ static int iris_load_fw_to_memory(struct iris_core *core,= const char *fw_name) =20 int iris_fw_load(struct iris_core *core) { - struct tz_cp_config *cp_config =3D core->iris_platform_data->tz_cp_config= _data; + const struct tz_cp_config *cp_config; const char *fwpath =3D NULL; - int ret; + int i, ret; =20 ret =3D of_property_read_string_index(core->dev->of_node, "firmware-name"= , 0, &fwpath); @@ -85,14 +85,17 @@ int iris_fw_load(struct iris_core *core) return ret; } =20 - ret =3D qcom_scm_mem_protect_video_var(cp_config->cp_start, - cp_config->cp_size, - cp_config->cp_nonpixel_start, - cp_config->cp_nonpixel_size); - if (ret) { - dev_err(core->dev, "protect memory failed\n"); - qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); - return ret; + for (i =3D 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) { + cp_config =3D &core->iris_platform_data->tz_cp_config_data[i]; + ret =3D qcom_scm_mem_protect_video_var(cp_config->cp_start, + cp_config->cp_size, + cp_config->cp_nonpixel_start, + cp_config->cp_nonpixel_size); + if (ret) { + dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret); + qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); + return ret; + } } =20 return ret; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index f63fb58b2fa87d31407be0f14524c963edd85d68..29900c3ea9b9ebbab614c804a24= 9b08ba6001494 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -223,7 +223,8 @@ struct iris_platform_data { u32 inst_fw_caps_dec_size; const struct platform_inst_fw_cap *inst_fw_caps_enc; u32 inst_fw_caps_enc_size; - struct tz_cp_config *tz_cp_config_data; + const struct tz_cp_config *tz_cp_config_data; + u32 tz_cp_config_data_size; u32 core_arch; u32 hw_response_timeout; struct ubwc_config_data *ubwc_config; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_platform_gen1.c index 6092667687bfe34a52f3ec4865f99eddeea435a8..d1dda98271fb7ecdc396fe1a2df= da1b73720dec8 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -278,11 +278,13 @@ static const char * const sm8250_opp_clk_table[] =3D { NULL, }; =20 -static struct tz_cp_config tz_cp_config_sm8250 =3D { - .cp_start =3D 0, - .cp_size =3D 0x25800000, - .cp_nonpixel_start =3D 0x01000000, - .cp_nonpixel_size =3D 0x24800000, +static const struct tz_cp_config tz_cp_config_sm8250[] =3D { + { + .cp_start =3D 0, + .cp_size =3D 0x25800000, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, + }, }; =20 static const u32 sm8250_vdec_input_config_param_default[] =3D { @@ -348,7 +350,8 @@ const struct iris_platform_data sm8250_data =3D { .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), - .tz_cp_config_data =3D &tz_cp_config_sm8250, + .tz_cp_config_data =3D tz_cp_config_sm8250, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe =3D 4, .max_session_count =3D 16, @@ -398,7 +401,8 @@ const struct iris_platform_data sc7280_data =3D { .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), - .tz_cp_config_data =3D &tz_cp_config_sm8250, + .tz_cp_config_data =3D tz_cp_config_sm8250, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe =3D 1, .no_aon =3D true, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 65860e3f43700ddb70eba617d78971c47945d008..38734293d811cd5a12244797dd0= cfcd95e3fb311 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -646,11 +646,13 @@ static struct ubwc_config_data ubwc_config_sm8550 =3D= { .bank_spreading =3D 1, }; =20 -static struct tz_cp_config tz_cp_config_sm8550 =3D { - .cp_start =3D 0, - .cp_size =3D 0x25800000, - .cp_nonpixel_start =3D 0x01000000, - .cp_nonpixel_size =3D 0x24800000, +static const struct tz_cp_config tz_cp_config_sm8550[] =3D { + { + .cp_start =3D 0, + .cp_size =3D 0x25800000, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, + }, }; =20 static const u32 sm8550_vdec_input_config_params_default[] =3D { @@ -770,7 +772,8 @@ const struct iris_platform_data sm8550_data =3D { .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), - .tz_cp_config_data =3D &tz_cp_config_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), .core_arch =3D VIDEO_ARCH_LX, .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config =3D &ubwc_config_sm8550, @@ -863,7 +866,8 @@ const struct iris_platform_data sm8650_data =3D { .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), - .tz_cp_config_data =3D &tz_cp_config_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), .core_arch =3D VIDEO_ARCH_LX, .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config =3D &ubwc_config_sm8550, @@ -946,7 +950,8 @@ const struct iris_platform_data sm8750_data =3D { .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), - .tz_cp_config_data =3D &tz_cp_config_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), .core_arch =3D VIDEO_ARCH_LX, .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config =3D &ubwc_config_sm8550, @@ -1033,7 +1038,8 @@ const struct iris_platform_data qcs8300_data =3D { .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), - .tz_cp_config_data =3D &tz_cp_config_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), .core_arch =3D VIDEO_ARCH_LX, .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, .ubwc_config =3D &ubwc_config_sm8550, --=20 2.34.1 From nobody Mon Dec 15 00:33:12 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A830324B3E for ; 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Reuse the buffer size calculation which are common, while adding the vpu4 ones separately. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 342 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 24 ++ 2 files changed, 366 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index 4463be05ce165adef6b152eb0c155d2e6a7b3c36..30d037e38cf2c6dc711c2a4a6c8= 8c5156a58607b 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -1408,6 +1408,304 @@ static u32 iris_vpu_enc_vpss_size(struct iris_inst = *inst) return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0); } =20 +static inline u32 size_dpb_opb(u32 height, u32 lcu_size) +{ + u32 max_tile_height =3D ((height + lcu_size - 1) / lcu_size) * lcu_size += 8; + u32 dpb_opb =3D 3 * ((max_tile_height >> 3) * DMA_ALIGNMENT); + u32 num_luma_chrome_plane =3D 2; + + return ALIGN(dpb_opb, DMA_ALIGNMENT) * num_luma_chrome_plane; +} + +static u32 hfi_vpu4x_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 n= um_vpp_pipes) +{ + u32 vp9_top_lb, vp9_fe_left_lb, vp9_se_left_lb, dpb_opb, vp9d_qp, num_lcu= _per_pipe; + u32 lcu_size =3D 64; + + vp9_top_lb =3D ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height), DMA= _ALIGNMENT); + vp9_top_lb +=3D ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height)= , DMA_ALIGNMENT); + vp9_top_lb +=3D max3(DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_16_BYTES)= * + MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE, + DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_32_BYTES) * + MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE, + DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_64_BYTES) * + MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE); + vp9_top_lb =3D ALIGN(vp9_top_lb, DMA_ALIGNMENT); + vp9_top_lb +=3D ALIGN((DMA_ALIGNMENT * DIV_ROUND_UP(frame_width, lcu_size= )), + DMA_ALIGNMENT) * FE_TOP_CTRL_LINE_NUMBERS; + vp9_top_lb +=3D ALIGN(DMA_ALIGNMENT * 8 * DIV_ROUND_UP(frame_width, lcu_s= ize), + DMA_ALIGNMENT) * (FE_TOP_DATA_LUMA_LINE_NUMBERS + + FE_TOP_DATA_CHROMA_LINE_NUMBERS); + + num_lcu_per_pipe =3D (DIV_ROUND_UP(frame_height, lcu_size) / num_vpp_pipe= s) + + (DIV_ROUND_UP(frame_height, lcu_size) % num_vpp_pipes); + vp9_fe_left_lb =3D ALIGN((DMA_ALIGNMENT * num_lcu_per_pipe), DMA_ALIGNMEN= T) * + FE_LFT_CTRL_LINE_NUMBERS; + vp9_fe_left_lb +=3D ((ALIGN((DMA_ALIGNMENT * 8 * num_lcu_per_pipe), DMA_A= LIGNMENT) * + FE_LFT_DB_DATA_LINE_NUMBERS) + + ALIGN((DMA_ALIGNMENT * 3 * num_lcu_per_pipe), DMA_ALIGNMENT) + + ALIGN((DMA_ALIGNMENT * 4 * num_lcu_per_pipe), DMA_ALIGNMENT) + + (ALIGN((DMA_ALIGNMENT * 24 * num_lcu_per_pipe), DMA_ALIGNMENT) * + FE_LFT_LR_DATA_LINE_NUMBERS)); + vp9_fe_left_lb =3D vp9_fe_left_lb * num_vpp_pipes; + + vp9_se_left_lb =3D ALIGN(size_vpxd_lb_se_left_ctrl(frame_width, frame_hei= ght), + DMA_ALIGNMENT); + dpb_opb =3D size_dpb_opb(frame_height, lcu_size); + vp9d_qp =3D ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT); + + return vp9_top_lb + vp9_fe_left_lb + (vp9_se_left_lb * num_vpp_pipes) + + (dpb_opb * num_vpp_pipes) + vp9d_qp; +} + +static u32 hfi_vpu4x_buffer_line_vp9d(u32 frame_width, u32 frame_height, u= 32 _yuv_bufcount_min, + bool is_opb, u32 num_vpp_pipes) +{ + u32 lb_size =3D hfi_vpu4x_vp9d_lb_size(frame_width, frame_height, num_vpp= _pipes); + u32 dpb_obp_size =3D 0, lcu_size =3D 64; + + if (is_opb) + dpb_obp_size =3D size_dpb_opb(frame_height, lcu_size) * num_vpp_pipes; + + return lb_size + dpb_obp_size; +} + +static u32 iris_vpu4x_dec_line_size(struct iris_inst *inst) +{ + u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; + u32 out_min_count =3D inst->buffers[BUF_OUTPUT].min_count; + struct v4l2_format *f =3D inst->fmt_src; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + bool is_opb =3D false; + + if (iris_split_mode_enabled(inst)) + is_opb =3D true; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_line_h264d(width, height, is_opb, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_line_h265d(width, height, is_opb, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return hfi_vpu4x_buffer_line_vp9d(width, height, out_min_count, is_opb, + num_vpp_pipes); + + return 0; +} + +static u32 hfi_vpu4x_buffer_persist_h265d(u32 rpu_enabled) +{ + return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + H265_NUM_FRM_INF= O * + H265_DISPLAY_BUF_SIZE + (H265_NUM_TILE * sizeof(u32)) + (NUM_HW_PIC_BUF * + (SIZE_SEI_USERDATA + SIZE_H265D_ARP + SIZE_THREE_DIMENSION_USERDATA)) + + rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA), DMA_ALIGNMENT); +} + +static u32 hfi_vpu4x_buffer_persist_vp9d(void) +{ + return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, DMA_ALI= GNMENT) + + (ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) * 2) + + ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT) + + ALIGN(VP9_UDC_HEADER_BUF_SIZE, DMA_ALIGNMENT) + + ALIGN(VP9_NUM_FRAME_INFO_BUF * CCE_TILE_OFFSET_SIZE, DMA_ALIGNMENT) + + ALIGN(VP9_NUM_FRAME_INFO_BUF * VP9_FRAME_INFO_BUF_SIZE_VPU4X, DMA_ALIGNM= ENT) + + HDR10_HIST_EXTRADATA_SIZE; +} + +static u32 iris_vpu4x_dec_persist_size(struct iris_inst *inst) +{ + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_persist_h264d(); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_vpu4x_buffer_persist_h265d(0); + else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return hfi_vpu4x_buffer_persist_vp9d(); + + return 0; +} + +static u32 size_se_lb(u32 standard, u32 num_vpp_pipes_enc, + u32 frame_width_coded, u32 frame_height_coded) +{ + u32 se_tlb_size =3D ALIGN(frame_width_coded, DMA_ALIGNMENT); + u32 se_llb_size =3D (standard =3D=3D HFI_CODEC_ENCODE_HEVC) ? + ((frame_height_coded + BUFFER_ALIGNMENT_32_BYTES - 1) / + BUFFER_ALIGNMENT_32_BYTES) * LOG2_16 * LLB_UNIT_SIZE : + ((frame_height_coded + BUFFER_ALIGNMENT_16_BYTES - 1) / + BUFFER_ALIGNMENT_16_BYTES) * LOG2_32 * LLB_UNIT_SIZE; + + se_llb_size =3D ALIGN(se_llb_size, BUFFER_ALIGNMENT_32_BYTES); + + if (num_vpp_pipes_enc > 1) + se_llb_size =3D ALIGN(se_llb_size + BUFFER_ALIGNMENT_512_BYTES, + DMA_ALIGNMENT) * num_vpp_pipes_enc; + + return ALIGN(se_tlb_size + se_llb_size, DMA_ALIGNMENT); +} + +static u32 size_te_lb(bool is_ten_bit, u32 num_vpp_pipes_enc, u32 width_in= _lcus, + u32 frame_height_coded, u32 frame_width_coded) +{ + u32 num_pixel_10_bit =3D 3, num_pixel_8_bit =3D 2, num_pixel_te_llb =3D 3; + u32 te_llb_col_rc_size =3D ALIGN(32 * width_in_lcus / num_vpp_pipes_enc, + DMA_ALIGNMENT) * num_vpp_pipes_enc; + u32 te_tlb_recon_data_size =3D ALIGN((is_ten_bit ? num_pixel_10_bit : num= _pixel_8_bit) * + frame_width_coded, DMA_ALIGNMENT); + u32 te_llb_recon_data_size =3D ((1 + is_ten_bit) * num_pixel_te_llb * fra= me_height_coded + + num_vpp_pipes_enc - 1) / num_vpp_pipes_enc; + te_llb_recon_data_size =3D ALIGN(te_llb_recon_data_size, DMA_ALIGNMENT) *= num_vpp_pipes_enc; + + return ALIGN(te_llb_recon_data_size + te_llb_col_rc_size + te_tlb_recon_d= ata_size, + DMA_ALIGNMENT); +} + +static inline u32 calc_fe_tlb_size(u32 size_per_lcu, bool is_ten_bit) +{ + u32 num_pixels_fe_tlb_10_bit =3D 128, num_pixels_fe_tlb_8_bit =3D 64; + + return is_ten_bit ? (num_pixels_fe_tlb_10_bit * (size_per_lcu + 1)) : + (size_per_lcu * num_pixels_fe_tlb_8_bit); +} + +static u32 size_fe_lb(bool is_ten_bit, u32 standard, u32 num_vpp_pipes_enc, + u32 frame_height_coded, u32 frame_width_coded) +{ + u32 log2_lcu_size, num_cu_in_height_pipe, num_cu_in_width, + fb_llb_db_ctrl_size, fb_llb_db_luma_size, fb_llb_db_chroma_size, + fb_tlb_db_ctrl_size, fb_tlb_db_luma_size, fb_tlb_db_chroma_size, + fb_llb_sao_ctrl_size, fb_llb_sao_luma_size, fb_llb_sao_chroma_size, + fb_tlb_sao_ctrl_size, fb_tlb_sao_luma_size, fb_tlb_sao_chroma_size, + fb_lb_top_sdc_size, fb_lb_se_ctrl_size, fe_tlb_size, size_per_lcu; + + log2_lcu_size =3D (standard =3D=3D HFI_CODEC_ENCODE_HEVC) ? 5 : 4; + num_cu_in_height_pipe =3D ((frame_height_coded >> log2_lcu_size) + num_vp= p_pipes_enc - 1) / + num_vpp_pipes_enc; + num_cu_in_width =3D frame_width_coded >> log2_lcu_size; + + size_per_lcu =3D 2; + fe_tlb_size =3D calc_fe_tlb_size(size_per_lcu, 1); + fb_llb_db_ctrl_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_hei= ght_pipe; + fb_llb_db_ctrl_size =3D ALIGN(fb_llb_db_ctrl_size, DMA_ALIGNMENT) * num_v= pp_pipes_enc; + + size_per_lcu =3D (1 << (log2_lcu_size - 3)); + fe_tlb_size =3D calc_fe_tlb_size(size_per_lcu, is_ten_bit); + fb_llb_db_luma_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_hei= ght_pipe; + fb_llb_db_luma_size =3D ALIGN(fb_llb_db_luma_size, DMA_ALIGNMENT) * num_v= pp_pipes_enc; + + size_per_lcu =3D ((1 << (log2_lcu_size - 4)) * 2); + fe_tlb_size =3D calc_fe_tlb_size(size_per_lcu, is_ten_bit); + fb_llb_db_chroma_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_h= eight_pipe; + fb_llb_db_chroma_size =3D ALIGN(fb_llb_db_chroma_size, DMA_ALIGNMENT) * n= um_vpp_pipes_enc; + + size_per_lcu =3D 1; + fe_tlb_size =3D calc_fe_tlb_size(size_per_lcu, 1); + fb_tlb_db_ctrl_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_wid= th; + fb_llb_sao_ctrl_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_he= ight_pipe; + fb_llb_sao_ctrl_size =3D fb_llb_sao_ctrl_size * num_vpp_pipes_enc; + fb_tlb_sao_ctrl_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_wi= dth; + + size_per_lcu =3D ((1 << (log2_lcu_size - 3)) + 1); + fe_tlb_size =3D calc_fe_tlb_size(size_per_lcu, is_ten_bit); + fb_tlb_db_luma_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_wid= th; + + size_per_lcu =3D (2 * ((1 << (log2_lcu_size - 4)) + 1)); + fe_tlb_size =3D calc_fe_tlb_size(size_per_lcu, is_ten_bit); + fb_tlb_db_chroma_size =3D ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_w= idth; + + fb_llb_sao_luma_size =3D BUFFER_ALIGNMENT_256_BYTES * num_vpp_pipes_enc; + fb_llb_sao_chroma_size =3D BUFFER_ALIGNMENT_256_BYTES * num_vpp_pipes_enc; + fb_tlb_sao_luma_size =3D BUFFER_ALIGNMENT_256_BYTES; + fb_tlb_sao_chroma_size =3D BUFFER_ALIGNMENT_256_BYTES; + fb_lb_top_sdc_size =3D ALIGN((FE_SDC_DATA_PER_BLOCK * (frame_width_coded = >> 5)), + DMA_ALIGNMENT); + fb_lb_se_ctrl_size =3D ALIGN((SE_CTRL_DATA_PER_BLOCK * (frame_width_coded= >> 5)), + DMA_ALIGNMENT); + + return fb_llb_db_ctrl_size + fb_llb_db_luma_size + fb_llb_db_chroma_size + + fb_tlb_db_ctrl_size + fb_tlb_db_luma_size + fb_tlb_db_chroma_size + + fb_llb_sao_ctrl_size + fb_llb_sao_luma_size + fb_llb_sao_chroma_size + + fb_tlb_sao_ctrl_size + fb_tlb_sao_luma_size + fb_tlb_sao_chroma_size + + fb_lb_top_sdc_size + fb_lb_se_ctrl_size; +} + +static u32 size_md_lb(u32 standard, u32 frame_width_coded, + u32 frame_height_coded, u32 num_vpp_pipes_enc) +{ + u32 md_tlb_size =3D ALIGN(frame_width_coded, DMA_ALIGNMENT); + u32 md_llb_size =3D (standard =3D=3D HFI_CODEC_ENCODE_HEVC) ? + ((frame_height_coded + BUFFER_ALIGNMENT_32_BYTES - 1) / + BUFFER_ALIGNMENT_32_BYTES) * LOG2_16 * LLB_UNIT_SIZE : + ((frame_height_coded + BUFFER_ALIGNMENT_16_BYTES - 1) / + BUFFER_ALIGNMENT_16_BYTES) * LOG2_32 * LLB_UNIT_SIZE; + + md_llb_size =3D ALIGN(md_llb_size, BUFFER_ALIGNMENT_32_BYTES); + + if (num_vpp_pipes_enc > 1) + md_llb_size =3D ALIGN(md_llb_size + BUFFER_ALIGNMENT_512_BYTES, + DMA_ALIGNMENT) * num_vpp_pipes_enc; + + md_llb_size =3D ALIGN(md_llb_size, DMA_ALIGNMENT); + + return ALIGN(md_tlb_size + md_llb_size, DMA_ALIGNMENT); +} + +static u32 size_dma_opb_lb(u32 num_vpp_pipes_enc, u32 frame_width_coded, + u32 frame_height_coded) +{ + u32 opb_packet_bytes =3D 128, opb_bpp =3D 128, opb_size_per_row =3D 6; + u32 dma_opb_wr_tlb_y_size =3D DIV_ROUND_UP(frame_width_coded, 16) * opb_p= acket_bytes; + u32 dma_opb_wr_tlb_uv_size =3D DIV_ROUND_UP(frame_width_coded, 16) * opb_= packet_bytes; + u32 dma_opb_wr2_tlb_y_size =3D ALIGN((opb_bpp * opb_size_per_row * frame_= height_coded / 8), + DMA_ALIGNMENT) * num_vpp_pipes_enc; + u32 dma_opb_wr2_tlb_uv_size =3D ALIGN((opb_bpp * opb_size_per_row * frame= _height_coded / 8), + DMA_ALIGNMENT) * num_vpp_pipes_enc; + + dma_opb_wr2_tlb_y_size =3D max(dma_opb_wr2_tlb_y_size, dma_opb_wr_tlb_y_s= ize << 1); + dma_opb_wr2_tlb_uv_size =3D max(dma_opb_wr2_tlb_uv_size, dma_opb_wr_tlb_u= v_size << 1); + + return ALIGN(dma_opb_wr_tlb_y_size + dma_opb_wr_tlb_uv_size + dma_opb_wr2= _tlb_y_size + + dma_opb_wr2_tlb_uv_size, DMA_ALIGNMENT); +} + +static u32 hfi_vpu4x_buffer_line_enc(u32 frame_width, u32 frame_height, + bool is_ten_bit, u32 num_vpp_pipes_enc, + u32 lcu_size, u32 standard) +{ + u32 width_in_lcus =3D (frame_width + lcu_size - 1) / lcu_size; + u32 height_in_lcus =3D (frame_height + lcu_size - 1) / lcu_size; + u32 frame_width_coded =3D width_in_lcus * lcu_size; + u32 frame_height_coded =3D height_in_lcus * lcu_size; + + u32 se_lb_size =3D size_se_lb(standard, num_vpp_pipes_enc, frame_width_co= ded, + frame_height_coded); + u32 te_lb_size =3D size_te_lb(is_ten_bit, num_vpp_pipes_enc, width_in_lcu= s, + frame_height_coded, frame_width_coded); + u32 fe_lb_size =3D size_fe_lb(is_ten_bit, standard, num_vpp_pipes_enc, fr= ame_height_coded, + frame_width_coded); + u32 md_lb_size =3D size_md_lb(standard, frame_width_coded, frame_height_c= oded, + num_vpp_pipes_enc); + u32 dma_opb_lb_size =3D size_dma_opb_lb(num_vpp_pipes_enc, frame_width_co= ded, + frame_height_coded); + u32 dse_lb_size =3D ALIGN((256 + (16 * (frame_width_coded >> 4))), DMA_AL= IGNMENT); + u32 size_vpss_lb_enc =3D size_vpss_line_buf_vpu33(num_vpp_pipes_enc, fram= e_width_coded, + frame_height_coded); + + return se_lb_size + te_lb_size + fe_lb_size + md_lb_size + dma_opb_lb_siz= e + + dse_lb_size + size_vpss_lb_enc; +} + +static u32 iris_vpu4x_enc_line_size(struct iris_inst *inst) +{ + u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; + u32 lcu_size =3D inst->codec =3D=3D V4L2_PIX_FMT_HEVC ? 32 : 16; + struct v4l2_format *f =3D inst->fmt_dst; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + + return hfi_vpu4x_buffer_line_enc(width, height, 0, num_vpp_pipes, + lcu_size, inst->codec); +} + static int output_min_count(struct iris_inst *inst) { int output_min_count =3D 4; @@ -1503,6 +1801,50 @@ u32 iris_vpu33_buf_size(struct iris_inst *inst, enum= iris_buffer_type buffer_typ return size; } =20 +u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buff= er_type) +{ + const struct iris_vpu_buf_type_handle *buf_type_handle_arr =3D NULL; + u32 size =3D 0, buf_type_handle_size =3D 0, i; + + static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle= [] =3D { + {BUF_BIN, iris_vpu_dec_bin_size }, + {BUF_COMV, iris_vpu_dec_comv_size }, + {BUF_NON_COMV, iris_vpu_dec_non_comv_size }, + {BUF_LINE, iris_vpu4x_dec_line_size }, + {BUF_PERSIST, iris_vpu4x_dec_persist_size }, + {BUF_DPB, iris_vpu_dec_dpb_size }, + {BUF_SCRATCH_1, iris_vpu_dec_scratch1_size }, + }; + + static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle= [] =3D { + {BUF_BIN, iris_vpu_enc_bin_size }, + {BUF_COMV, iris_vpu_enc_comv_size }, + {BUF_NON_COMV, iris_vpu_enc_non_comv_size }, + {BUF_LINE, iris_vpu4x_enc_line_size }, + {BUF_ARP, iris_vpu_enc_arp_size }, + {BUF_VPSS, iris_vpu_enc_vpss_size }, + {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size }, + {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size }, + }; + + if (inst->domain =3D=3D DECODER) { + buf_type_handle_size =3D ARRAY_SIZE(dec_internal_buf_type_handle); + buf_type_handle_arr =3D dec_internal_buf_type_handle; + } else if (inst->domain =3D=3D ENCODER) { + buf_type_handle_size =3D ARRAY_SIZE(enc_internal_buf_type_handle); + buf_type_handle_arr =3D enc_internal_buf_type_handle; + } + + for (i =3D 0; i < buf_type_handle_size; i++) { + if (buf_type_handle_arr[i].type =3D=3D buffer_type) { + size =3D buf_type_handle_arr[i].handle(inst); + break; + } + } + + return size; +} + static u32 internal_buffer_count(struct iris_inst *inst, enum iris_buffer_type buffer_type) { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.h index 04f0b7400a1e4e1d274d690a2761b9e57778e8b7..9aaff14c018efe243f524fec12b= 9d09db342ec0d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h @@ -47,7 +47,12 @@ struct iris_inst; #define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4) #define VP9_PROB_TABLE_SIZE (3840) #define VP9_FRAME_INFO_BUF_SIZE (6144) +#define VP9_FRAME_INFO_BUF_SIZE_VPU4X (6400) +#define BUFFER_ALIGNMENT_16_BYTES 16 #define BUFFER_ALIGNMENT_32_BYTES 32 +#define BUFFER_ALIGNMENT_64_BYTES 64 +#define BUFFER_ALIGNMENT_256_BYTES 256 +#define BUFFER_ALIGNMENT_512_BYTES 512 #define CCE_TILE_OFFSET_SIZE ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES) #define MAX_SUPERFRAME_HEADER_LEN (34) #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 @@ -66,6 +71,8 @@ struct iris_inst; #define H265_CABAC_HDR_RATIO_HD_TOT 2 #define H265_CABAC_RES_RATIO_HD_TOT 2 #define SIZE_H265D_VPP_CMD_PER_BUF (256) +#define SIZE_THREE_DIMENSION_USERDATA 768 +#define SIZE_H265D_ARP 9728 =20 #define VPX_DECODER_FRAME_CONCURENCY_LVL (2) #define VPX_DECODER_FRAME_BIN_HDR_BUDGET 1 @@ -76,6 +83,18 @@ struct iris_inst; =20 #define SIZE_H264D_HW_PIC_T (BIT(11)) =20 +#define FE_LFT_CTRL_LINE_NUMBERS 4 +#define FE_LFT_DB_DATA_LINE_NUMBERS 2 +#define FE_LFT_LR_DATA_LINE_NUMBERS 4 +#define FE_TOP_CTRL_LINE_NUMBERS 3 +#define FE_TOP_DATA_LUMA_LINE_NUMBERS 2 +#define FE_TOP_DATA_CHROMA_LINE_NUMBERS 3 +#define FE_SDC_DATA_PER_BLOCK 16 +#define SE_CTRL_DATA_PER_BLOCK 2020 + +#define MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE 96 +#define MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE 192 + #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 #define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16 #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384 @@ -96,6 +115,10 @@ struct iris_inst; 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Move those into the common register defines header. This is done to reuse the defines for vpu4 in subsequent patch which enables the power sequence for vpu4. Reviewed-by: Bryan O'Donoghue Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 42 --------------- drivers/media/platform/qcom/iris/iris_vpu_common.c | 43 --------------- .../platform/qcom/iris/iris_vpu_register_defines.h | 61 ++++++++++++++++++= ++++ 3 files changed, 61 insertions(+), 85 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index 339776a0b4672e246848c3a6a260eb83c7da6a60..cd53bcda3b3e1d6f234486df49a= 51150a7ec9799 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -11,48 +11,6 @@ #include "iris_vpu_common.h" #include "iris_vpu_register_defines.h" =20 -#define WRAPPER_TZ_BASE_OFFS 0x000C0000 -#define AON_BASE_OFFS 0x000E0000 -#define AON_MVP_NOC_RESET 0x0001F000 - -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) -#define REQ_POWER_DOWN_PREP BIT(0) -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) -#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is com= plete */ -#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is den= ied */ -#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ -#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) -#define CORE_CLK_RUN 0x0 -/* VPU v3.5 */ -#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) - -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) -#define CTL_AXI_CLK_HALT BIT(0) -#define CTL_CLK_HALT BIT(1) - -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) -#define RESET_HIGH BIT(0) - -#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) -#define CORE_BRIDGE_SW_RESET BIT(0) -#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) - -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) -#define MSK_SIGNAL_FROM_TENSILICA BIT(0) -#define MSK_CORE_POWER_ON BIT(1) - -#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) -#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) - -#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004) - -#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) - -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) - #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18) #define SW_RESET BIT(0) #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index fef192a2de48fa47af421632829184c5896326cd..50242fc6b4653a7d74ff64500f4= 0eb8a859a6548 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -11,13 +11,6 @@ #include "iris_vpu_common.h" #include "iris_vpu_register_defines.h" =20 -#define WRAPPER_TZ_BASE_OFFS 0x000C0000 -#define AON_BASE_OFFS 0x000E0000 - -#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS) - -#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C) -#define CLEAR_XTENSA2HOST_INTR BIT(0) =20 #define CTRL_INIT (CPU_CS_BASE_OFFS + 0x48) #define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C) @@ -35,42 +28,6 @@ #define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64) #define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68) =20 -#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148) -#define HOST2XTENSA_INTR_ENABLE BIT(0) - -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) -#define MSK_SIGNAL_FROM_TENSILICA BIT(0) -#define MSK_CORE_POWER_ON BIT(1) - -#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150) -#define CPU_IC_SOFTINT_H2A_SHFT 0x0 - -#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C) -#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) -#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2) - -#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10) -#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3) -#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2) - -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) - -#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10) -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) -#define CTL_AXI_CLK_HALT BIT(0) -#define CTL_CLK_HALT BIT(1) - -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) -#define RESET_HIGH BIT(0) - -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) -#define REQ_POWER_DOWN_PREP BIT(0) - -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) - static void iris_vpu_interrupt_init(struct iris_core *core) { u32 mask_val; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b= /drivers/media/platform/qcom/iris/iris_vpu_register_defines.h index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..72168b9ffa7385d53d7190265d1= c0922ee04a656 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h @@ -7,11 +7,72 @@ #define __IRIS_VPU_REGISTER_DEFINES_H__ =20 #define VCODEC_BASE_OFFS 0x00000000 +#define AON_MVP_NOC_RESET 0x0001F000 #define CPU_BASE_OFFS 0x000A0000 #define WRAPPER_BASE_OFFS 0x000B0000 +#define WRAPPER_TZ_BASE_OFFS 0x000C0000 +#define AON_BASE_OFFS 0x000E0000 + +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) + +#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) +#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) + +#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004) =20 #define CPU_CS_BASE_OFFS (CPU_BASE_OFFS) +#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS) + +#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C) +#define CLEAR_XTENSA2HOST_INTR BIT(0) + +#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148) +#define HOST2XTENSA_INTR_ENABLE BIT(0) + +#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150) +#define CPU_IC_SOFTINT_H2A_SHFT 0x0 + +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) +#define CORE_BRIDGE_SW_RESET BIT(0) +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) + +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) +#define MSK_SIGNAL_FROM_TENSILICA BIT(0) +#define MSK_CORE_POWER_ON BIT(1) =20 +#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C) +#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) +#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2) + +#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10) +#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3) +#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2) + +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) +#define REQ_POWER_DOWN_PREP BIT(0) + +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is com= plete */ +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is den= ied */ +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ + +#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80) +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) +#define CORE_CLK_RUN 0x0 + +#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10) + +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) +#define CTL_AXI_CLK_HALT BIT(0) +#define CTL_CLK_HALT BIT(1) + +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) +#define RESET_HIGH BIT(0) + +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) =20 #endif --=20 2.34.1 From nobody Mon Dec 15 00:33:12 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23E31325714 for ; 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Move those to common file that can be shared for both vpu35 and vpu4. This patch prepares for power sequence for vpu4 which is added in subsequent patch. Reviewed-by: Bryan O'Donoghue Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 157 +----------------= ---- drivers/media/platform/qcom/iris/iris_vpu_common.c | 141 ++++++++++++++++++ drivers/media/platform/qcom/iris/iris_vpu_common.h | 4 + 3 files changed, 151 insertions(+), 151 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index cd53bcda3b3e1d6f234486df49a51150a7ec9799..fe4423b951b1e9e31d06dffc69d= 18071cc985731 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -16,8 +16,6 @@ #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20) #define NOC_HALT BIT(0) #define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28) -#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL (AON_BASE_OFFS + 0x2C) -#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS (AON_BASE_OFFS + 0x30) =20 static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) { @@ -262,155 +260,12 @@ static void iris_vpu35_power_off_hw(struct iris_core= *core) iris_disable_unprepare_clock(core, IRIS_AXI_CLK); } =20 -static int iris_vpu35_power_off_controller(struct iris_core *core) -{ - u32 clk_rst_tbl_size =3D core->iris_platform_data->clk_rst_tbl_size; - unsigned int count =3D 0; - u32 val =3D 0; - bool handshake_done, handshake_busy; - int ret; - - writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CP= U_CS_X2RPMH); - - writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CON= TROL); - - ret =3D readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STAT= US, - val, val & BIT(0), 200, 2000); - if (ret) - goto disable_power; - - writel(0, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL); - - /* Retry up to 1000 times as recommended by hardware documentation */ - do { - /* set MNoC to low power */ - writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_N= OC_LPI_CONTROL); - - udelay(15); - - val =3D readl(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS); - - handshake_done =3D val & NOC_LPI_STATUS_DONE; - handshake_busy =3D val & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE); - - if (handshake_done || !handshake_busy) - break; - - writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL); - - udelay(15); - - } while (++count < 1000); - - if (!handshake_done && handshake_busy) - dev_err(core->dev, "LPI handshake timeout\n"); - - ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC= _LPI_STATUS, - val, val & BIT(0), 200, 2000); - if (ret) - goto disable_power; - - writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL); - - writel(0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL); - - ret =3D readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STAT= US, - val, val =3D=3D 0, 200, 2000); - if (ret) - goto disable_power; - -disable_power: - iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); - iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); - - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); - - reset_control_bulk_reset(clk_rst_tbl_size, core->resets); - - return 0; -} - -static int iris_vpu35_power_on_controller(struct iris_core *core) -{ - int ret; - - ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= CTRL_POWER_DOMAIN]); - if (ret) - return ret; - - ret =3D iris_prepare_enable_clock(core, IRIS_AXI1_CLK); - if (ret) - goto err_disable_power; - - ret =3D iris_prepare_enable_clock(core, IRIS_CTRL_FREERUN_CLK); - if (ret) - goto err_disable_axi1_clk; - - ret =3D iris_prepare_enable_clock(core, IRIS_CTRL_CLK); - if (ret) - goto err_disable_ctrl_free_clk; - - return 0; - -err_disable_ctrl_free_clk: - iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); -err_disable_axi1_clk: - iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); -err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); - - return ret; -} - -static void iris_vpu35_program_bootup_registers(struct iris_core *core) -{ - writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0); -} - -static u64 iris_vpu3x_calculate_frequency(struct iris_inst *inst, size_t d= ata_size) -{ - struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; - struct v4l2_format *inp_f =3D inst->fmt_src; - u32 height, width, mbs_per_second, mbpf; - u64 fw_cycles, fw_vpp_cycles; - u64 vsp_cycles, vpp_cycles; - u32 fps =3D DEFAULT_FPS; - - width =3D max(inp_f->fmt.pix_mp.width, inst->crop.width); - height =3D max(inp_f->fmt.pix_mp.height, inst->crop.height); - - mbpf =3D NUM_MBS_PER_FRAME(height, width); - mbs_per_second =3D mbpf * fps; - - fw_cycles =3D fps * caps->mb_cycles_fw; - fw_vpp_cycles =3D fps * caps->mb_cycles_fw_vpp; - - vpp_cycles =3D mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->= fw_caps[PIPE].value); - /* 21 / 20 is minimum overhead factor */ - vpp_cycles +=3D max(div_u64(vpp_cycles, 20), fw_vpp_cycles); - - /* 1.059 is multi-pipe overhead */ - if (inst->fw_caps[PIPE].value > 1) - vpp_cycles +=3D div_u64(vpp_cycles * 59, 1000); - - vsp_cycles =3D fps * data_size * 8; - vsp_cycles =3D div_u64(vsp_cycles, 2); - /* VSP FW overhead 1.05 */ - vsp_cycles =3D div_u64(vsp_cycles * 21, 20); - - if (inst->fw_caps[STAGE].value =3D=3D STAGE_1) - vsp_cycles =3D vsp_cycles * 3; - - return max3(vpp_cycles, vsp_cycles, fw_cycles); -} - const struct vpu_ops iris_vpu3_ops =3D { .power_off_hw =3D iris_vpu3_power_off_hardware, .power_on_hw =3D iris_vpu_power_on_hw, .power_off_controller =3D iris_vpu_power_off_controller, .power_on_controller =3D iris_vpu_power_on_controller, - .calc_freq =3D iris_vpu3x_calculate_frequency, + .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, }; =20 const struct vpu_ops iris_vpu33_ops =3D { @@ -418,14 +273,14 @@ const struct vpu_ops iris_vpu33_ops =3D { .power_on_hw =3D iris_vpu_power_on_hw, .power_off_controller =3D iris_vpu33_power_off_controller, .power_on_controller =3D iris_vpu_power_on_controller, - .calc_freq =3D iris_vpu3x_calculate_frequency, + .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, }; =20 const struct vpu_ops iris_vpu35_ops =3D { .power_off_hw =3D iris_vpu35_power_off_hw, .power_on_hw =3D iris_vpu35_power_on_hw, - .power_off_controller =3D iris_vpu35_power_off_controller, - .power_on_controller =3D iris_vpu35_power_on_controller, - .program_bootup_registers =3D iris_vpu35_program_bootup_registers, - .calc_freq =3D iris_vpu3x_calculate_frequency, + .power_off_controller =3D iris_vpu35_vpu4x_power_off_controller, + .power_on_controller =3D iris_vpu35_vpu4x_power_on_controller, + .program_bootup_registers =3D iris_vpu35_vpu4x_program_bootup_registers, + .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 50242fc6b4653a7d74ff64500f40eb8a859a6548..548e5f1727fdb7543f76a1871f1= 7257fa2360733 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -8,9 +8,12 @@ #include =20 #include "iris_core.h" +#include "iris_instance.h" #include "iris_vpu_common.h" #include "iris_vpu_register_defines.h" =20 +#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL (AON_BASE_OFFS + 0x2C) +#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS (AON_BASE_OFFS + 0x30) =20 #define CTRL_INIT (CPU_CS_BASE_OFFS + 0x48) #define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C) @@ -305,6 +308,144 @@ int iris_vpu_power_on_hw(struct iris_core *core) return ret; } =20 +int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core) +{ + u32 clk_rst_tbl_size =3D core->iris_platform_data->clk_rst_tbl_size; + bool handshake_done, handshake_busy; + u32 count =3D 0, val =3D 0; + int ret; + + writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CP= U_CS_X2RPMH); + + writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CON= TROL); + + ret =3D readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STAT= US, + val, val & BIT(0), 200, 2000); + if (ret) + goto disable_power; + + writel(0, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL); + + /* Retry up to 1000 times as recommended by hardware documentation */ + do { + /* set MNoC to low power */ + writel(REQ_POWER_DOWN_PREP, core->reg_base + + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL); + usleep_range(10, 20); + val =3D readl(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS); + + handshake_done =3D val & NOC_LPI_STATUS_DONE; + handshake_busy =3D val & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE); + + if (handshake_done || !handshake_busy) + break; + + writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL); + usleep_range(10, 20); + + } while (++count < 1000); + + if (!handshake_done && handshake_busy) + dev_err(core->dev, "LPI handshake timeout\n"); + + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC= _LPI_STATUS, + val, val & BIT(0), 200, 2000); + if (ret) + goto disable_power; + + writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL); + + writel(0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL); + + readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS, + val, val =3D=3D 0, 200, 2000); + +disable_power: + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); + iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); + + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + + reset_control_bulk_reset(clk_rst_tbl_size, core->resets); + + return 0; +} + +int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) +{ + int ret; + + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= CTRL_POWER_DOMAIN]); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_AXI1_CLK); + if (ret) + goto err_disable_power; + + ret =3D iris_prepare_enable_clock(core, IRIS_CTRL_FREERUN_CLK); + if (ret) + goto err_disable_axi1_clk; + + ret =3D iris_prepare_enable_clock(core, IRIS_CTRL_CLK); + if (ret) + goto err_disable_ctrl_free_clk; + + return 0; + +err_disable_ctrl_free_clk: + iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); +err_disable_axi1_clk: + iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); +err_disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + + return ret; +} + +void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core) +{ + writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0); +} + +u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t da= ta_size) +{ + struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; + struct v4l2_format *inp_f =3D inst->fmt_src; + u32 height, width, mbs_per_second, mbpf; + u64 fw_cycles, fw_vpp_cycles; + u64 vsp_cycles, vpp_cycles; + u32 fps =3D DEFAULT_FPS; + + width =3D max(inp_f->fmt.pix_mp.width, inst->crop.width); + height =3D max(inp_f->fmt.pix_mp.height, inst->crop.height); + + mbpf =3D NUM_MBS_PER_FRAME(height, width); + mbs_per_second =3D mbpf * fps; + + fw_cycles =3D fps * caps->mb_cycles_fw; + fw_vpp_cycles =3D fps * caps->mb_cycles_fw_vpp; + + vpp_cycles =3D mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->= fw_caps[PIPE].value); + /* 21 / 20 is minimum overhead factor */ + vpp_cycles +=3D max(div_u64(vpp_cycles, 20), fw_vpp_cycles); + + /* 1.059 is multi-pipe overhead */ + if (inst->fw_caps[PIPE].value > 1) + vpp_cycles +=3D div_u64(vpp_cycles * 59, 1000); + + vsp_cycles =3D fps * data_size * 8; + vsp_cycles =3D div_u64(vsp_cycles, 2); + /* VSP FW overhead 1.05 */ + vsp_cycles =3D div_u64(vsp_cycles * 21, 20); + + if (inst->fw_caps[STAGE].value =3D=3D STAGE_1) + vsp_cycles =3D vsp_cycles * 3; + + return max3(vpp_cycles, vsp_cycles, fw_cycles); +} + int iris_vpu_power_on(struct iris_core *core) { u32 freq; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index d636e287457adf0c44540af5c85cfa69decbca8b..7cf4304604cca590544a938c7e8= 11c202cea3d93 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -33,5 +33,9 @@ int iris_vpu_power_on(struct iris_core *core); int iris_vpu_power_off_controller(struct iris_core *core); void iris_vpu_power_off_hw(struct iris_core *core); void iris_vpu_power_off(struct iris_core *core); +int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core); +int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core); +void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core); +u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t da= ta_size); =20 #endif --=20 2.34.1 From nobody Mon Dec 15 00:33:12 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EC243246FF for ; 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Hook up vpu4 op with vpu4 specific implemtation or resue from earlier generation wherever feasible, like clock calculation in this case. Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/Makefile | 1 + .../platform/qcom/iris/iris_platform_common.h | 7 + drivers/media/platform/qcom/iris/iris_vpu4x.c | 369 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + 4 files changed, 378 insertions(+) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index fad3be044e5fe783db697a592b4f09de4d42d0d2..2abbd3aeb4af07e52bf372a4b2f= 352463529c92c 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -22,6 +22,7 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_venc.o \ iris_vpu2.o \ iris_vpu3x.o \ + iris_vpu4x.o \ iris_vpu_buffer.o \ iris_vpu_common.o \ =20 diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 29900c3ea9b9ebbab614c804a249b08ba6001494..bc78cf7c77718666ddac86d6913= b4d380991018f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -57,6 +57,10 @@ enum platform_clk_type { IRIS_AXI1_CLK, IRIS_CTRL_FREERUN_CLK, IRIS_HW_FREERUN_CLK, + IRIS_BSE_HW_CLK, + IRIS_VPP0_HW_CLK, + IRIS_VPP1_HW_CLK, + IRIS_APV_HW_CLK, }; =20 struct platform_clk_data { @@ -191,6 +195,9 @@ struct icc_vote_data { enum platform_pm_domain_type { IRIS_CTRL_POWER_DOMAIN, IRIS_HW_POWER_DOMAIN, + IRIS_VPP0_HW_POWER_DOMAIN, + IRIS_VPP1_HW_POWER_DOMAIN, + IRIS_APV_HW_POWER_DOMAIN, }; =20 struct iris_platform_data { diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/= platform/qcom/iris/iris_vpu4x.c new file mode 100644 index 0000000000000000000000000000000000000000..a8db02ce5c5ec583c4027166b34= ce51d3d683b4e --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +#include "iris_instance.h" +#include "iris_vpu_common.h" +#include "iris_vpu_register_defines.h" + +#define AON_WRAPPER_MVP_NOC_RESET_SYNCRST (AON_MVP_NOC_RESET + 0x08) +#define CPU_CS_APV_BRIDGE_SYNC_RESET (CPU_BASE_OFFS + 0x174) +#define MVP_NOC_RESET_REQ_MASK 0x70103 +#define VPU_IDLE_BITS 0x7103 +#define WRAPPER_EFUSE_MONITOR (WRAPPER_BASE_OFFS + 0x08) + +#define APV_CLK_HALT BIT(1) +#define CORE_CLK_HALT BIT(0) +#define CORE_PWR_ON BIT(1) +#define DISABLE_VIDEO_APV_BIT BIT(27) +#define DISABLE_VIDEO_VPP1_BIT BIT(28) +#define DISABLE_VIDEO_VPP0_BIT BIT(29) + +static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mod= e, u32 efuse_value) +{ + int ret; + + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], hw_mode); + if (ret) + return ret; + + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs + [IRIS_VPP0_HW_POWER_DOMAIN], hw_mode); + if (ret) + goto restore_hw_domain_mode; + } + + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs + [IRIS_VPP1_HW_POWER_DOMAIN], hw_mode); + if (ret) + goto restore_vpp0_domain_mode; + } + + if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) { + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs + [IRIS_APV_HW_POWER_DOMAIN], hw_mode); + if (ret) + goto restore_vpp1_domain_mode; + } + + return 0; + +restore_vpp1_domain_mode: + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP1_HW_POWER_D= OMAIN], + !hw_mode); +restore_vpp0_domain_mode: + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_D= OMAIN], + !hw_mode); +restore_hw_domain_mode: + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]= , !hw_mode); + + return ret; +} + +static int iris_vpu4x_power_on_apv(struct iris_core *core) +{ + int ret; + + ret =3D iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_APV_HW_CLK); + if (ret) + goto disable_apv_hw_power_domain; + + return 0; + +disable_apv_hw_power_domain: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_= POWER_DOMAIN]); + + return ret; +} + +static void iris_vpu4x_power_off_apv(struct iris_core *core) +{ + bool handshake_done, handshake_busy; + u32 value, count =3D 0; + int ret; + + value =3D readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + if (value & APV_CLK_HALT) + writel(0x0, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + do { + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CON= TROL); + usleep_range(10, 20); + value =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); + + handshake_done =3D value & NOC_LPI_STATUS_DONE; + handshake_busy =3D value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE); + + if (handshake_done || !handshake_busy) + break; + + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + usleep_range(10, 20); + + } while (++count < 1000); + + if (!handshake_done && handshake_busy) + dev_err(core->dev, "LPI handshake timeout\n"); + + writel(0x080200, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, + value, value & 0x080200, 200, 2000); + if (ret) + goto disable_clocks_and_power; + + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_SYNCRST); + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, + value, value =3D=3D 0x0, 200, 2000); + if (ret) + goto disable_clocks_and_power; + + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_bas= e + + CPU_CS_APV_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_APV_BRIDGE_S= YNC_RESET); + writel(0x0, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET); + +disable_clocks_and_power: + iris_disable_unprepare_clock(core, IRIS_APV_HW_CLK); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_= POWER_DOMAIN]); +} + +static void iris_vpu4x_ahb_sync_reset_apv(struct iris_core *core) +{ + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_bas= e + + CPU_CS_APV_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_APV_BRIDGE_S= YNC_RESET); + writel(0x0, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET); +} + +static void iris_vpu4x_ahb_sync_reset_hardware(struct iris_core *core) +{ + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_bas= e + + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_S= YNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); +} + +static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 e= fuse_value) +{ + int ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_AXI_CLK); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); + if (ret) + goto disable_axi_clock; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); + if (ret) + goto disable_hw_free_run_clock; + + ret =3D iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); + if (ret) + goto disable_hw_clock; + + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { + ret =3D iris_prepare_enable_clock(core, IRIS_VPP0_HW_CLK); + if (ret) + goto disable_bse_hw_clock; + } + + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { + ret =3D iris_prepare_enable_clock(core, IRIS_VPP1_HW_CLK); + if (ret) + goto disable_vpp0_hw_clock; + } + + return 0; + +disable_vpp0_hw_clock: + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) + iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK); +disable_bse_hw_clock: + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); +disable_hw_clock: + iris_disable_unprepare_clock(core, IRIS_HW_CLK); +disable_hw_free_run_clock: + iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); +disable_axi_clock: + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + + return ret; +} + +static void iris_vpu4x_disable_hardware_clocks(struct iris_core *core, u32= efuse_value) +{ + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) + iris_disable_unprepare_clock(core, IRIS_VPP1_HW_CLK); + + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) + iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK); + + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); +} + +static int iris_vpu4x_power_on_hardware(struct iris_core *core) +{ + u32 efuse_value =3D readl(core->reg_base + WRAPPER_EFUSE_MONITOR); + int ret; + + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); + if (ret) + return ret; + + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP0_HW_POWER_DOMAIN]); + if (ret) + goto disable_hw_power_domain; + } + + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP1_HW_POWER_DOMAIN]); + if (ret) + goto disable_vpp0_power_domain; + } + + ret =3D iris_vpu4x_enable_hardware_clocks(core, efuse_value); + if (ret) + goto disable_vpp1_power_domain; + + if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) { + ret =3D iris_vpu4x_power_on_apv(core); + if (ret) + goto disable_hw_clocks; + + iris_vpu4x_ahb_sync_reset_apv(core); + } + + iris_vpu4x_ahb_sync_reset_hardware(core); + + ret =3D iris_vpu4x_genpd_set_hwmode(core, true, efuse_value); + if (ret) + goto disable_apv_power_domain; + + return 0; + +disable_apv_power_domain: + if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) + iris_vpu4x_power_off_apv(core); +disable_hw_clocks: + iris_vpu4x_disable_hardware_clocks(core, efuse_value); +disable_vpp1_power_domain: + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP1_HW_POWER_DOMAIN]); +disable_vpp0_power_domain: + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP0_HW_POWER_DOMAIN]); +disable_hw_power_domain: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + + return ret; +} + +static void iris_vpu4x_power_off_hardware(struct iris_core *core) +{ + u32 efuse_value =3D readl(core->reg_base + WRAPPER_EFUSE_MONITOR); + bool handshake_done, handshake_busy; + u32 value, count =3D 0; + int ret; + + iris_vpu4x_genpd_set_hwmode(core, false, efuse_value); + + if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) + iris_vpu4x_power_off_apv(core); + + value =3D readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); + + if (!(value & CORE_PWR_ON)) + goto disable_clocks_and_power; + + value =3D readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + if (value & CORE_CLK_HALT) + writel(0x0, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN, value, + value & VPU_IDLE_BITS, 2000, 20000); + + do { + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CON= TROL); + usleep_range(10, 20); + value =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); + + handshake_done =3D value & NOC_LPI_STATUS_DONE; + handshake_busy =3D value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE); + + if (handshake_done || !handshake_busy) + break; + + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + usleep_range(10, 20); + + } while (++count < 1000); + + if (!handshake_done && handshake_busy) + dev_err(core->dev, "LPI handshake timeout\n"); + + writel(MVP_NOC_RESET_REQ_MASK, core->reg_base + AON_WRAPPER_MVP_NOC_RESET= _REQ); + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, + value, value & MVP_NOC_RESET_REQ_MASK, 200, 2000); + if (ret) + goto disable_clocks_and_power; + + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_SYNCRST); + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, + value, value =3D=3D 0x0, 200, 2000); + if (ret) + goto disable_clocks_and_power; + + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_bas= e + + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_S= YNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + +disable_clocks_and_power: + iris_vpu4x_disable_hardware_clocks(core, efuse_value); + + if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP1_HW_POWER_DOMAIN]); + + if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs + [IRIS_VPP0_HW_POWER_DOMAIN]); + + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); +} + +const struct vpu_ops iris_vpu4x_ops =3D { + .power_off_hw =3D iris_vpu4x_power_off_hardware, + .power_on_hw =3D iris_vpu4x_power_on_hardware, + .power_off_controller =3D iris_vpu35_vpu4x_power_off_controller, + .power_on_controller =3D iris_vpu35_vpu4x_power_on_controller, + .program_bootup_registers =3D iris_vpu35_vpu4x_program_bootup_registers, + .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, +}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 7cf4304604cca590544a938c7e811c202cea3d93..f6dffc613b822341fb21e12de6b= 1395202f62cde 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -12,6 +12,7 @@ extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; +extern const struct vpu_ops iris_vpu4x_ops; =20 struct vpu_ops { void (*power_off_hw)(struct iris_core *core); --=20 2.34.1