From nobody Wed Dec 17 00:23:34 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4553E2D1905 for ; Thu, 11 Dec 2025 03:05:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765422331; cv=none; b=hx4cU8wGQZNalkEO5RqQs1tJZYvwYQeMLVGOxJtge4eyKijTkj3lFoqGFaTzPJXX453D2zkh0sqxkZDJTHpcnF4l8P9kSgm3dEXwvkm7rIv1FMoPtkYGTFksjxBcsTs7nBdlJy4gU1LwX5rOvHWuOrGlFSPDqg5mgtS5y0y/4FA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765422331; c=relaxed/simple; bh=JvAMLHfXjJOTx0dCOL2JhodZ67/6o6sMlk2mAe+sfJc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lNBMSySyTMLOM5fgHCQ6hVYEvhKTGWvVf5M4IwDn7f6RsvryVwtf++IY5cIzvcTJuk3DSGnx2b+8kFS4vAO4eiojV+N8SiUR2QnCXboIC8soTFfLya25JrDABXrTpRO5A3ogF+q8mtuvVPh/jkFlgklgvkuW/18bRugfU0AJB14= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=IUdTSPLZ; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=HsRi136g; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="IUdTSPLZ"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="HsRi136g" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BALP6PH3544196 for ; Thu, 11 Dec 2025 03:05:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= U+eAwpJifGXoos/x16Zz1HAoa3GC+zmnPW0PBAoA+Wc=; b=IUdTSPLZS5YGhZCp 9o1KYmRGnXbwpcxYQaaxZbZAtc8LjNb8HCikaw+n7LS8XRxu+Zo4n1fIZ66Up3c+ MfHPxVXtwNtX7f7RZ6vxmwyhcGp0gZ1sAmRrQaqc669nvmj75ArlJBUrGDNbiPxf UKbt2/zMp5JcH+VCrD7nBSpUudhYCBYCNqJChjg6XD7DS+eU9zp/8dUAj2PWEZPF whEPSmoMMY19mKT1+2hL6GOpP5PpdBGxgYip2QveU/dCQCLgbu6RzELETPJA6qGn kTyXRQT5TuALpcMyGJknir77znA+VCy1FZjPvlhTltocVdZr4NfrcpgClGkarNhB CJDdDQ== Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ay1xp3x9e-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 11 Dec 2025 03:05:25 +0000 (GMT) Received: by mail-pg1-f197.google.com with SMTP id 41be03b00d2f7-b62da7602a0so536631a12.2 for ; Wed, 10 Dec 2025 19:05:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1765422325; x=1766027125; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=U+eAwpJifGXoos/x16Zz1HAoa3GC+zmnPW0PBAoA+Wc=; b=HsRi136g5H2vTpdJCTdh22GwRSPBDO/Cm75N5cw7kGncnRza50Ic7HlVoClT30hcTd 8hQNuy4h92WIi0yY3OcMdzXKvzGrCwR4Hii7ee5ZgVsrvo7Dita3P6f7ME2Ws82R+Te3 zfZqG9PwuSzjd0R6P2p68WQIRt2jYS5yYiMEpm087gjG0DUWrrD/+RN/4fIm9oWTY8of 72z2A0SuzUSTAuAeNtDUoxgV+/ColTLq4tsimXtN4QawQtu/VR521XYvdF5VbSmhlFLf 1tjKGJukTZCCOSENRvsnvjVcX9gy1HuexGNV2HGjwTZ8K1dkw4BdAWdKGh60Mk8NnDTu Jwjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765422325; x=1766027125; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=U+eAwpJifGXoos/x16Zz1HAoa3GC+zmnPW0PBAoA+Wc=; b=oDqnh/yaXTS9MSlwHXx9a6SDRdtgRVCz02pJsN8F01fIuDbx7/tq/WgAoYDFVFQesH ZAFHoO5S6Yw8R8e/I13t5XPTurfP1WXRSMeaB/eLLNWT4hG5uJJ0bUag66SPf1TAdOCr +g1brcVY5LYAMJMrVEg+Wu5JV1qe749NEz/QyIsifACINXGCKAb6eUajZG/MYBHqDDFx kw4ISR0ZbyYRJqs/hEUAP7t5Dyz+elwe50k4GMfr9hq8g9SVFElzK4Tc0c/rZi+EO0nP 53Jq9w6it2mWWqNSq7/0c5ER+wFeNuorp4SI+a5+K8InLSso1v84WagT/SzFkRtqVDpx iCBg== X-Forwarded-Encrypted: i=1; AJvYcCVPmI5KgY39o7f8y9X5ZBbNNleljQN5oQiP3jdYcytfLkUsDayO6lBVA6fswr8tTMUHaqwdI+yhirw93Ak=@vger.kernel.org X-Gm-Message-State: AOJu0YxHgRs/A5y8Z/rg7ibDpp187znVrz14QOWRjPGPCwpd8Wy+cQc3 dhoQD/NXXb8GDFMeoGJjVAHS0rWJ/9gUAqRDsKdIw5nqPiI1Kkfbe7M3Qmos6BtXSZqHMHBNLBw y5ryFJLWBsNbKaj+PQUrSFaowEoRDfa6GQrTG3w+c0JYmplnCOF5nUhxNhVeGyhlhYos= X-Gm-Gg: AY/fxX7AmTlBAQKn18j326fm/4HjQr1Xj5KU0UEf7ItjP/GHyYAng5REHbWjdp2P59n bjR2qjiclWfYxBbFG5RYjvjhgh/wNAlpK5zU6ZUozzRnrT9ZI3iCsoZU5967ovc4zqmRrN9m7NJ PeS/VBZWQzPZF92SQmweAC7R9orfE2x+sHkNGj+xfNugFkD/Ry8IFJ0jO2SKduz109w74Zmso09 pE0SWtFq97v5QCyBLIoBkEhEJwpcEcdRDrB/dWQ2PFg37LNPNl80G214E321dgB1nnaYodAi2pR edeKstR6ZfFbdbCOfaGtDqE/yVzTAHLJXrUMewI2mzZy+2opY4BV5p3vkhRNMRoZguKsXG8/r05 ciikRyYEvOsRMIuffmSDCWX2MUIDWKmQrWhL1MHd9cAfR9zq3UI8vTD7xEcax X-Received: by 2002:a05:7022:984:b0:119:e56b:91f6 with SMTP id a92af1059eb24-11f296b3ed0mr3539441c88.39.1765422323712; Wed, 10 Dec 2025 19:05:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IGnMsisXBzYTBmYe3aJBT3sjh/+4XQ3e979CCzXDwJSRZHRr/QXlTY0UwLMPAzo1euZ69LTBw== X-Received: by 2002:a05:7022:984:b0:119:e56b:91f6 with SMTP id a92af1059eb24-11f296b3ed0mr3539393c88.39.1765422322878; Wed, 10 Dec 2025 19:05:22 -0800 (PST) Received: from hu-jingyw-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f2e2ff624sm3935642c88.12.2025.12.10.19.05.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 19:05:22 -0800 (PST) From: Jingyi Wang Date: Wed, 10 Dec 2025 19:05:04 -0800 Subject: [PATCH v3 3/5] arm64: dts: qcom: Introduce Kaanapali SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251210-knp-dts-v3-3-8dcd52f055c2@oss.qualcomm.com> References: <20251210-knp-dts-v3-0-8dcd52f055c2@oss.qualcomm.com> In-Reply-To: <20251210-knp-dts-v3-0-8dcd52f055c2@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Jingyi Wang , Tengfei Fan X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765422317; l=43566; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=JvAMLHfXjJOTx0dCOL2JhodZ67/6o6sMlk2mAe+sfJc=; b=vp++MKfokt4QhgPJb9x8A1Z86OeKhqywoXBSWLLhZfIbwUkTGvBulmsPAJzV6xGZnXhwZ63MO z7o1HZuBqJYCWF6WcnZ+v5+BxBLumpb4h8e67Y/uYLtmT3usCTTDuCv X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjExMDAxNyBTYWx0ZWRfX6gfqesIGr+7D 1+sY1G15wPkUal5ehyFXi31ggKK+JA4MYJTAXz3s9dHCXu+/nGm3xz2c2JD8dB8dEiPR/AD6qnr YXd3ZQAJneZglq8pB3ksFqYRmmKVfRNERD3LQDtsv34IKTNeCvJtJ3Cl49KQ+lJ1i0yx7fPKgxs 8H3BkTsrbcX6h/r9iLWL5ogj6SsUzP1BssK+nrreb4ud0o6xlJl3chD6bNklbo328vJMk+n8/PY uiVKqEuvmljCB8lFf34iMjvf9j/XoDvw4SizoeiI0KP0pQQC0//6un7YF99JQiY5l/UQRHgyLnz gvJZWooXSGudSY4s4bjNhPydtBHJRb598YDIOiN/KBFdm+N5f5HUwVjC8L8lYL4PNDNDpChOhX3 oiydUqOBybPkQUScIkJZhF9EXdcauQ== X-Proofpoint-ORIG-GUID: XUEZC7DmZY4qNnemY73v5yF_VyywAETA X-Proofpoint-GUID: XUEZC7DmZY4qNnemY73v5yF_VyywAETA X-Authority-Analysis: v=2.4 cv=A/Zh/qWG c=1 sm=1 tr=0 ts=693a34f5 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=P7TurCwWt9EVGe50nVwA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-10_03,2025-12-09_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 spamscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512110017 Kaanapali is Snapdragon SoC from Qualcomm. Features added in this patch: - CPUs with PSCI idle states and cpufreq - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - GCC and RPMHCC - TLMM - Interconnect with CPU BWMONs - QuP with UART - SMMU - RPMhPD - UFS with Inline Crypto Engine - LLCC - Watchdog - SD Card - PCIe Written with help from Raviteja Laggyshetty (added interconnect nodes), Taniya Das (added Clock Controllers and cpufreq), Jishnu Prakash (added RPMhPD), Nitin Rawat (added UFS), Gaurav Kashyap (added ICE), Manish Pandey (added SD Card) and Qiang Yu (added PCIe). Co-developed-by: Tengfei Fan Signed-off-by: Tengfei Fan Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1606 +++++++++++++++++++++++++++= ++++ 1 file changed, 1606 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi new file mode 100644 index 000000000000..f104ea16ff45 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -0,0 +1,1606 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "kaanapali-ipcc.h" + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 0>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 0>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 0>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 0>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd4>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 0>; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd5>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 0>; + }; + + cpu6: cpu@10000 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x10000>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_1>; + power-domains =3D <&cpu_pd6>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 1>; + + l2_1: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + cpu7: cpu@10100 { + device_type =3D "cpu"; + compatible =3D "qcom,oryon"; + reg =3D <0x0 0x10100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_1>; + power-domains =3D <&cpu_pd7>; + power-domain-names =3D "psci"; + clocks =3D <&pdp_scmi_perf 1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu6>; + }; + + core1 { + cpu =3D <&cpu7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cluster0_c4: cpu-sleep-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "retention"; + arm,psci-suspend-param =3D <0x00000004>; + entry-latency-us =3D <93>; + exit-latency-us =3D <129>; + min-residency-us =3D <560>; + }; + + cluster1_c4: cpu-sleep-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "retention"; + arm,psci-suspend-param =3D <0x00000004>; + entry-latency-us =3D <172>; + exit-latency-us =3D <130>; + min-residency-us =3D <686>; + }; + }; + + domain-idle-states { + cluster_cl5: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x01000054>; + entry-latency-us =3D <2150>; + exit-latency-us =3D <1983>; + min-residency-us =3D <9144>; + }; + + domain_ss3: domain-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x0200c354>; + entry-latency-us =3D <2800>; + exit-latency-us =3D <4400>; + min-residency-us =3D <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-kaanapali", "qcom,scm"; + qcom,dload-mode =3D <&tcsr 0x19000>; + interconnects =3D <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + }; + + scmi: scmi { + compatible =3D "arm,scmi"; + mboxes =3D <&pdp0_mbox 0>, <&pdp0_mbox 1>; + mbox-names =3D "tx", "rx"; + shmem =3D <&pdp_tx>, <&pdp_rx>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + pdp_scmi_perf: protocol@13 { + reg =3D <0x13>; + #clock-cells =3D <1>; + }; + }; + }; + + clk_virt: interconnect-0 { + compatible =3D "qcom,kaanapali-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible =3D "qcom,kaanapali-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + memory@a0000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster0_c4>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster1_c4>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cluster1_c4>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_cl5>; + power-domains =3D <&system_pd>; + }; + + system_pd: power-domain-system { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&domain_ss3>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + pdp_mem: pdp-region@81300000 { + reg =3D <0x0 0x81300000 0x0 0x100000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@81c60000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + smem_mem: smem@81d00000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x81d00000 0x0 0x200000>; + hwlocks =3D <&tcsr_mutex 3>; + no-map; + }; + + pdp_ns_shared_mem: pdp-ns-shared-region@81f00000 { + reg =3D <0x0 0x81f00000 0x0 0x100000>; + no-map; + }; + + dsm_partition_1_mem: dsm-partition-1@84a00000 { + reg =3D <0x0 0x84a00000 0x0 0x5500000>; + no-map; + }; + + dsm_partition_2_mem: dsm-partition-2@89f00000 { + reg =3D <0x0 0x89f00000 0x0 0xa80000>; + no-map; + }; + + mpss_mem: mpss@8aa00000 { + reg =3D <0x0 0x8aa00000 0x0 0xeb00000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@99500000 { + reg =3D <0x0 0x99500000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@99580000 { + reg =3D <0x0 0x99580000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@99590000 { + reg =3D <0x0 0x99590000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@9959a000 { + reg =3D <0x0 0x9959a000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera@99600000 { + reg =3D <0x0 0x99600000 0x0 0x800000>; + no-map; + }; + + camera_2_mem: camera-2@99e00000 { + reg =3D <0x0 0x99e00000 0x0 0x800000>; + no-map; + }; + + video_mem: video@9a600000 { + reg =3D <0x0 0x9a600000 0x0 0x800000>; + no-map; + }; + + cvp_mem: cvp@9ae00000 { + reg =3D <0x0 0x9ae00000 0x0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp@9b500000 { + reg =3D <0x0 0x9b500000 0x0 0x1900000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb@9ce00000 { + reg =3D <0x0 0x9ce00000 0x0 0x80000>; + no-map; + }; + + soccp_mem: soccp@a03d0000 { + reg =3D <0x0 0xa03d0000 0x0 0x500000>; + no-map; + }; + + soccp_dtb_mem: soccp-dtb@a08d0000 { + reg =3D <0x0 0xa08d0000 0x0 0x40000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb@a1380000 { + reg =3D <0x0 0xa1380000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi@a1400000 { + reg =3D <0x0 0xa1400000 0x0 0x4c00000>; + no-map; + }; + + rmtfs_mem: rmtfs@d7c00000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0 0xd7c00000 0 0x400000>; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D ; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0 0 0 0 0x10 0>; + ranges =3D <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,kaanapali-gcc"; + reg =3D <0x0 0x00100000 0x0 0x1f4200>; + + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>, + <&pcie0_phy>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <0>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + qupv3_1: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AXI_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + iommus =3D <&apps_smmu 0xa3 0x0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + uart7: serial@a9c000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x00a9c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart7_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + ipcc: mailbox@1106000 { + compatible =3D "qcom,kaanapali-ipcc", "qcom,ipcc"; + reg =3D <0x0 0x01106000 0x0 0x1000>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + + #mbox-cells =3D <2>; + }; + + cnoc_main: interconnect@1500000 { + compatible =3D "qcom,kaanapali-cnoc-main"; + reg =3D <0x0 0x01500000 0x0 0x1a080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + config_noc: interconnect@1600000 { + compatible =3D "qcom,kaanapali-cnoc-cfg"; + reg =3D <0x0 0x01600000 0x0 0x6200>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,kaanapali-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x1f080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + pcie_noc: interconnect@16c0000 { + compatible =3D "qcom,kaanapali-pcie-anoc"; + reg =3D <0x0 0x016c0000 0x0 0x11400>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + }; + + aggre_noc: interconnect@16e0000 { + compatible =3D "qcom,kaanapali-aggre-noc"; + reg =3D <0x0 0x016e0000 0x0 0x42400>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; + + mmss_noc: interconnect@1780000 { + compatible =3D "qcom,kaanapali-mmss-noc"; + reg =3D <0x0 0x01780000 0x0 0x5b800>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + pcie0: pcie@1c00000 { + device_type =3D "pci"; + compatible =3D "qcom,kaanapali-pcie", "qcom,pcie-sm8550"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, + <0x02000000 0 0x40300000 0 0x40300000 0 0x23d00000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr", + "cnoc_sf_axi"; + + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + interconnects =3D <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + power-domains =3D <&gcc GCC_PCIE_0_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + + operating-points-v2 =3D <&pcie0_opp_table>; + + iommu-map =3D <0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 0x7>; + #interrupt-cells =3D <1>; + + msi-map =3D <0x0 &gic_its 0x1400 0x1>, + <0x100 &gic_its 0x1401 0x1>; + msi-map-mask =3D <0xff00>; + max-link-speed =3D <3>; + linux,pci-domain =3D <0>; + num-lanes =3D <2>; + bus-range =3D <0 0xff>; + + dma-coherent; + + status =3D "disabled"; + + pcie0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <984500 1>; + }; + + /* GEN 3 x2 */ + opp-16000000 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <1969000 1>; + }; + }; + + pcie_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + phys =3D <&pcie0_phy>; + }; + }; + + pcie0_phy: phy@1c06000 { + compatible =3D "qcom,kaanapali-qmp-gen3x2-pcie-phy"; + reg =3D <0 0x01c06000 0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>, + <&gcc GCC_PCIE_0_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr"; + + power-domains =3D <&gcc GCC_PCIE_0_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie0_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + ufs_mem_phy: phy@1d80000 { + compatible =3D "qcom,kaanapali-qmp-ufs-phy", "qcom,sm8750-qmp-ufs-phy"; + reg =3D <0x0 0x01d80000 0x0 0x2000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; + + clock-names =3D "ref", + "ref_aux", + "qref"; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + + power-domains =3D <&gcc GCC_UFS_MEM_PHY_GDSC>; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible =3D "qcom,kaanapali-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg =3D <0x0 0x01d84000 0x0 0x3000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + operating-points-v2 =3D <&ufs_opp_table>; + + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + interconnects =3D <&aggre_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "ufs-ddr", + "cpu-ufs"; + + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0x60 0x0>; + dma-coherent; + + lanes-per-direction =3D <2>; + qcom,ice =3D <&ice>; + + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + + #reset-cells =3D <1>; + + status =3D "disabled"; + + ufs_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-403000000 { + opp-hz =3D /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + ice: crypto@1d88000 { + compatible =3D "qcom,kaanapali-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg =3D <0x0 0x01d88000 0x0 0x18000>; + + clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible =3D "qcom,kaanapali-tcsr", "syscon"; + reg =3D <0x0 0x01fc0000 0x0 0x30000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible =3D "qcom,kaanapali-lpass-lpiaon-noc"; + reg =3D <0x0 0x07400000 0x0 0x19080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible =3D "qcom,kaanapali-lpass-lpicx-noc"; + reg =3D <0x0 0x07420000 0x0 0x44080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + lpass_ag_noc: interconnect@7f40000 { + compatible =3D "qcom,kaanapali-lpass-ag-noc"; + reg =3D <0x0 0x07f40000 0x0 0xe080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + sdhc_2: mmc@8804000 { + compatible =3D "qcom,kaanapali-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0 0x08804000 0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "core", "xo"; + + interconnects =3D <&aggre_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&sdhc2_opp_table>; + + qcom,dll-config =3D <0x0007442c>; + qcom,ddr-config =3D <0x80040868>; + + iommus =3D <&apps_smmu 0x540 0x0>; + dma-coherent; + + resets =3D <&gcc GCC_SDCC2_BCR>; + status =3D "disabled"; + + sdhc2_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + opp-peak-kBps =3D <160000 100000>; + opp-avg-kBps =3D <50000 0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + opp-peak-kBps =3D <200000 120000>; + opp-avg-kBps =3D <104000 0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,kaanapali-pdc", "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x10000>, + <0x0 0x179600f0 0x0 0xf4>; + + qcom,pdc-ranges =3D <0 745 38>, + <40 785 11>, + <51 527 4>, + <58 534 2>, + <61 537 20>, + <84 559 14>, + <98 609 32>, + <130 717 12>, + <142 251 5>, + <147 796 16>, + <163 783 2>, + <165 531 2>, + <167 536 1>, + <168 557 2>, + <170 415 1>, + <171 438 1>, + <172 579 1>, + <173 703 1>, + <174 708 1>, + <175 714 1>, + <176 68 1>, + <177 86 1>, + <178 96 1>, + <179 249 1>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + aoss_qmp: power-management@c300000 { + compatible =3D "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0x0 0x0c300000 0x0 0x400>; + + interrupts-extended =3D <&ipcc IPCC_MPROC_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells =3D <0>; + }; + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,kaanapali-tlmm"; + reg =3D <0x0 0x0f100000 0x0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 218>; + interrupt-controller; + #interrupt-cells =3D <2>; + wakeup-parent =3D <&pdc>; + + qup_uart7_default: qup-uart7-state { + /* TX, RX */ + pins =3D "gpio62", "gpio63"; + function =3D "qup1_se7"; + drive-strength =3D <2>; + bias-disable; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + + card-detect-pins { + pins =3D "gpio55"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + + card-detect-pins { + pins =3D "gpio55"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + }; + + sram@14680000 { + compatible =3D "qcom,kaanapali-imem", "mmio-sram"; + reg =3D <0x0 0x14680000 0x0 0x1000>; + ranges =3D <0 0 0x14680000 0x1000>; + + no-memory-wc; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + pil-sram@94c { + compatible =3D "qcom,pil-reloc-info"; + reg =3D <0x94c 0xc8>; + }; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,kaanapali-smmu-500", "qcom,smmu-500", "arm,mmu-500= "; + reg =3D <0x0 0x15000000 0x0 0x100000>; + + interrupts =3D, + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + + dma-coherent; + }; + + intc: interrupt-controller@17000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x200000>; + + interrupts =3D ; + + #interrupt-cells =3D <3>; + interrupt-controller; + + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x40000>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic_its: msi-controller@17040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x17040000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + }; + + watchdog@17600000 { + compatible =3D "qcom,apss-wdt-kaanapali", "qcom,kpss-wdt"; + reg =3D <0x0 0x17600000 0x0 0x1000>; + clocks =3D <&sleep_clk>; + interrupts =3D ; + }; + + pdp0_mbox: mailbox@17610000 { + compatible =3D "qcom,kaanapali-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg =3D <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; + interrupts =3D ; + #mbox-cells =3D <1>; + }; + + timer@17810000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17810000 0x0 0x1000>; + + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges =3D <0 0 0 0 0x20000000>; + + frame@17811000 { + reg =3D <0x0 0x17811000 0x1000>, + <0x0 0x17812000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + + frame@17813000 { + reg =3D <0x0 0x17813000 0x1000>; + frame-number =3D <1>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17815000 { + reg =3D <0x0 0x17815000 0x1000>; + frame-number =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17817000 { + reg =3D <0x0 0x17817000 0x1000>; + frame-number =3D <3>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17819000 { + reg =3D <0x0 0x17819000 0x1000>; + frame-number =3D <4>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@1781b000 { + reg =3D <0x0 0x1781b000 0x1000>; + frame-number =3D <5>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@1781d000 { + reg =3D <0x0 0x1781d000 0x1000>; + frame-number =3D <6>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@18900000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18900000 0x0 0x10000>, + <0x0 0x18910000 0x0 0x10000>, + <0x0 0x18920000 0x0 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + interrupts =3D , + , + ; + + power-domains =3D <&system_pd>; + label =3D "apps_rsc"; + + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,kaanapali-rpmh-clk"; + #clock-cells =3D <1>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,kaanapali-rpmhpd"; + + operating-points-v2 =3D <&rpmhpd_opp_table>; + + #power-domain-cells =3D <1>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d3: opp-50 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d2_1: opp-51 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d1_1: opp-54 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_l0: opp-76 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_l2: opp-96 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l2: opp-224 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l0: opp-400 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l2: opp-432 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l3: opp-448 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l4: opp-452 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l5: opp-456 { + opp-level =3D ; + }; + + rpmhpd_opp_super_turbo_no_cpr: opp-480 { + opp-level =3D ; + }; + }; + }; + }; + + nsp_noc: interconnect@260c0000 { + compatible =3D "qcom,kaanapali-nsp-noc"; + reg =3D <0x0 0x260c0000 0x0 0x21280>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + /* Cluster 0 */ + pmu@310b3400 { + compatible =3D "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; + reg =3D <0x0 0x310b3400 0x0 0x600>; + + interrupts =3D ; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 =3D <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-0 { + opp-peak-kBps =3D <2188000>; + }; + + opp-1 { + opp-peak-kBps =3D <5412000>; + }; + + opp-2 { + opp-peak-kBps =3D <6220000>; + }; + + opp-3 { + opp-peak-kBps =3D <6832000>; + }; + + opp-4 { + opp-peak-kBps =3D <8368000>; + }; + + opp-5 { + opp-peak-kBps =3D <10944000>; + }; + + opp-6 { + opp-peak-kBps =3D <12748000>; + }; + + opp-7 { + opp-peak-kBps =3D <14744000>; + }; + + opp-8 { + opp-peak-kBps =3D <16896000>; + }; + + opp-9 { + opp-peak-kBps =3D <19120000>; + }; + + opp-10 { + opp-peak-kBps =3D <21332000>; + }; + }; + }; + + /* Cluster 1 */ + pmu@310b7400 { + compatible =3D "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; + reg =3D <0x0 0x310b7400 0x0 0x600>; + + interrupts =3D ; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 =3D <&cpu_bwmon_opp_table>; + }; + + gem_noc: interconnect@31100000 { + compatible =3D "qcom,kaanapali-gem-noc"; + reg =3D <0x0 0x31100000 0x0 0x153080>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + #interconnect-cells =3D <2>; + }; + + system-cache-controller@31800000 { + compatible =3D "qcom,kaanapali-llcc"; + reg =3D <0x0 0x31800000 0x0 0x200000>, + <0x0 0x32800000 0x0 0x200000>, + <0x0 0x31c00000 0x0 0x200000>, + <0x0 0x32c00000 0x0 0x200000>, + <0x0 0x34800000 0x0 0x200000>, + <0x0 0x34c00000 0x0 0x200000>; + reg-names =3D "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + + interrupts =3D ; + }; + + sram: sram@81f08000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x81f08000 0x0 0x200>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0 0x81f08000 0x200>; + + pdp_rx: scp-sram-section@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x80>; + }; + + pdp_tx: scp-sram-section@100 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x100 0x80>; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + + interrupts =3D , + , + , + ; + }; +}; --=20 2.25.1