From nobody Fri Dec 19 09:46:25 2025 Received: from mail40.out.titan.email (mail40.out.titan.email [209.209.25.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D50B91E2606 for ; Tue, 9 Dec 2025 14:19:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.209.25.23 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765289974; cv=none; b=curGUtN4P+KWXmsYD7AfGW3MIs6nrLoXa04fDv8eN6cRHEwfrl6quWPT8TXDlnDU+kzIdmH3YhwuL5/I01qWKqDdiRYFPVOOwWpInWvtl/9y35Jiyh+cUS4l1QTed8kjSEn+rFDWLRsJBrW3pbrwSlU5mBFovRU0i+/6y8K5nmM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765289974; c=relaxed/simple; bh=mLxHM7v3nc2eSPeHc66Rsm2ca/TBQClwE1qkrXRjbiI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cS4J+U9Q90VP69BdaJcFKJ+rbsaCQ63FSroY93I/HNCU7uSh8yq8FYvJwtADXWGTJbSfjAKcbMRl9JvHh1p8Ta9D+BeEZx4JuQvmLWYyby91etsUzwXOV3wc6TMU4MVmQAZcOPhEKUMCax5zq56CIMlTUKs3pipXTExopgKm4RA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ziyao.cc; spf=pass smtp.mailfrom=ziyao.cc; dkim=pass (1024-bit key) header.d=ziyao.cc header.i=@ziyao.cc header.b=Rfsr7aE/; arc=none smtp.client-ip=209.209.25.23 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ziyao.cc Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ziyao.cc Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ziyao.cc header.i=@ziyao.cc header.b="Rfsr7aE/" Received: from localhost (localhost [127.0.0.1]) by smtp-out.flockmail.com (Postfix) with ESMTP id 4dQgVB3gRZz9s0g; Tue, 9 Dec 2025 14:00:34 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=A7BJ2vjwLN9PGUv41KyJdSJlE9d2VhELFYZ/HdmZbZs=; c=relaxed/relaxed; d=ziyao.cc; h=cc:references:mime-version:subject:from:to:in-reply-to:date:message-id:from:to:cc:subject:date:message-id:in-reply-to:references:reply-to; q=dns/txt; s=titan1; t=1765288834; v=1; b=Rfsr7aE/YKzbZWePife2RDVHBt4e//dtbnKSd6Lb4fT/Qy7fEss4BCcdM9+ojpku1NH8gpJP c/W8bJYEHI7nBBlTAiKYE1uyDxQ6La+eqoTVjGol04jxbSWIzjI4OLoLmc2Sp7U7kthlqTTz45Y XoQ7HFBrpRudksz8YwBtM7wQ= Received: from ketchup (unknown [117.171.66.90]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp-out.flockmail.com (Postfix) with ESMTPSA id 4dQgV40ylDz9rxt; Tue, 9 Dec 2025 14:00:27 +0000 (UTC) Feedback-ID: :me@ziyao.cc:ziyao.cc:flockmailId From: Yao Zi To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui , Jiaxun Yang , Binbin Zhou Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Yao Zi Subject: [PATCH 1/2] LoongArch: dts: Describe PCI sideband IRQ through interrupt-extended Date: Tue, 9 Dec 2025 14:00:05 +0000 Message-ID: <20251209140006.54821-2-me@ziyao.cc> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251209140006.54821-1-me@ziyao.cc> References: <20251209140006.54821-1-me@ziyao.cc> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-F-Verdict: SPFVALID X-Titan-Src-Out: 1765288834073928996.21635.2100463422223919414@prod-use1-smtp-out1003. X-CMAE-Score: 0 X-CMAE-Analysis: v=2.4 cv=a8/K9VSF c=1 sm=1 tr=0 ts=69382b82 a=rBp+3XZz9uO5KTvnfbZ58A==:117 a=rBp+3XZz9uO5KTvnfbZ58A==:17 a=MKtGQD3n3ToA:10 a=1oJP67jkp3AA:10 a=CEWIc4RMnpUA:10 a=W4-7hV26G1j7c2fSSyQA:9 a=3z85VNIBY5UIEeAh_hcH:22 a=NWVoK91CQySWRX1oVYDe:22 Content-Type: text/plain; charset="utf-8" SoC integrated peripherals on LS2K1000 and LS2K2000 could be discovered as PCI devices, but require sideband interrupts to function, which are previously described by interrupts and interrupt-parent properties. However, pci/pci-device.yaml allows interrupts property to only specify PCI INTx interrupts, not sideband ones. Convert these devices to use interrupt-extended property, which describes sideband interrupts used by PCI devices since dt-schema commit e6ea659d2baa ("schemas: pci-device: Allow interrupts-extended for sideband interrupts"), eliminating dtbs_check warnings. Fixes: 30a5532a3206 ("LoongArch: dts: DeviceTree for Loongson-2K1000") Signed-off-by: Yao Zi --- arch/loongarch/boot/dts/loongson-2k1000.dtsi | 25 ++++++--------- arch/loongarch/boot/dts/loongson-2k2000.dtsi | 32 ++++++++------------ 2 files changed, 21 insertions(+), 36 deletions(-) diff --git a/arch/loongarch/boot/dts/loongson-2k1000.dtsi b/arch/loongarch/= boot/dts/loongson-2k1000.dtsi index 60ab425f793f..eee06b84951c 100644 --- a/arch/loongarch/boot/dts/loongson-2k1000.dtsi +++ b/arch/loongarch/boot/dts/loongson-2k1000.dtsi @@ -437,54 +437,47 @@ pcie@1a000000 { =20 gmac0: ethernet@3,0 { reg =3D <0x1800 0x0 0x0 0x0 0x0>; - interrupt-parent =3D <&liointc0>; - interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH>, - <13 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended =3D <&liointc0 12 IRQ_TYPE_LEVEL_HIGH>, + <&liointc0 13 IRQ_TYPE_LEVEL_HIGH>; interrupt-names =3D "macirq", "eth_lpi"; status =3D "disabled"; }; =20 gmac1: ethernet@3,1 { reg =3D <0x1900 0x0 0x0 0x0 0x0>; - interrupt-parent =3D <&liointc0>; - interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH>, - <15 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended =3D <&liointc0 14 IRQ_TYPE_LEVEL_HIGH>, + <&liointc0 15 IRQ_TYPE_LEVEL_HIGH>; interrupt-names =3D "macirq", "eth_lpi"; status =3D "disabled"; }; =20 ehci0: usb@4,1 { reg =3D <0x2100 0x0 0x0 0x0 0x0>; - interrupt-parent =3D <&liointc1>; - interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended =3D <&liointc1 18 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; }; =20 ohci0: usb@4,2 { reg =3D <0x2200 0x0 0x0 0x0 0x0>; - interrupt-parent =3D <&liointc1>; - interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended =3D <&liointc1 19 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; }; =20 display@6,0 { reg =3D <0x3000 0x0 0x0 0x0 0x0>; - interrupt-parent =3D <&liointc0>; - interrupts =3D <28 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended =3D <&liointc0 28 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; }; =20 hda@7,0 { reg =3D <0x3800 0x0 0x0 0x0 0x0>; - interrupt-parent =3D <&liointc0>; - interrupts =3D <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended =3D <&liointc0 4 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; }; =20 sata: sata@8,0 { reg =3D <0x4000 0x0 0x0 0x0 0x0>; - interrupt-parent =3D <&liointc0>; - interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended =3D <&liointc0 19 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; }; =20 diff --git a/arch/loongarch/boot/dts/loongson-2k2000.dtsi b/arch/loongarch/= boot/dts/loongson-2k2000.dtsi index 6c77b86ee06c..87c45f1f7cc7 100644 --- a/arch/loongarch/boot/dts/loongson-2k2000.dtsi +++ b/arch/loongarch/boot/dts/loongson-2k2000.dtsi @@ -291,65 +291,57 @@ pcie@1a000000 { =20 gmac0: ethernet@3,0 { reg =3D <0x1800 0x0 0x0 0x0 0x0>; - interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH>, - <13 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended =3D <&pic 12 IRQ_TYPE_LEVEL_HIGH>, + <&pic 13 IRQ_TYPE_LEVEL_HIGH>; interrupt-names =3D "macirq", "eth_lpi"; - interrupt-parent =3D <&pic>; status =3D "disabled"; }; =20 gmac1: ethernet@3,1 { reg =3D <0x1900 0x0 0x0 0x0 0x0>; - interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH>, - <15 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended =3D <&pic 14 IRQ_TYPE_LEVEL_HIGH>, + <&pic 15 IRQ_TYPE_LEVEL_HIGH>; interrupt-names =3D "macirq", "eth_lpi"; - interrupt-parent =3D <&pic>; status =3D "disabled"; }; =20 gmac2: ethernet@3,2 { reg =3D <0x1a00 0x0 0x0 0x0 0x0>; - interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH>, - <18 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended =3D <&pic 17 IRQ_TYPE_LEVEL_HIGH>, + <&pic 18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names =3D "macirq", "eth_lpi"; - interrupt-parent =3D <&pic>; status =3D "disabled"; }; =20 xhci0: usb@4,0 { reg =3D <0x2000 0x0 0x0 0x0 0x0>; - interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent =3D <&pic>; + interrupts-extended =3D <&pic 48 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; }; =20 xhci1: usb@19,0 { reg =3D <0xc800 0x0 0x0 0x0 0x0>; - interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent =3D <&pic>; + interrupts-extended =3D <&pic 22 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; }; =20 display@6,1 { reg =3D <0x3100 0x0 0x0 0x0 0x0>; - interrupts =3D <28 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent =3D <&pic>; + interrupts-extended =3D <&pic 28 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; }; =20 i2s@7,0 { reg =3D <0x3800 0x0 0x0 0x0 0x0>; - interrupts =3D <78 IRQ_TYPE_LEVEL_HIGH>, - <79 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended =3D <&pic 78 IRQ_TYPE_LEVEL_HIGH>, + <&pic 79 IRQ_TYPE_LEVEL_HIGH>; interrupt-names =3D "tx", "rx"; - interrupt-parent =3D <&pic>; status =3D "disabled"; }; =20 sata: sata@8,0 { reg =3D <0x4000 0x0 0x0 0x0 0x0>; - interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent =3D <&pic>; + interrupts-extended =3D <&pic 16 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; }; =20 --=20 2.51.2 From nobody Fri Dec 19 09:46:25 2025 Received: from mail5.out.flockmail.com (mail5.out.flockmail.com [54.161.96.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F9A92DC321 for ; Tue, 9 Dec 2025 14:09:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 9 Dec 2025 14:00:34 +0000 (UTC) Feedback-ID: :me@ziyao.cc:ziyao.cc:flockmailId From: Yao Zi To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui , Jiaxun Yang , Binbin Zhou Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Yao Zi Subject: [PATCH 2/2] dt-bindings: PCI: loongson: Document msi-parent property Date: Tue, 9 Dec 2025 14:00:06 +0000 Message-ID: <20251209140006.54821-3-me@ziyao.cc> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251209140006.54821-1-me@ziyao.cc> References: <20251209140006.54821-1-me@ziyao.cc> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-F-Verdict: SPFVALID X-Titan-Src-Out: 1765288842007571500.21635.6149325618728624297@prod-use1-smtp-out1003. X-CMAE-Score: 0 X-CMAE-Analysis: v=2.4 cv=a8/K9VSF c=1 sm=1 tr=0 ts=69382b8a a=rBp+3XZz9uO5KTvnfbZ58A==:117 a=rBp+3XZz9uO5KTvnfbZ58A==:17 a=MKtGQD3n3ToA:10 a=1oJP67jkp3AA:10 a=CEWIc4RMnpUA:10 a=luwqUdSl4_V6MCu2PjAA:9 a=3z85VNIBY5UIEeAh_hcH:22 a=NWVoK91CQySWRX1oVYDe:22 Content-Type: text/plain; charset="utf-8" Loongson PCI controllers found in LS2K1000/2000 SoCs (loongson,ls2k-pci), 7A1000/2000 bridge chips (loongson,ls7a-pci), and RS780E bridge chips (loongson,rs780e-pci) all have their paired MSI controllers. Though only the one in LS2K2000 SoC is described in devicetree, we should document the property for all variants. For the same reason, it isn't marked as required for now. Fixes: 83e757ecfd5d ("dt-bindings: Document Loongson PCI Host Controller") Signed-off-by: Yao Zi Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/loongson.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/loongson.yaml b/Document= ation/devicetree/bindings/pci/loongson.yaml index e5bba63aa947..26e77218b901 100644 --- a/Documentation/devicetree/bindings/pci/loongson.yaml +++ b/Documentation/devicetree/bindings/pci/loongson.yaml @@ -32,6 +32,8 @@ properties: minItems: 1 maxItems: 3 =20 + msi-parent: true + required: - compatible - reg --=20 2.51.2