From nobody Fri Dec 19 11:29:42 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA4052E093B; Tue, 9 Dec 2025 10:34:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765276466; cv=none; b=hF2e1BbOeXD2lPvQBmsKDAqr4L50xwG7wynOfqt88RHm8XiO0ckRU5EhXiHbv4zmRIRDhe+J++gVsOpXWR6fuJ0hrTT4K2dIRQ6Zvtka7IlpXjM8ymW+E1cbNGCkfxfD2CJYi6uCRJP3wF37OIuAuAt7mQmaWOAwBKTNKNJ9v+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765276466; c=relaxed/simple; bh=SGzx6Y6h73rZhJ/XlDZgJtNuHxNiFSCSI+vKYl0sD4c=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=eXu08HZyvKk1LqMmS/Kx9qxuA8rAc5Rcyz+gR5hFBMBp4bJFvIWotgGt+Rfcv106RhxKZ+kDdiOyo3ySKrvRX2m4irXGpmxSHvGAP+JxECoi8HIOybNIuWk0eF5UGEg7Vf6qWdg1HkDZZ5fU88B5YrF/sfNBJOoP8yhjgV3UfjM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=VbL+huk3; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="VbL+huk3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1765276462; bh=SGzx6Y6h73rZhJ/XlDZgJtNuHxNiFSCSI+vKYl0sD4c=; h=From:To:Cc:Subject:Date:From; b=VbL+huk3oLxZ6uOD2TRLlO3udMAYmoCxWhlq7ahucLf5waifua2yf2JyQRKWWh+/7 YekQlmJ4btcliQpdEI7gEDFjTGeoNK0Nlwo20iqoaweHtxIdLuUPydp0FeeQmHS3iQ fNc+EijSN+OK9OJOWu9VSKsT6ZCpkXKyEw5EStIK7vReKmNnp+XKHD0zRCd3biWfyC 18GpXkbYe1WNt24Kk86fzMOPjUZDnEcUtTZyxd+PB4cu3Cwk79ZOIi1iisAE8YLa7L MStTvp8am+UNNNR9o+kIZNUZ98kgLzbqjWhhJMhgJroi/5xMrubA7V41ZwVCwIMyra nN/J25MIqBalw== Received: from benjamin-XPS-13-9310.. (unknown [IPv6:2a01:e0a:120:3210:2285:5e2d:9392:bcdf]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bali.collaboradmins.com (Postfix) with ESMTPSA id 363F017E0330; Tue, 9 Dec 2025 11:34:22 +0100 (CET) From: Benjamin Gaignard To: nicolas.dufresne@collabora.com, p.zabel@pengutronix.de, mchehab@kernel.org, heiko@sntech.de, hverkuil@kernel.org Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Benjamin Gaignard Subject: [PATCH v2] media: verisilicon: AV1: Fix tx mode bit setting Date: Tue, 9 Dec 2025 11:34:17 +0100 Message-ID: <20251209103417.21966-1-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AV1 specification describes 3 possibles tx modes: 4x4 only, largest and select. Hardware allows 5 possibles tx modes: 4x4 only, 8x8, 16x16, 32x32 and select. Since the both aren't exactly matching we need to add a mapping function to set the correct mode on hardware. Signed-off-by: Benjamin Gaignard Fixes: 727a400686a2c ("media: verisilicon: Add Rockchip AV1 decoder") --- .../verisilicon/rockchip_vpu981_hw_av1_dec.c | 27 ++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.= c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c index f4f7cb45b1f1..f52b8208e6b9 100644 --- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c +++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c @@ -72,6 +72,14 @@ : AV1_DIV_ROUND_UP_POW2((_value_), (_n_))); \ }) =20 +enum rockchip_av1_tx_mode { + ROCKCHIP_AV1_TX_MODE_ONLY_4X4 =3D 0, + ROCKCHIP_AV1_TX_MODE_8X8 =3D 1, + ROCKCHIP_AV1_TX_MODE_16x16 =3D 2, + ROCKCHIP_AV1_TX_MODE_32x32 =3D 3, + ROCKCHIP_AV1_TX_MODE_SELECT =3D 4, +}; + struct rockchip_av1_film_grain { u8 scaling_lut_y[256]; u8 scaling_lut_cb[256]; @@ -1935,11 +1943,26 @@ static void rockchip_vpu981_av1_dec_set_reference_f= rames(struct hantro_ctx *ctx) rockchip_vpu981_av1_dec_set_other_frames(ctx); } =20 +static int rockchip_vpu981_av1_get_hardware_tx_mode(enum v4l2_av1_tx_mode = tx_mode) +{ + switch (tx_mode) { + case V4L2_AV1_TX_MODE_ONLY_4X4: + return ROCKCHIP_AV1_TX_MODE_ONLY_4X4; + case V4L2_AV1_TX_MODE_LARGEST: + return ROCKCHIP_AV1_TX_MODE_32x32; + case V4L2_AV1_TX_MODE_SELECT: + return ROCKCHIP_AV1_TX_MODE_SELECT; + } + + return ROCKCHIP_AV1_TX_MODE_32x32; +} + static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx) { struct hantro_dev *vpu =3D ctx->dev; struct hantro_av1_dec_hw_ctx *av1_dec =3D &ctx->av1_dec; struct hantro_av1_dec_ctrls *ctrls =3D &av1_dec->ctrls; + int tx_mode; =20 hantro_reg_write(vpu, &av1_skip_mode, !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SKIP_MODE_PRESENT)); @@ -2005,7 +2028,9 @@ static void rockchip_vpu981_av1_dec_set_parameters(st= ruct hantro_ctx *ctx) !!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_HIGH_PRECISION_MV)); hantro_reg_write(vpu, &av1_comp_pred_mode, (ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_REFERENCE_SELECT) ? 2 : 0); - hantro_reg_write(vpu, &av1_transform_mode, (ctrls->frame->tx_mode =3D=3D = 1) ? 3 : 4); + + tx_mode =3D rockchip_vpu981_av1_get_hardware_tx_mode(ctrls->frame->tx_mod= e); + hantro_reg_write(vpu, &av1_transform_mode, tx_mode); hantro_reg_write(vpu, &av1_max_cb_size, (ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_USE_128X128_SUPERBLOCK) ? 7 : 6); --=20 2.43.0