From nobody Mon Feb 9 01:16:59 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0FB282D12ED; Tue, 9 Dec 2025 09:11:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765271495; cv=none; b=WooppnqwKzzwDR4IcAu9hVERZUVJosFCdV4NrEMSuvTuBfqfUzFrYFsNGpyPAuwQMmI245mdCoQebfXI2yGUkjleT8+chSBAckJ9XiZT9jgN3juk8HkL99R5Paw71tQFO87/DznpHcrWU3o6v2ptFuxmsfOtliWOSeR5OVmPHkk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765271495; c=relaxed/simple; bh=jjCcNU6521+jhdzUHgDC++nvbAEjOdLIhUK5/nIcTMg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fAVVNHdQP76Sro8KwwJbj19g1nBn7ENtLU6eYoc0gB6INmh1U6yB+ATUYR1x3jDac32sepcCrve1BLtxN1s4Pk0l2gqfLZf0bKHoSQtpMYBjRUcV6VOMFQq94FR3Fab4jW5uR6uXCHos6ESAEA8mIth0dgWpMhnPx5hsVhY1QzQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: 7GT+ANnEQc2bnUysy6oDww== X-CSE-MsgGUID: zw9vNks8QFOJPMS711FY6A== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 09 Dec 2025 18:11:27 +0900 Received: from vm01.adwin.renesas.com (unknown [10.226.92.124]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9C5CA40071EC; Tue, 9 Dec 2025 18:11:22 +0900 (JST) From: Ovidiu Panait To: john.madieu.xa@bp.renesas.com, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: thermal: r9a09g047-tsu: Document RZ/V2N TSU Date: Tue, 9 Dec 2025 09:11:13 +0000 Message-ID: <20251209091115.8541-2-ovidiu.panait.rb@renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251209091115.8541-1-ovidiu.panait.rb@renesas.com> References: <20251209091115.8541-1-ovidiu.panait.rb@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/V2N SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing two dedicated channels for temperature sensing. The Renesas RZ/V2N SoC is using the same TSU IP found on the RZ/G3E SoC, the only difference being that it has two channels instead of one. Add new compatible string "renesas,r9a09g056-tsu" for RZ/V2N and use "renesas,r9a09g047-tsu" as a fallback compatible to indicate hardware compatibility with the RZ/G3E implementation. Signed-off-by: Ovidiu Panait Acked-by: Rob Herring (Arm) Reviewed-by: Geert Uytterhoeven --- .../devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-ts= u.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.ya= ml index a04e5048eadf..d560c58be4d6 100644 --- a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml @@ -21,7 +21,9 @@ properties: - renesas,r9a09g047-tsu # RZ/G3E - renesas,r9a09g077-tsu # RZ/T2H - items: - - const: renesas,r9a09g057-tsu # RZ/V2H + - enum: + - renesas,r9a09g056-tsu # RZ/V2N + - renesas,r9a09g057-tsu # RZ/V2H - const: renesas,r9a09g047-tsu # RZ/G3E - items: - const: renesas,r9a09g087-tsu # RZ/N2H --=20 2.51.0 From nobody Mon Feb 9 01:16:59 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2AA3F26F2B8; Tue, 9 Dec 2025 09:11:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765271503; cv=none; b=pVwN9s7lRjjkGlTZoIVaeDJVUy121Z7gS25gj8w6y/0J7wiBmPkg0VRgZWXCaRfJhD9+7h35KcpNp2YdfvPT0NaDdgMAFnOJElWFcxkOY1cWuLAPTvZqEYFQMb9TaVkdltAEf/SKe8V17SRu0a5KNn3X2tk3ULM0UQSfNzKPiy8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765271503; c=relaxed/simple; bh=b1Pzn2+PxNwyEgJQcrpu2UWu+2svMokxcbNopM/8f8A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MUU72UJiGrdbZonM1d7viRpFSWJrbhR+ItbSvz3HrWLWeaTI1OlUKPFY04ZuxMDwEoZQzsdg5ErruyduuxG/HSsfF6Z6JfNBBoD/NP2RrF1kOd8w473+qoFPjK6RODxY4nAboQRa3QOBFm//g40fOc84Aw2tOw0c4WGtTeQwM+s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: MxVW9n1sQZexSEN6mO5Wwg== X-CSE-MsgGUID: VSTmk3wHQ6qDWvQiXX7gVw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 09 Dec 2025 18:11:33 +0900 Received: from vm01.adwin.renesas.com (unknown [10.226.92.124]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 7F02240071EC; Tue, 9 Dec 2025 18:11:28 +0900 (JST) From: Ovidiu Panait To: john.madieu.xa@bp.renesas.com, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/3] clk: renesas: r9a09g056: Add clock and reset entries for TSU Date: Tue, 9 Dec 2025 09:11:14 +0000 Message-ID: <20251209091115.8541-3-ovidiu.panait.rb@renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251209091115.8541-1-ovidiu.panait.rb@renesas.com> References: <20251209091115.8541-1-ovidiu.panait.rb@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add module clock and reset entries for the TSU0 and TSU1 blocks on the Renesas RZ/V2N (R9A09G056) SoC. Signed-off-by: Ovidiu Panait Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g056-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a0= 9g056-cpg.c index f48a082e65d7..77e0154a28dd 100644 --- a/drivers/clk/renesas/r9a09g056-cpg.c +++ b/drivers/clk/renesas/r9a09g056-cpg.c @@ -397,6 +397,10 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[]= __initconst =3D { BUS_MSTOP(3, BIT(4))), DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, BUS_MSTOP(3, BIT(4))), + DEF_MOD("tsu_0_pclk", CLK_QEXTAL, 16, 9, 8, 9, + BUS_MSTOP(5, BIT(2))), + DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, + BUS_MSTOP(2, BIT(15))), }; =20 static const struct rzv2h_reset r9a09g056_resets[] __initconst =3D { @@ -454,6 +458,8 @@ static const struct rzv2h_reset r9a09g056_resets[] __in= itconst =3D { DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */ DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */ DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */ + DEF_RST(15, 7, 7, 8), /* TSU_0_PRESETN */ + DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ }; =20 const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst =3D { --=20 2.51.0 From nobody Mon Feb 9 01:16:59 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DB3F928B4FD; Tue, 9 Dec 2025 09:11:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765271502; cv=none; b=fqN+O6MASbeeumYZn1xwmzmPFwI+gxIz5iL7bkmy0+YPOSYzGxiOmr/lmn3o0Ps58iCSwgVgHApUd7EcExP7j0M1MiOAsXWf/G1bW9olksxZU2GQWBSMTvu75aNvrX7rIjWstQ6ceoQz+naU4tWJiCT/9FpTHfX4IHjqFgmSBU8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765271502; c=relaxed/simple; bh=yRkqzoKV3n6zFPJocmJIqr17hOM4ahDb5J7rmZJnUa8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uR68/c5vMbHhlGF7U+/KtcmN8xua1HcBvWaqeLggcMI8YXgMCYiPKEVR/lO8keSD8AWBG0e/fjShpt8Ghp0ibCuONBt0em7Ypu6bqZ8HbVGh8B2PFXcWFsVP5ShRzevGTPyqgdUcZyl7pVD0vfUyJSqelM030R9ghQ6Ywe935R0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: QggkPq7eTByu+mLvWXrxfQ== X-CSE-MsgGUID: KoiSG0bKTUyae2CfrXvZyA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 09 Dec 2025 18:11:39 +0900 Received: from vm01.adwin.renesas.com (unknown [10.226.92.124]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 638B740071EC; Tue, 9 Dec 2025 18:11:34 +0900 (JST) From: Ovidiu Panait To: john.madieu.xa@bp.renesas.com, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 3/3] arm64: dts: renesas: r9a09g056: Add TSU nodes Date: Tue, 9 Dec 2025 09:11:15 +0000 Message-ID: <20251209091115.8541-4-ovidiu.panait.rb@renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251209091115.8541-1-ovidiu.panait.rb@renesas.com> References: <20251209091115.8541-1-ovidiu.panait.rb@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/V2N SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing two dedicated channels for temperature sensing: - TSU0, which is located near the DRP-AI block - TSU1, which is located near the CPU and DRP-AI block Since TSU1 is physically closer the CPU and the highest temperature spot, it is used for CPU throttling through a passive trip and cooling map. TSU0 is configured only with a critical trip. Add TSU nodes along with thermal zones and keep them enabled in the SoC DTSI. Signed-off-by: Ovidiu Panait Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 75 ++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g056.dtsi index 8781c2fa7313..5035ffdda79b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -83,6 +83,7 @@ cpu0: cpu@0 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -93,6 +94,7 @@ cpu1: cpu@100 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -103,6 +105,7 @@ cpu2: cpu@200 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -113,6 +116,7 @@ cpu3: cpu@300 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -211,6 +215,32 @@ sys: system-controller@10430000 { resets =3D <&cpg 0x30>; }; =20 + tsu0: thermal@11000000 { + compatible =3D "renesas,r9a09g056-tsu", "renesas,r9a09g047-tsu"; + reg =3D <0 0x11000000 0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "adi", "adcmpi"; + clocks =3D <&cpg CPG_MOD 0x109>; + resets =3D <&cpg 0xf7>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + renesas,tsu-trim =3D <&sys 0x320>; + }; + + tsu1: thermal@14002000 { + compatible =3D "renesas,r9a09g056-tsu", "renesas,r9a09g047-tsu"; + reg =3D <0 0x14002000 0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "adi", "adcmpi"; + clocks =3D <&cpg CPG_MOD 0x10a>; + resets =3D <&cpg 0xf8>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + renesas,tsu-trim =3D <&sys 0x330>; + }; + xspi: spi@11030000 { compatible =3D "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi"; reg =3D <0 0x11030000 0 0x10000>, @@ -964,6 +994,51 @@ stmmac_axi_setup: stmmac-axi-config { snps,blen =3D <16 8 4 0 0 0 0>; }; =20 + thermal-zones { + sensor1_thermal: sensor1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&tsu0>; + + trips { + sensor1_crit: sensor1-crit { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + sensor2_thermal: sensor2-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&tsu1>; + + cooling-maps { + map0 { + trip =3D <&sensor2_target>; + cooling-device =3D <&cpu0 0 3>, <&cpu1 0 3>, + <&cpu2 0 3>, <&cpu3 0 3>; + contribution =3D <1024>; + }; + }; + + trips { + sensor2_target: trip-point { + temperature =3D <95000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + sensor2_crit: sensor2-crit { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts =3D , --=20 2.51.0