From nobody Fri Dec 19 08:07:24 2025 Received: from out198-15.us.a.mail.aliyun.com (out198-15.us.a.mail.aliyun.com [47.90.198.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E4363126A5 for ; Tue, 9 Dec 2025 06:27:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765261676; cv=none; b=AOuOSka2IRmtNOQ3hZdrQbQZxsNdO8Y+o9zrWRp+UMthdKYxH3te2iX5HZJKu1FFgrjH3nvKTED0w73Sn5uXqGOE/MMGyyks6OMD6J+NWR3k9gwXUAROGMbr0fl5Ed2gctZwQnEYnrmapQEd7R6/wPhSkqWzSz+gQ6nyETzjVhY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765261676; c=relaxed/simple; bh=rnzWBtkTLmwGxORc3WjA6CEtXIImfRKRmqnSKbB64BA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hf2g4MA/F7rgwqdSiPk+3ovhDVmyojinn+6uDIbbfIB1HxDm8XCwkKVIL5IpZQCI8rlM76oUjYKG+zFIuiF0H+Bxfy3XWAQIzkTDyIJPZlaZfMQZ6GA2j8yTgDQXwnkK8lQmr7TCPLwysj/OO/Qz/LYOR0qDk3Kt5l7OZYfNga4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=47.90.198.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net Received: from localhost.localdomain(mailfrom:shenxiaochen@open-hieco.net fp:SMTPD_---.fg6MeSC_1765261653 cluster:ay29) by smtp.aliyun-inc.com; Tue, 09 Dec 2025 14:27:35 +0800 From: Xiaochen Shen To: tony.luck@intel.com, reinette.chatre@intel.com, bp@alien8.de, fenghuay@nvidia.com Cc: babu.moger@amd.com, james.morse@arm.com, Dave.Martin@arm.com, x86@kernel.org, linux-kernel@vger.kernel.org, shenxiaochen@open-hieco.net Subject: [PATCH v3 1/2] x86/resctrl: Add missing resctrl initialization for Hygon Date: Tue, 9 Dec 2025 14:26:49 +0800 Message-ID: <20251209062650.1536952-2-shenxiaochen@open-hieco.net> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251209062650.1536952-1-shenxiaochen@open-hieco.net> References: <20251209062650.1536952-1-shenxiaochen@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hygon CPUs supporting Platform QoS features currently undergo partial resctrl initialization through resctrl_cpu_detect() in the Hygon BSP init helper and AMD/Hygon common initialization code. However, several critical data structures remain uninitialized for Hygon CPUs in the following paths: - get_mem_config()-> __rdt_get_mem_config_amd(): rdt_resource::membw,alloc_capable hw_res::num_closid - rdt_init_res_defs()->rdt_init_res_defs_amd(): rdt_resource::cache hw_res::msr_base,msr_update Add the missing AMD/Hygon common initialization to ensure proper Platform QoS functionality on Hygon CPUs. Fixes: d8df126349da ("x86/cpu/hygon: Add missing resctrl_cpu_detect() in bs= p_init helper") Signed-off-by: Xiaochen Shen Reviewed-by: Reinette Chatre Cc: stable@vger.kernel.org --- arch/x86/kernel/cpu/resctrl/core.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 3792ab4819dc..10de1594d328 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -825,7 +825,8 @@ static __init bool get_mem_config(void) =20 if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) return __get_mem_config_intel(&hw_res->r_resctrl); - else if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) + else if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD || + boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) return __rdt_get_mem_config_amd(&hw_res->r_resctrl); =20 return false; @@ -987,7 +988,8 @@ static __init void rdt_init_res_defs(void) { if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) rdt_init_res_defs_intel(); - else if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) + else if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD || + boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) rdt_init_res_defs_amd(); } =20 --=20 2.47.3 From nobody Fri Dec 19 08:07:24 2025 Received: from out28-194.mail.aliyun.com (out28-194.mail.aliyun.com [115.124.28.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA2E431ED97 for ; Tue, 9 Dec 2025 06:27:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765261670; cv=none; b=b22SAf2fSLp0TYIfYUW0cniVC+ARFib4iBv+6EoPTRgNNSYdXyM09+KG/xS8yhgaJpCLgRfy+iB9Mx/ba+xHnwrI/uFfazSKojxalcMmTPnKkDZSUaq4TBFexjRwjtblhshRAJGV8pVhoIpkuLmS8QvLj6PfhL0GJpaTeKsolH8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765261670; c=relaxed/simple; bh=CmrqMBQh3ryk+N7OMnzdv3rQX2oQC1P5IMhDxgGxuD8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BvNgXVmSLEKcV83mu0pwLJ6ObtIQRkKh9ERQ3BPC1QeBMN4AVZZ7Vdi2lr7G4EWkC0579zgXgW4jUKyZBkw3KbDnlJGeN774UPsx/mqtNX9EZJ/cXanT2QlpocqfUJYxbv8JpTRNDDisa2C40RBp2X6eWkcugliV3zfA2qZr9ZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net Received: from localhost.localdomain(mailfrom:shenxiaochen@open-hieco.net fp:SMTPD_---.fg6MeVn_1765261656 cluster:ay29) by smtp.aliyun-inc.com; Tue, 09 Dec 2025 14:27:38 +0800 From: Xiaochen Shen To: tony.luck@intel.com, reinette.chatre@intel.com, bp@alien8.de, fenghuay@nvidia.com Cc: babu.moger@amd.com, james.morse@arm.com, Dave.Martin@arm.com, x86@kernel.org, linux-kernel@vger.kernel.org, shenxiaochen@open-hieco.net Subject: [PATCH v3 2/2] x86/resctrl: Fix memory bandwidth counter width for Hygon Date: Tue, 9 Dec 2025 14:26:50 +0800 Message-ID: <20251209062650.1536952-3-shenxiaochen@open-hieco.net> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251209062650.1536952-1-shenxiaochen@open-hieco.net> References: <20251209062650.1536952-1-shenxiaochen@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The memory bandwidth calculation relies on reading the hardware counter and measuring the delta between samples. To ensure accurate measurement, the software reads the counter frequently enough to prevent it from rolling over twice between reads. The default Memory Bandwidth Monitoring (MBM) counter width is 24 bits. Hygon CPUs provide a 32-bit width counter, but they do not support the MBM capability CPUID leaf (0xF.[ECX=3D1]:EAX) to report the width offset (from 24 bits). Consequently, the kernel falls back to the 24-bit default counter width, which causes incorrect overflow handling on Hygon CPUs. Fix this by explicitly setting the counter width offset to 8 bits (resulting in a 32-bit total counter width) for Hygon CPUs. Fixes: d8df126349da ("x86/cpu/hygon: Add missing resctrl_cpu_detect() in bs= p_init helper") Signed-off-by: Xiaochen Shen Reviewed-by: Tony Luck Reviewed-by: Reinette Chatre Cc: stable@vger.kernel.org --- arch/x86/kernel/cpu/resctrl/core.c | 15 +++++++++++++-- arch/x86/kernel/cpu/resctrl/internal.h | 3 +++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 10de1594d328..6ebff44a3f75 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -1021,8 +1021,19 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c) c->x86_cache_occ_scale =3D ebx; c->x86_cache_mbm_width_offset =3D eax & 0xff; =20 - if (c->x86_vendor =3D=3D X86_VENDOR_AMD && !c->x86_cache_mbm_width_offse= t) - c->x86_cache_mbm_width_offset =3D MBM_CNTR_WIDTH_OFFSET_AMD; + if (!c->x86_cache_mbm_width_offset) { + switch (c->x86_vendor) { + case X86_VENDOR_AMD: + c->x86_cache_mbm_width_offset =3D MBM_CNTR_WIDTH_OFFSET_AMD; + break; + case X86_VENDOR_HYGON: + c->x86_cache_mbm_width_offset =3D MBM_CNTR_WIDTH_OFFSET_HYGON; + break; + default: + /* Leave c->x86_cache_mbm_width_offset as 0 */ + break; + } + } } } =20 diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 4a916c84a322..79c18657ede0 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -14,6 +14,9 @@ =20 #define MBM_CNTR_WIDTH_OFFSET_AMD 20 =20 +/* Hygon MBM counter width as an offset from MBM_CNTR_WIDTH_BASE */ +#define MBM_CNTR_WIDTH_OFFSET_HYGON 8 + #define RMID_VAL_ERROR BIT_ULL(63) =20 #define RMID_VAL_UNAVAIL BIT_ULL(62) --=20 2.47.3