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Mon, 08 Dec 2025 21:23:32 -0800 (PST) Received: from hu-bibekkum-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-bf681738a29sm13689924a12.3.2025.12.08.21.23.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Dec 2025 21:23:32 -0800 (PST) From: bibek.patro@oss.qualcomm.com To: konrad.dybcio@oss.qualcomm.com, robin.clark@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Charan Teja Kalla , Bibek Kumar Patro Subject: [PATCH v5] iommu/arm-smmu-qcom: add actlr settings for mdss on Qualcomm platforms Date: Tue, 9 Dec 2025 10:53:23 +0530 Message-Id: <20251209052323.1133495-1-bibek.patro@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA5MDAzOSBTYWx0ZWRfX1XFGEMByx67h BA6m9YBOsHUlprGHETBa5DJNp3lwINIA/+9tC4Z1Bvz/zo3QxT9dEmbMxIGDOU3xc8WjvM47VNc Yzs7gHXJfkTaN5nayl4GetvqcnfmMzOkGnemKdp+AkoXKpkJmXpCG0OSrjhqPTYvT7tg/PKs41G N1fKfnt0PYQzUg1bxIzPiW5a8DzNmQFJlwdWCclgB7Q27zIfgRjmjGElUCKyw6p8rdFbFySV31l obsUALeg/T0RpOKu/84s0J9KoOHEv5R02eqkJVa1eZduMEGqzRkLNK41pUZtPjKi/bhGDp2symS 8vhpK9F1O4ZnhQBjkqkGrpp9jMbQwS9DZClJHzIinPwhBNq3uB1Ln8sKXNDCMEM+GMArhtHLYu/ XtJnFU3SHNCQuwxswm/qaBxjNDFgRA== X-Proofpoint-ORIG-GUID: MTwy0lR2p_oM34g4b-UNOm9XAZlu33Kc X-Proofpoint-GUID: MTwy0lR2p_oM34g4b-UNOm9XAZlu33Kc X-Authority-Analysis: v=2.4 cv=fsXRpV4f c=1 sm=1 tr=0 ts=6937b255 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Nhz1Ti08P7End7UVPfYA:9 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-08_07,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 malwarescore=0 suspectscore=0 adultscore=0 spamscore=0 clxscore=1015 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512090039 Content-Type: text/plain; charset="utf-8" From: Charan Teja Kalla Add ACTLR settings for missing MDSS devices on Qualcomm platforms. These are QoS settings and are specific to per SoC thus different settings, eg: some have shallow prefetch while others have no prefetch. Aswell, this prefetch feature is not implemented for all the platforms, capturing to those are implemented to the best of my knowledge. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Charan Teja Kalla Signed-off-by: Bibek Kumar Patro --- Changes from V4: 1) Change subject prefix to "iommu/arm-smmu-qcom:" based on the changes. -- Bjorn https://lore.kernel.org/all/20251202125447.2102658-1-charan.kalla@oss.qualc= omm.com/ Changes from V3: 1) Add actlr setting for missing sc8180x & sm6115. 2) Improved commit message. https://lore.kernel.org/all/20251124171030.323989-1-charan.kalla@oss.qualco= mm.com/ Changes from V2: 1) Add actlr settings for all the mdss devices on Qualcomm platforms. 2) Improved the commit message that explain why different ACTLR settings https://lore.kernel.org/lkml/20251118171822.3539062-1-charan.kalla@oss.qual= comm.com/#t Changes from V1: 1) Added actlr setting only for MDSS and dropped for fastrpc. -- konrad 2) ACTLR table is updated per alphanumeric order -- konrad=20 https://lore.kernel.org/all/20251105075307.1658329-1-charan.kalla@oss.qua= lcomm.com/ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 57c097e87613..c6645df97bbc 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -41,12 +41,38 @@ static const struct of_device_id qcom_smmu_actlr_client= _of_match[] =3D { .data =3D (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, { .compatible =3D "qcom,fastrpc", .data =3D (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, + { .compatible =3D "qcom,qcm2290-mdss", + .data =3D (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, { .compatible =3D "qcom,sc7280-mdss", .data =3D (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, { .compatible =3D "qcom,sc7280-venus", .data =3D (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, + { .compatible =3D "qcom,sc8180x-mdss", + .data =3D (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, + { .compatible =3D "qcom,sc8280xp-mdss", + .data =3D (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, + { .compatible =3D "qcom,sm6115-mdss", + .data =3D (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, + { .compatible =3D "qcom,sm6125-mdss", + .data =3D (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, + { .compatible =3D "qcom,sm6350-mdss", + .data =3D (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, + { .compatible =3D "qcom,sm8150-mdss", + .data =3D (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, + { .compatible =3D "qcom,sm8250-mdss", + .data =3D (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, + { .compatible =3D "qcom,sm8350-mdss", + .data =3D (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, + { .compatible =3D "qcom,sm8450-mdss", + .data =3D (const void *) (PREFETCH_DEFAULT | CMTLB) }, { .compatible =3D "qcom,sm8550-mdss", .data =3D (const void *) (PREFETCH_DEFAULT | CMTLB) }, + { .compatible =3D "qcom,sm8650-mdss", + .data =3D (const void *) (PREFETCH_DEFAULT | CMTLB) }, + { .compatible =3D "qcom,sm8750-mdss", + .data =3D (const void *) (PREFETCH_DEFAULT | CMTLB) }, + { .compatible =3D "qcom,x1e80100-mdss", + .data =3D (const void *) (PREFETCH_DEFAULT | CMTLB) }, { } }; =20 --=20 2.34.1