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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b412deddsm11547484a12.31.2025.12.08.07.21.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Dec 2025 07:21:40 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Philipp Zabel Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 7/9] pwm: rzg2l-gpt: Add suspend/resume support Date: Mon, 8 Dec 2025 15:21:24 +0000 Message-ID: <20251208152133.269316-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> References: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das On RZ/G3E using PSCI, s2ram powers down the SoC. Add suspend/resume callbacks for save/restore GPT context. Signed-off-by: Biju Das --- v3->v4: * Added error checks on suspend() and device set to operational state on failure(). v3: * New patch. --- drivers/pwm/pwm-rzg2l-gpt.c | 132 +++++++++++++++++++++++++++++++----- 1 file changed, 116 insertions(+), 16 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 79ee59271d24..4eac35390c60 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -90,14 +90,26 @@ struct rzg2l_gpt_info { u8 prescale_mult; }; =20 +struct rzg2l_gpt_cache { + u32 gtpr; + u32 gtccr[2]; + u32 gtcr; + u32 gtior; +}; + struct rzg2l_gpt_chip { void __iomem *mmio; struct mutex lock; /* lock to protect shared channel resources */ const struct rzg2l_gpt_info *info; + struct clk *clk; + struct clk *bus_clk; + struct reset_control *rst; + struct reset_control *rst_s; unsigned long rate_khz; u32 period_ticks[RZG2L_MAX_HW_CHANNELS]; u32 channel_request_count[RZG2L_MAX_HW_CHANNELS]; u32 channel_enable_count[RZG2L_MAX_HW_CHANNELS]; + struct rzg2l_gpt_cache hw_cache[RZG2L_MAX_HW_CHANNELS]; }; =20 /* This represents a hardware configuration for one channel */ @@ -462,10 +474,8 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) { struct rzg2l_gpt_chip *rzg2l_gpt; struct device *dev =3D &pdev->dev; - struct reset_control *rstc; struct pwm_chip *chip; unsigned long rate; - struct clk *clk; int ret; =20 chip =3D devm_pwmchip_alloc(dev, RZG2L_MAX_PWM_CHANNELS, sizeof(*rzg2l_gp= t)); @@ -479,27 +489,29 @@ static int rzg2l_gpt_probe(struct platform_device *pd= ev) =20 rzg2l_gpt->info =3D of_device_get_match_data(dev); =20 - rstc =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); - if (IS_ERR(rstc)) - return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\= n"); + rzg2l_gpt->rst =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); + if (IS_ERR(rzg2l_gpt->rst)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->rst), + "Cannot deassert reset control\n"); =20 - rstc =3D devm_reset_control_get_optional_exclusive_deasserted(dev, "rst_s= "); - if (IS_ERR(rstc)) - return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert rst_s reset\n"= ); + rzg2l_gpt->rst_s =3D devm_reset_control_get_optional_exclusive_deasserted= (dev, "rst_s"); + if (IS_ERR(rzg2l_gpt->rst_s)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->rst_s), + "Cannot deassert rst_s reset\n"); =20 - clk =3D devm_clk_get_optional_enabled(dev, "bus"); - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "Cannot get bus clock\n"); + rzg2l_gpt->bus_clk =3D devm_clk_get_optional_enabled(dev, "bus"); + if (IS_ERR(rzg2l_gpt->bus_clk)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->bus_clk), "Cannot get bus c= lock\n"); =20 - clk =3D devm_clk_get_enabled(dev, NULL); - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n"); + rzg2l_gpt->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(rzg2l_gpt->clk)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->clk), "Cannot get clock\n"); =20 - ret =3D devm_clk_rate_exclusive_get(dev, clk); + ret =3D devm_clk_rate_exclusive_get(dev, rzg2l_gpt->clk); if (ret) return ret; =20 - rate =3D clk_get_rate(clk); + rate =3D clk_get_rate(rzg2l_gpt->clk); if (!rate) return dev_err_probe(dev, -EINVAL, "The gpt clk rate is 0"); =20 @@ -526,7 +538,92 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) if (ret) return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); =20 + platform_set_drvdata(pdev, chip); + + return 0; +} + +static int rzg2l_gpt_suspend(struct device *dev) +{ + struct pwm_chip *chip =3D dev_get_drvdata(dev); + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + unsigned int i; + int ret; + + for (i =3D 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!rzg2l_gpt->channel_enable_count[i]) + continue; + + rzg2l_gpt->hw_cache[i].gtpr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(i)); + rzg2l_gpt->hw_cache[i].gtccr[0] =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCC= R(i, 0)); + rzg2l_gpt->hw_cache[i].gtccr[1] =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCC= R(i, 1)); + rzg2l_gpt->hw_cache[i].gtcr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(i)); + rzg2l_gpt->hw_cache[i].gtior =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTIOR(i= )); + } + + clk_disable_unprepare(rzg2l_gpt->clk); + clk_disable_unprepare(rzg2l_gpt->bus_clk); + ret =3D reset_control_assert(rzg2l_gpt->rst_s); + if (ret) + goto fail_clk; + + ret =3D reset_control_assert(rzg2l_gpt->rst); + if (ret) + goto fail_reset_s; + return 0; + +fail_reset_s: + reset_control_deassert(rzg2l_gpt->rst_s); +fail_clk: + clk_prepare_enable(rzg2l_gpt->bus_clk); + clk_prepare_enable(rzg2l_gpt->clk); + return ret; +} + +static int rzg2l_gpt_resume(struct device *dev) +{ + struct pwm_chip *chip =3D dev_get_drvdata(dev); + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + unsigned int i; + int ret; + + ret =3D reset_control_deassert(rzg2l_gpt->rst); + if (ret) + return ret; + + ret =3D reset_control_deassert(rzg2l_gpt->rst_s); + if (ret) + goto fail_reset; + + ret =3D clk_prepare_enable(rzg2l_gpt->bus_clk); + if (ret) + goto fail_reset_all; + + ret =3D clk_prepare_enable(rzg2l_gpt->clk); + if (ret) + goto fail_bus_clk; + + for (i =3D 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!rzg2l_gpt->channel_enable_count[i]) + continue; + + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(i), rzg2l_gpt->hw_cache[i].gtpr); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(i, 0), rzg2l_gpt->hw_cache[i].gtc= cr[0]); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(i, 1), rzg2l_gpt->hw_cache[i].gtc= cr[1]); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCR(i), rzg2l_gpt->hw_cache[i].gtcr); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTIOR(i), rzg2l_gpt->hw_cache[i].gtior); + } + + return 0; + +fail_bus_clk: + clk_disable_unprepare(rzg2l_gpt->bus_clk); +fail_reset_all: + reset_control_assert(rzg2l_gpt->rst_s); +fail_reset: + reset_control_assert(rzg2l_gpt->rst); + return ret; } =20 static const struct rzg2l_gpt_info rzg3e_data =3D { @@ -548,10 +645,13 @@ static const struct of_device_id rzg2l_gpt_of_table[]= =3D { }; MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table); =20 +static DEFINE_SIMPLE_DEV_PM_OPS(rzg2l_gpt_pm_ops, rzg2l_gpt_suspend, rzg2l= _gpt_resume); + static struct platform_driver rzg2l_gpt_driver =3D { .driver =3D { .name =3D "pwm-rzg2l-gpt", .of_match_table =3D rzg2l_gpt_of_table, + .pm =3D pm_sleep_ptr(&rzg2l_gpt_pm_ops), }, .probe =3D rzg2l_gpt_probe, }; --=20 2.43.0