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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b412deddsm11547484a12.31.2025.12.08.07.21.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Dec 2025 07:21:36 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v4 1/9] dt-bindings: pwm: Document RZ/G3E GPT support Date: Mon, 8 Dec 2025 15:21:18 +0000 Message-ID: <20251208152133.269316-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> References: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Document support for the GPT found on the Renesas RZ/G3E (R9A09G047) SoC. The GPT is a 32-bit timer with 16 hardware channels (GPT0: 8 channel and GPT1: 8channels). The hardware supports simultaneous control of all channels. PWM waveforms can be generated by controlling the up-counter, downcounter, or up- and down-counter. Reviewed-by: Rob Herring (Arm) Signed-off-by: Biju Das --- v3->v4: * No change. v2->v3: * Added Rb tag from Rob. v1->v2: * Created separate document for RZ/G3E GPT. * Updated commit header and description. --- .../bindings/pwm/renesas,rzg3e-gpt.yaml | 323 ++++++++++++++++++ 1 file changed, 323 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt= .yaml diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml b= /Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml new file mode 100644 index 000000000000..cb4ffab5f47f --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml @@ -0,0 +1,323 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/renesas,rzg3e-gpt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3E General PWM Timer (GPT) + +maintainers: + - Biju Das + +description: | + RZ/G3E General PWM Timer (GPT) composed of 16 channels with 32-bit + timer. It supports the following functions + * 32 bits x 16 channels. + * Up-counting or down-counting (saw waves) or up/down-counting + (triangle waves) for each counter. + * Clock sources independently selectable for each channel. + * Four I/O pins per channel. + * Two output compare/input capture registers per channel. + * For the two output compare/input capture registers of each channel, + four registers are provided as buffer registers and are capable of + operating as comparison registers when buffering is not in use. + * In output compare operation, buffer switching can be at crests or + troughs, enabling the generation of laterally asymmetric PWM waveforms. + * Registers for setting up frame cycles in each channel (with capability + for generating interrupts at overflow or underflow) + * Generation of dead times in PWM operation. + * Synchronous starting, stopping and clearing counters for arbitrary + channels. + * Count start, count stop, count clear, up-count, down-count, or input + capture operation in response to a maximum of 8 ELC events. + * Count start, count stop, count clear, up-count, down-count, or input + capture operation in response to the status of two input pins. + * Starting, clearing, stopping and up/down counters in response to a + maximum of four external triggers. + * Output pin disable function by detected short-circuits between output + pins. + * A/D converter start triggers can be generated. + * Compare match A to F event and overflow/underflow event can be output + to the ELC. + * Enables the noise filter for input capture. + * Logical operation between the channel output. + +properties: + compatible: + items: + - const: renesas,r9a09g047-gpt # RZ/G3E + + reg: + maxItems: 1 + + '#pwm-cells': + const: 3 + + interrupts: + items: + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.0 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.0 + - description: Compare match with the GTCCRC for channel GPT{0,1}.0 + - description: Compare match with the GTCCRD for channel GPT{0,1}.0 + - description: Compare match with the GTCCRE for channel GPT{0,1}.0 + - description: Compare match with the GTCCRF for channel GPT{0,1}.0 + - description: A and B both high interrupt for channel GPT{0,1}.0 + - description: A and B both low interrupt for channel GPT{0,1}.0 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.1 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.1 + - description: Compare match with the GTCCRC for channel GPT{0,1}.1 + - description: Compare match with the GTCCRD for channel GPT{0,1}.1 + - description: Compare match with the GTCCRE for channel GPT{0,1}.1 + - description: Compare match with the GTCCRF for channel GPT{0,1}.1 + - description: A and B both high interrupt for channel GPT{0,1}.1 + - description: A and B both low interrupt for channel GPT{0,1}.1 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.2 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.2 + - description: Compare match with the GTCCRC for channel GPT{0,1}.2 + - description: Compare match with the GTCCRD for channel GPT{0,1}.2 + - description: Compare match with the GTCCRE for channel GPT{0,1}.2 + - description: Compare match with the GTCCRF for channel GPT{0,1}.2 + - description: A and B both high interrupt for channel GPT{0,1}.2 + - description: A and B both low interrupt for channel GPT{0,1}.2 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.3 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.3 + - description: Compare match with the GTCCRC for channel GPT{0,1}.3 + - description: Compare match with the GTCCRD for channel GPT{0,1}.3 + - description: Compare match with the GTCCRE for channel GPT{0,1}.3 + - description: Compare match with the GTCCRF for channel GPT{0,1}.3 + - description: A and B both high interrupt for channel GPT{0,1}.3 + - description: A and B both low interrupt for channel GPT{0,1}.3 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.4 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.4 + - description: Compare match with the GTCCRC for channel GPT{0,1}.4 + - description: Compare match with the GTCCRD for channel GPT{0,1}.4 + - description: Compare match with the GTCCRE for channel GPT{0,1}.4 + - description: Compare match with the GTCCRF for channel GPT{0,1}.4 + - description: A and B both high interrupt for channel GPT{0,1}.4 + - description: A and B both low interrupt for channel GPT{0,1}.4 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.5 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.5 + - description: Compare match with the GTCCRC for channel GPT{0,1}.5 + - description: Compare match with the GTCCRD for channel GPT{0,1}.5 + - description: Compare match with the GTCCRE for channel GPT{0,1}.5 + - description: Compare match with the GTCCRF for channel GPT{0,1}.5 + - description: A and B both high interrupt for channel GPT{0,1}.5 + - description: A and B both low interrupt for channel GPT{0,1}.5 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.6 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.6 + - description: Compare match with the GTCCRC for channel GPT{0,1}.6 + - description: Compare match with the GTCCRD for channel GPT{0,1}.6 + - description: Compare match with the GTCCRE for channel GPT{0,1}.6 + - description: Compare match with the GTCCRF for channel GPT{0,1}.6 + - description: A and B both high interrupt for channel GPT{0,1}.6 + - description: A and B both low interrupt for channel GPT{0,1}.6 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.7 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.7 + - description: Compare match with the GTCCRC for channel GPT{0,1}.7 + - description: Compare match with the GTCCRD for channel GPT{0,1}.7 + - description: Compare match with the GTCCRE for channel GPT{0,1}.7 + - description: Compare match with the GTCCRF for channel GPT{0,1}.7 + - description: A and B both high interrupt for channel GPT{0,1}.7 + - description: A and B both low interrupt for channel GPT{0,1}.7 + + interrupt-names: + items: + - const: gtcia0 + - const: gtcib0 + - const: gtcic0 + - const: gtcid0 + - const: gtcie0 + - const: gtcif0 + - const: gtcih0 + - const: gtcil0 + - const: gtcia1 + - const: gtcib1 + - const: gtcic1 + - const: gtcid1 + - const: gtcie1 + - const: gtcif1 + - const: gtcih1 + - const: gtcil1 + - const: gtcia2 + - const: gtcib2 + - const: gtcic2 + - const: gtcid2 + - const: gtcie2 + - const: gtcif2 + - const: gtcih2 + - const: gtcil2 + - const: gtcia3 + - const: gtcib3 + - const: gtcic3 + - const: gtcid3 + - const: gtcie3 + - const: gtcif3 + - const: gtcih3 + - const: gtcil3 + - const: gtcia4 + - const: gtcib4 + - const: gtcic4 + - const: gtcid4 + - const: gtcie4 + - const: gtcif4 + - const: gtcih4 + - const: gtcil4 + - const: gtcia5 + - const: gtcib5 + - const: gtcic5 + - const: gtcid5 + - const: gtcie5 + - const: gtcif5 + - const: gtcih5 + - const: gtcil5 + - const: gtcia6 + - const: gtcib6 + - const: gtcic6 + - const: gtcid6 + - const: gtcie6 + - const: gtcif6 + - const: gtcih6 + - const: gtcil6 + - const: gtcia7 + - const: gtcib7 + - const: gtcic7 + - const: gtcid7 + - const: gtcie7 + - const: gtcif7 + - const: gtcih7 + - const: gtcil7 + + clocks: + items: + - description: Core clock (PCLKD) + - description: Bus clock (PCLKA) + + clock-names: + items: + - const: core + - const: bus + + power-domains: + maxItems: 1 + + resets: + items: + - description: Reset for bus clock (PCLKA/PCLKD) + - description: Reset for core clock (PCLKD) + + reset-names: + items: + - const: rst_p + - const: rst_s + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + - reset-names + +allOf: + - $ref: pwm.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + + pwm@13010000 { + compatible =3D "renesas,r9a09g047-gpt"; + reg =3D <0x13010000 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "gtcia0", "gtcib0", "gtcic0", "gtcid0", + "gtcie0", "gtcif0", "gtcih0", "gtcil0", + "gtcia1", "gtcib1", "gtcic1", "gtcid1", + "gtcie1", "gtcif1", "gtcih1", "gtcil1", + "gtcia2", "gtcib2", "gtcic2", "gtcid2", + "gtcie2", "gtcif2", "gtcih2", "gtcil2", + "gtcia3", "gtcib3", "gtcic3", "gtcid3", + "gtcie3", "gtcif3", "gtcih3", "gtcil3", + "gtcia4", "gtcib4", "gtcic4", "gtcid4", + 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b412deddsm11547484a12.31.2025.12.08.07.21.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Dec 2025 07:21:37 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v4 2/9] pwm: rzg2l-gpt: Implementation of the waveform callbacks Date: Mon, 8 Dec 2025 15:21:19 +0000 Message-ID: <20251208152133.269316-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> References: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Convert the rzg2l-gpt driver to use the new callbacks for hardware programming. Signed-off-by: Biju Das --- v3->v4: * Updated rzg2l_gpt_is_ch_enabled() fit into 80-character limit for consistency with other functions. v2->v3: * Prepared as a series. * Created separate patch for fix for reinitialization of the cache variable in disable(). * .round_waveform_tohw() do not fail if the requested period is too small but use the smallest possible value. * Added lock in rzg2l_gpt_read_waveform(). * wfhw is reinitialized in rzg2l_gpt_read_waveform if channel is disabled * Optimizated rzg2l_gpt_is_ch_enabled() to avoid redundant reads to=20 RZG2L_GTCR(ch). * .write_waveform() returns error incase of invalid period for second channel. v1->v2: * Dropped modifing hardware from .round_waveform_tohw() callback. v1: * https://lore.kernel.org/all/20250805065032.193766-1-biju.das.jz@bp.renes= as.com/ --- drivers/pwm/pwm-rzg2l-gpt.c | 192 ++++++++++++++++++++++-------------- 1 file changed, 118 insertions(+), 74 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 4856af080e8e..2f424a7b05cc 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -86,6 +86,13 @@ struct rzg2l_gpt_chip { u32 channel_enable_count[RZG2L_MAX_HW_CHANNELS]; }; =20 +/* This represents a hardware configuration for one channel */ +struct rzg2l_gpt_waveform { + u32 gtpr; + u32 gtccr; + u8 prescale; +}; + static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *ch= ip) { return pwmchip_get_drvdata(chip); @@ -153,7 +160,8 @@ static void rzg2l_gpt_free(struct pwm_chip *chip, struc= t pwm_device *pwm) rzg2l_gpt->channel_request_count[ch]--; } =20 -static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 h= wpwm) +static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 h= wpwm, + u32 *gtcr) { u8 ch =3D RZG2L_GET_CH(hwpwm); u32 val; @@ -162,6 +170,9 @@ static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_ch= ip *rzg2l_gpt, u8 hwpwm) if (!(val & RZG2L_GTCR_CST)) return false; =20 + if (gtcr) + *gtcr =3D val; + val =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTIOR(ch)); =20 return val & RZG2L_GTIOR_OxE(rzg2l_gpt_subchannel(hwpwm)); @@ -220,54 +231,38 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct = rzg2l_gpt_chip *rzg2l_gpt, return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz); } =20 -static int rzg2l_gpt_get_state(struct pwm_chip *chip, struct pwm_device *p= wm, - struct pwm_state *state) -{ - struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); - - state->enabled =3D rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm); - if (state->enabled) { - u32 sub_ch =3D rzg2l_gpt_subchannel(pwm->hwpwm); - u32 ch =3D RZG2L_GET_CH(pwm->hwpwm); - u8 prescale; - u32 val; - - val =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch)); - prescale =3D FIELD_GET(RZG2L_GTCR_TPCS, val); - - val =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch)); - state->period =3D rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val, pre= scale); - - val =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch)); - state->duty_cycle =3D rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val,= prescale); - if (state->duty_cycle > state->period) - state->duty_cycle =3D state->period; - } - - state->polarity =3D PWM_POLARITY_NORMAL; - - return 0; -} - static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 presc= ale) { return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * pres= cale)), U32_MAX); } =20 -/* Caller holds the lock while calling rzg2l_gpt_config() */ -static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm, - const struct pwm_state *state) +static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip, + struct pwm_device *pwm, + const struct pwm_waveform *wf, + void *_wfhw) + { struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); - u8 sub_ch =3D rzg2l_gpt_subchannel(pwm->hwpwm); + struct rzg2l_gpt_waveform *wfhw =3D _wfhw; + bool is_small_second_period =3D false; u8 ch =3D RZG2L_GET_CH(pwm->hwpwm); u64 period_ticks, duty_ticks; unsigned long pv, dc; - u8 prescale; + + guard(mutex)(&rzg2l_gpt->lock); + if (wf->period_length_ns =3D=3D 0) { + *wfhw =3D (struct rzg2l_gpt_waveform){ + .gtpr =3D 0, + .gtccr =3D 0, + .prescale =3D 0, + }; + + return 0; + } =20 /* Limit period/duty cycle to max value supported by the HW */ - period_ticks =3D mul_u64_u64_div_u64(state->period, rzg2l_gpt->rate_khz, = USEC_PER_SEC); + period_ticks =3D mul_u64_u64_div_u64(wf->period_length_ns, rzg2l_gpt->rat= e_khz, USEC_PER_SEC); if (period_ticks > RZG2L_MAX_TICKS) period_ticks =3D RZG2L_MAX_TICKS; /* @@ -278,21 +273,25 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, if (rzg2l_gpt->channel_request_count[ch] > 1) { u8 sibling_ch =3D rzg2l_gpt_sibling(pwm->hwpwm); =20 - if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, sibling_ch)) { + if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, sibling_ch, NULL)) { if (period_ticks < rzg2l_gpt->period_ticks[ch]) - return -EBUSY; + is_small_second_period =3D true; =20 period_ticks =3D rzg2l_gpt->period_ticks[ch]; } } =20 - prescale =3D rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks); - pv =3D rzg2l_gpt_calculate_pv_or_dc(period_ticks, prescale); + wfhw->prescale =3D rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks); + pv =3D rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale); + wfhw->gtpr =3D pv; + if (is_small_second_period) + return 1; =20 - duty_ticks =3D mul_u64_u64_div_u64(state->duty_cycle, rzg2l_gpt->rate_khz= , USEC_PER_SEC); + duty_ticks =3D mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_kh= z, USEC_PER_SEC); if (duty_ticks > period_ticks) duty_ticks =3D period_ticks; - dc =3D rzg2l_gpt_calculate_pv_or_dc(duty_ticks, prescale); + dc =3D rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale); + wfhw->gtccr =3D dc; =20 /* * GPT counter is shared by multiple channels, we cache the period ticks @@ -301,6 +300,61 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, str= uct pwm_device *pwm, */ rzg2l_gpt->period_ticks[ch] =3D period_ticks; =20 + return 0; +} + +static int rzg2l_gpt_round_waveform_fromhw(struct pwm_chip *chip, + struct pwm_device *pwm, + const void *_wfhw, + struct pwm_waveform *wf) +{ + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + const struct rzg2l_gpt_waveform *wfhw =3D _wfhw; + + wf->period_length_ns =3D rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, wf= hw->gtpr, + wfhw->prescale); + wf->duty_length_ns =3D rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, wfhw= ->gtccr, + wfhw->prescale); + wf->duty_offset_ns =3D 0; + + return 0; +} + +static int rzg2l_gpt_read_waveform(struct pwm_chip *chip, + struct pwm_device *pwm, + void *_wfhw) +{ + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + struct rzg2l_gpt_waveform *wfhw =3D _wfhw; + u32 sub_ch =3D rzg2l_gpt_subchannel(pwm->hwpwm); + u32 ch =3D RZG2L_GET_CH(pwm->hwpwm); + u32 gtcr; + + guard(mutex)(&rzg2l_gpt->lock); + if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, >cr)) { + wfhw->prescale =3D FIELD_GET(RZG2L_GTCR_TPCS, gtcr); + wfhw->gtpr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch)); + wfhw->gtccr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch)); + if (wfhw->gtccr > wfhw->gtpr) + wfhw->gtccr =3D wfhw->gtpr; + } else { + *wfhw =3D (struct rzg2l_gpt_waveform) { }; + } + + return 0; +} + +static int rzg2l_gpt_write_waveform(struct pwm_chip *chip, + struct pwm_device *pwm, + const void *_wfhw) +{ + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + const struct rzg2l_gpt_waveform *wfhw =3D _wfhw; + u8 sub_ch =3D rzg2l_gpt_subchannel(pwm->hwpwm); + u8 ch =3D RZG2L_GET_CH(pwm->hwpwm); + u32 gptr; + + guard(mutex)(&rzg2l_gpt->lock); /* * Counter must be stopped before modifying mode, prescaler, timer * counter and buffer enable registers. These registers are shared @@ -319,14 +373,20 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, =20 /* Select count clock */ rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS, - FIELD_PREP(RZG2L_GTCR_TPCS, prescale)); + FIELD_PREP(RZG2L_GTCR_TPCS, wfhw->prescale)); =20 /* Set period */ - rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), pv); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), wfhw->gtpr); + } else { + if (wfhw->gtpr) { + gptr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch)); + if (wfhw->gtpr < gptr) + return -EBUSY; + } } =20 /* Set duty cycle */ - rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch), dc); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch), wfhw->gtccr); =20 if (rzg2l_gpt->channel_enable_count[ch] <=3D 1) { /* Set initial value for counter */ @@ -335,44 +395,28 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, /* Set no buffer operation */ rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTBER(ch), 0); =20 - /* Restart the counter after updating the registers */ - rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), - RZG2L_GTCR_CST, RZG2L_GTCR_CST); - } - - return 0; -} - -static int rzg2l_gpt_apply(struct pwm_chip *chip, struct pwm_device *pwm, - const struct pwm_state *state) -{ - struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); - bool enabled =3D pwm->state.enabled; - int ret; - - if (state->polarity !=3D PWM_POLARITY_NORMAL) - return -EINVAL; - - guard(mutex)(&rzg2l_gpt->lock); - if (!state->enabled) { - if (enabled) - rzg2l_gpt_disable(rzg2l_gpt, pwm); - - return 0; + if (wfhw->gtpr) + /* Restart the counter after updating the registers */ + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), + RZG2L_GTCR_CST, RZG2L_GTCR_CST); } =20 - ret =3D rzg2l_gpt_config(chip, pwm, state); - if (!ret && !enabled) + if (wfhw->gtpr && !rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, NULL)) rzg2l_gpt_enable(rzg2l_gpt, pwm); + else if (!wfhw->gtpr && rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, NU= LL)) + rzg2l_gpt_disable(rzg2l_gpt, pwm); =20 - return ret; + return 0; } =20 static const struct pwm_ops rzg2l_gpt_ops =3D { .request =3D rzg2l_gpt_request, .free =3D rzg2l_gpt_free, - .get_state =3D rzg2l_gpt_get_state, - .apply =3D rzg2l_gpt_apply, + .sizeof_wfhw =3D sizeof(struct rzg2l_gpt_waveform), + .round_waveform_tohw =3D rzg2l_gpt_round_waveform_tohw, + .round_waveform_fromhw =3D rzg2l_gpt_round_waveform_fromhw, + .read_waveform =3D rzg2l_gpt_read_waveform, + .write_waveform =3D rzg2l_gpt_write_waveform, }; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b412deddsm11547484a12.31.2025.12.08.07.21.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Dec 2025 07:21:37 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v4 3/9] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip Date: Mon, 8 Dec 2025 15:21:20 +0000 Message-ID: <20251208152133.269316-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> References: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G3E GPT IP is similar to the one found on RZ/G2L GPT, but there are some differences. The field width of prescalar on RZ/G3E is 4 whereas on RZ/G2L it is 3. Add rzg2l_gpt_info variable to handle this differences. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v3->v4: * Dropped field_{get,prep} as mainline now support it. * Updated commit description. * Retained RZG2L_GTCR_TPCS bit definitons * Replaced gtcr_tpcs_mask->gtcr_tpcs v2->v3: * No change. v1->v2: * Collected tag. --- drivers/pwm/pwm-rzg2l-gpt.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 2f424a7b05cc..5a8e5a3eb1b1 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -77,9 +77,14 @@ #define RZG2L_MAX_SCALE_FACTOR 1024 #define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR) =20 +struct rzg2l_gpt_info { + u32 gtcr_tpcs; +}; + struct rzg2l_gpt_chip { void __iomem *mmio; struct mutex lock; /* lock to protect shared channel resources */ + const struct rzg2l_gpt_info *info; unsigned long rate_khz; u32 period_ticks[RZG2L_MAX_HW_CHANNELS]; u32 channel_request_count[RZG2L_MAX_HW_CHANNELS]; @@ -332,7 +337,7 @@ static int rzg2l_gpt_read_waveform(struct pwm_chip *chi= p, =20 guard(mutex)(&rzg2l_gpt->lock); if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, >cr)) { - wfhw->prescale =3D FIELD_GET(RZG2L_GTCR_TPCS, gtcr); + wfhw->prescale =3D field_get(rzg2l_gpt->info->gtcr_tpcs, gtcr); wfhw->gtpr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch)); wfhw->gtccr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch)); if (wfhw->gtccr > wfhw->gtpr) @@ -372,8 +377,8 @@ static int rzg2l_gpt_write_waveform(struct pwm_chip *ch= ip, rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTUDDTYC(ch), RZG2L_GTUDDTYC_UP_COUNTIN= G); =20 /* Select count clock */ - rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS, - FIELD_PREP(RZG2L_GTCR_TPCS, wfhw->prescale)); + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), rzg2l_gpt->info->gtcr_tpcs, + field_prep(rzg2l_gpt->info->gtcr_tpcs, wfhw->prescale)); =20 /* Set period */ rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), wfhw->gtpr); @@ -438,6 +443,8 @@ static int rzg2l_gpt_probe(struct platform_device *pdev) if (IS_ERR(rzg2l_gpt->mmio)) return PTR_ERR(rzg2l_gpt->mmio); =20 + rzg2l_gpt->info =3D of_device_get_match_data(dev); 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b412deddsm11547484a12.31.2025.12.08.07.21.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Dec 2025 07:21:38 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v4 4/9] pwm: rzg2l-gpt: Add prescale_mult variable to struct rzg2l_gpt_info Date: Mon, 8 Dec 2025 15:21:21 +0000 Message-ID: <20251208152133.269316-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> References: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G3E GPT IP has prescale factor power of 2 where as that of RZ/G2L is 4. Add prescale_mult variable to struct rzg2l_gpt_info for handling this difference. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v3->v4: * Updated commit header and description * Renamed prescale_pow_of_two_mult_factor->prescale_mult v2->v3: * No change. v1->v2: * Collected tag. --- drivers/pwm/pwm-rzg2l-gpt.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 5a8e5a3eb1b1..47324c9fa6dd 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -79,6 +79,7 @@ =20 struct rzg2l_gpt_info { u32 gtcr_tpcs; + u8 prescale_mult; }; =20 struct rzg2l_gpt_chip { @@ -221,6 +222,7 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rz= g2l_gpt, static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l= _gpt, u32 val, u8 prescale) { + const struct rzg2l_gpt_info *info =3D rzg2l_gpt->info; u64 tmp; =20 /* @@ -230,15 +232,18 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct = rzg2l_gpt_chip *rzg2l_gpt, * < 2^32 * 2^10 * 2^20 * =3D 2^62 */ - tmp =3D (u64)val << (2 * prescale); + tmp =3D (u64)val << (info->prescale_mult * prescale); tmp *=3D USEC_PER_SEC; =20 return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz); } =20 -static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 presc= ale) +static u32 rzg2l_gpt_calculate_pv_or_dc(const struct rzg2l_gpt_info *info, + u64 period_or_duty_cycle, u8 prescale) { - return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * pres= cale)), + return min_t(u64, + DIV_ROUND_DOWN_ULL(period_or_duty_cycle, + 1 << (info->prescale_mult * prescale)), U32_MAX); } =20 @@ -249,6 +254,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chi= p *chip, =20 { struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + const struct rzg2l_gpt_info *info =3D rzg2l_gpt->info; struct rzg2l_gpt_waveform *wfhw =3D _wfhw; bool is_small_second_period =3D false; u8 ch =3D RZG2L_GET_CH(pwm->hwpwm); @@ -287,7 +293,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chi= p *chip, } =20 wfhw->prescale =3D rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks); - pv =3D rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale); + pv =3D rzg2l_gpt_calculate_pv_or_dc(info, period_ticks, wfhw->prescale); wfhw->gtpr =3D pv; if (is_small_second_period) return 1; @@ -295,7 +301,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chi= p *chip, duty_ticks =3D mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_kh= z, USEC_PER_SEC); if (duty_ticks > period_ticks) duty_ticks =3D period_ticks; - dc =3D rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale); + dc =3D rzg2l_gpt_calculate_pv_or_dc(info, duty_ticks, wfhw->prescale); wfhw->gtccr =3D dc; =20 /* @@ -489,6 +495,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev) =20 static const struct rzg2l_gpt_info rzg2l_data =3D { .gtcr_tpcs =3D RZG2L_GTCR_TPCS, + .prescale_mult =3D 2, }; =20 static const struct of_device_id rzg2l_gpt_of_table[] =3D { --=20 2.43.0 From nobody Tue Dec 16 13:37:31 2025 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC8072DC350 for ; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b412deddsm11547484a12.31.2025.12.08.07.21.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Dec 2025 07:21:39 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v4 5/9] pwm: rzg2l-gpt: Add calculate_prescale() callback to struct rzg2l_gpt_info Date: Mon, 8 Dec 2025 15:21:22 +0000 Message-ID: <20251208152133.269316-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> References: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G2L GPT the prescale factors are continuous power of 4 whereas on RZ/G3E it is power of 2 but discontinuous. Add calculate_prescale() callback to struct rzg2l_gpt_info for handling this difference. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v3->v4: * No change. v2->v3: * No change. v1->v2: * Collected tag. --- drivers/pwm/pwm-rzg2l-gpt.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 47324c9fa6dd..791900f6de3d 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -78,6 +78,7 @@ #define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR) =20 struct rzg2l_gpt_info { + u8 (*calculate_prescale)(u64 period); u32 gtcr_tpcs; u8 prescale_mult; }; @@ -131,8 +132,7 @@ static void rzg2l_gpt_modify(struct rzg2l_gpt_chip *rzg= 2l_gpt, u32 reg, u32 clr, (rzg2l_gpt_read(rzg2l_gpt, reg) & ~clr) | set); } =20 -static u8 rzg2l_gpt_calculate_prescale(struct rzg2l_gpt_chip *rzg2l_gpt, - u64 period_ticks) +static u8 rzg2l_gpt_calculate_prescale(u64 period_ticks) { u32 prescaled_period_ticks; u8 prescale; @@ -292,7 +292,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chi= p *chip, } } =20 - wfhw->prescale =3D rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks); 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b412deddsm11547484a12.31.2025.12.08.07.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Dec 2025 07:21:39 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v4 6/9] pwm: rzg2l-gpt: Add RZ/G3E support Date: Mon, 8 Dec 2025 15:21:23 +0000 Message-ID: <20251208152133.269316-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> References: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add RZ/G3E GPT support. It has multiple clocks and resets compared to RZ/G2L. Also prescale field width and factor for calculating prescale are different. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v3->v4: * Added RZG3E_GTCR_TPCS bit definition for RZ/G3E and added to rzg3e_data. v2->v3: * No change. v1->v2: * Added link to hardware manual * Updated limitation section * Collected tag=20 --- drivers/pwm/pwm-rzg2l-gpt.c | 47 +++++++++++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 791900f6de3d..79ee59271d24 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -6,15 +6,21 @@ * * Hardware manual for this IP can be found here * https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-use= rs-manual-hardware-0?language=3Den + * https://www.renesas.com/en/document/mah/rzg3e-group-users-manual-hardwa= re * * Limitations: * - Counter must be stopped before modifying Mode and Prescaler. * - When PWM is disabled, the output is driven to inactive. * - While the hardware supports both polarities, the driver (for now) * only handles normal polarity. - * - General PWM Timer (GPT) has 8 HW channels for PWM operations and - * each HW channel have 2 IOs. + * - For RZ/G2L, the General PWM Timer (GPT) has 8 HW channels for PWM + operations and each HW channel have 2 IOs (GTIOCn{A, B}). * - Each IO is modelled as an independent PWM channel. + * - For RZ/G3E, the General PWM Timer (GPT) has 16 HW channels for PWM + operations (GPT0: 8 channels, GPT1: 8 Channels) and each HW channel + have 4 IOs (GTIOCn{A,AN,B,BN}). The 2 extra IOs GTIOCnAN and GTIOCnBN + in RZ/G3E are anti-phase signals of GTIOCnA and GTIOCnB. The + anti-phase signals of RZ/G3E are not modelled as PWM channel. * - When both channels are used, disabling the channel on one stops the * other. * - When both channels are used, the period of both IOs in the HW channel @@ -47,6 +53,7 @@ #define RZG2L_GTCR_CST BIT(0) #define RZG2L_GTCR_MD GENMASK(18, 16) #define RZG2L_GTCR_TPCS GENMASK(26, 24) +#define RZG3E_GTCR_TPCS GENMASK(26, 23) =20 #define RZG2L_GTCR_MD_SAW_WAVE_PWM_MODE FIELD_PREP(RZG2L_GTCR_MD, 0) =20 @@ -146,6 +153,27 @@ static u8 rzg2l_gpt_calculate_prescale(u64 period_tick= s) return prescale; } =20 +static u8 rzg3e_gpt_calculate_prescale(u64 period_ticks) +{ + u32 prescaled_period_ticks; + u8 prescale; + + prescaled_period_ticks =3D period_ticks >> 32; + if (prescaled_period_ticks >=3D 64 && prescaled_period_ticks < 256) { + prescale =3D 6; + } else if (prescaled_period_ticks >=3D 256 && prescaled_period_ticks < 10= 24) { + prescale =3D 8; + } else if (prescaled_period_ticks >=3D 1024) { + prescale =3D 10; + } else { + prescale =3D fls(prescaled_period_ticks); + if (prescale > 1) + prescale -=3D 1; + } + + return prescale; +} + static int rzg2l_gpt_request(struct pwm_chip *chip, struct pwm_device *pwm) { struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); @@ -455,6 +483,14 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) if (IS_ERR(rstc)) return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\= n"); =20 + rstc =3D devm_reset_control_get_optional_exclusive_deasserted(dev, "rst_s= "); + if (IS_ERR(rstc)) + return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert rst_s reset\n"= ); + + clk =3D devm_clk_get_optional_enabled(dev, "bus"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "Cannot get bus clock\n"); + clk =3D devm_clk_get_enabled(dev, NULL); if (IS_ERR(clk)) return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n"); @@ -493,6 +529,12 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) return 0; } =20 +static const struct rzg2l_gpt_info rzg3e_data =3D { + .calculate_prescale =3D rzg3e_gpt_calculate_prescale, + .gtcr_tpcs =3D RZG3E_GTCR_TPCS, + .prescale_mult =3D 1, +}; + static const struct rzg2l_gpt_info rzg2l_data =3D { .calculate_prescale =3D rzg2l_gpt_calculate_prescale, .gtcr_tpcs =3D RZG2L_GTCR_TPCS, @@ -500,6 +542,7 @@ static const struct rzg2l_gpt_info rzg2l_data =3D { }; =20 static const struct of_device_id rzg2l_gpt_of_table[] =3D { + { .compatible =3D "renesas,r9a09g047-gpt", .data =3D &rzg3e_data }, { .compatible =3D "renesas,rzg2l-gpt", .data =3D &rzg2l_data }, { /* Sentinel */ } }; --=20 2.43.0 From nobody Tue Dec 16 13:37:31 2025 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18E662D8385 for ; Mon, 8 Dec 2025 15:21:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765207306; cv=none; b=ZR40uIZw+Q5ImBu9HdDKIEn+Ff6w1qin6JiPsED2n3bqu56e+3NDE94Tx2JGNSrqH6VuWOA7CBh6jw+mvl+fCH+hT+Z5LyR0mRUOB9/mCwk/H8xQ5Vs/AJF3em9PneNi7F8mDdKnxXevzrrZrnydDl/as8BragGqlTQJn+gTM6k= ARC-Message-Signature: i=1; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b412deddsm11547484a12.31.2025.12.08.07.21.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Dec 2025 07:21:40 -0800 (PST) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Philipp Zabel Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 7/9] pwm: rzg2l-gpt: Add suspend/resume support Date: Mon, 8 Dec 2025 15:21:24 +0000 Message-ID: <20251208152133.269316-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> References: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das On RZ/G3E using PSCI, s2ram powers down the SoC. Add suspend/resume callbacks for save/restore GPT context. Signed-off-by: Biju Das --- v3->v4: * Added error checks on suspend() and device set to operational state on failure(). v3: * New patch. --- drivers/pwm/pwm-rzg2l-gpt.c | 132 +++++++++++++++++++++++++++++++----- 1 file changed, 116 insertions(+), 16 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 79ee59271d24..4eac35390c60 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -90,14 +90,26 @@ struct rzg2l_gpt_info { u8 prescale_mult; }; =20 +struct rzg2l_gpt_cache { + u32 gtpr; + u32 gtccr[2]; + u32 gtcr; + u32 gtior; +}; + struct rzg2l_gpt_chip { void __iomem *mmio; struct mutex lock; /* lock to protect shared channel resources */ const struct rzg2l_gpt_info *info; + struct clk *clk; + struct clk *bus_clk; + struct reset_control *rst; + struct reset_control *rst_s; unsigned long rate_khz; u32 period_ticks[RZG2L_MAX_HW_CHANNELS]; u32 channel_request_count[RZG2L_MAX_HW_CHANNELS]; u32 channel_enable_count[RZG2L_MAX_HW_CHANNELS]; + struct rzg2l_gpt_cache hw_cache[RZG2L_MAX_HW_CHANNELS]; }; =20 /* This represents a hardware configuration for one channel */ @@ -462,10 +474,8 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) { struct rzg2l_gpt_chip *rzg2l_gpt; struct device *dev =3D &pdev->dev; - struct reset_control *rstc; struct pwm_chip *chip; unsigned long rate; - struct clk *clk; int ret; =20 chip =3D devm_pwmchip_alloc(dev, RZG2L_MAX_PWM_CHANNELS, sizeof(*rzg2l_gp= t)); @@ -479,27 +489,29 @@ static int rzg2l_gpt_probe(struct platform_device *pd= ev) =20 rzg2l_gpt->info =3D of_device_get_match_data(dev); =20 - rstc =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); - if (IS_ERR(rstc)) - return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\= n"); + rzg2l_gpt->rst =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); + if (IS_ERR(rzg2l_gpt->rst)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->rst), + "Cannot deassert reset control\n"); =20 - rstc =3D devm_reset_control_get_optional_exclusive_deasserted(dev, "rst_s= "); - if (IS_ERR(rstc)) - return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert rst_s reset\n"= ); + rzg2l_gpt->rst_s =3D devm_reset_control_get_optional_exclusive_deasserted= (dev, "rst_s"); + if (IS_ERR(rzg2l_gpt->rst_s)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->rst_s), + "Cannot deassert rst_s reset\n"); =20 - clk =3D devm_clk_get_optional_enabled(dev, "bus"); - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "Cannot get bus clock\n"); + rzg2l_gpt->bus_clk =3D devm_clk_get_optional_enabled(dev, "bus"); + if (IS_ERR(rzg2l_gpt->bus_clk)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->bus_clk), "Cannot get bus c= lock\n"); =20 - clk =3D devm_clk_get_enabled(dev, NULL); - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n"); + rzg2l_gpt->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(rzg2l_gpt->clk)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->clk), "Cannot get clock\n"); =20 - ret =3D devm_clk_rate_exclusive_get(dev, clk); + ret =3D devm_clk_rate_exclusive_get(dev, rzg2l_gpt->clk); if (ret) return ret; =20 - rate =3D clk_get_rate(clk); + rate =3D clk_get_rate(rzg2l_gpt->clk); if (!rate) return dev_err_probe(dev, -EINVAL, "The gpt clk rate is 0"); =20 @@ -526,7 +538,92 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) if (ret) return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); =20 + platform_set_drvdata(pdev, chip); + + return 0; +} + +static int rzg2l_gpt_suspend(struct device *dev) +{ + struct pwm_chip *chip =3D dev_get_drvdata(dev); + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + unsigned int i; + int ret; + + for (i =3D 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!rzg2l_gpt->channel_enable_count[i]) + continue; + + rzg2l_gpt->hw_cache[i].gtpr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(i)); + rzg2l_gpt->hw_cache[i].gtccr[0] =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCC= R(i, 0)); + rzg2l_gpt->hw_cache[i].gtccr[1] =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCC= R(i, 1)); + rzg2l_gpt->hw_cache[i].gtcr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(i)); + rzg2l_gpt->hw_cache[i].gtior =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTIOR(i= )); + } + + clk_disable_unprepare(rzg2l_gpt->clk); + clk_disable_unprepare(rzg2l_gpt->bus_clk); + ret =3D reset_control_assert(rzg2l_gpt->rst_s); + if (ret) + goto fail_clk; + + ret =3D reset_control_assert(rzg2l_gpt->rst); + if (ret) + goto fail_reset_s; + return 0; + +fail_reset_s: + reset_control_deassert(rzg2l_gpt->rst_s); +fail_clk: + clk_prepare_enable(rzg2l_gpt->bus_clk); + clk_prepare_enable(rzg2l_gpt->clk); + return ret; +} + +static int rzg2l_gpt_resume(struct device *dev) +{ + struct pwm_chip *chip =3D dev_get_drvdata(dev); + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + unsigned int i; + int ret; + + ret =3D reset_control_deassert(rzg2l_gpt->rst); + if (ret) + return ret; + + ret =3D reset_control_deassert(rzg2l_gpt->rst_s); + if (ret) + goto fail_reset; + + ret =3D clk_prepare_enable(rzg2l_gpt->bus_clk); + if (ret) + goto fail_reset_all; + + ret =3D clk_prepare_enable(rzg2l_gpt->clk); + if (ret) + goto fail_bus_clk; + + for (i =3D 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!rzg2l_gpt->channel_enable_count[i]) + continue; + + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(i), rzg2l_gpt->hw_cache[i].gtpr); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(i, 0), rzg2l_gpt->hw_cache[i].gtc= cr[0]); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(i, 1), rzg2l_gpt->hw_cache[i].gtc= cr[1]); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCR(i), rzg2l_gpt->hw_cache[i].gtcr); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTIOR(i), rzg2l_gpt->hw_cache[i].gtior); + } + + return 0; + +fail_bus_clk: + clk_disable_unprepare(rzg2l_gpt->bus_clk); +fail_reset_all: + reset_control_assert(rzg2l_gpt->rst_s); +fail_reset: + reset_control_assert(rzg2l_gpt->rst); + return ret; } =20 static const struct rzg2l_gpt_info rzg3e_data =3D { @@ -548,10 +645,13 @@ static const struct of_device_id rzg2l_gpt_of_table[]= =3D { }; MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table); =20 +static DEFINE_SIMPLE_DEV_PM_OPS(rzg2l_gpt_pm_ops, rzg2l_gpt_suspend, rzg2l= _gpt_resume); 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b412deddsm11547484a12.31.2025.12.08.07.21.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Dec 2025 07:21:40 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v4 8/9] arm64: dts: renesas: r9a09g047: Add GPT nodes Date: Mon, 8 Dec 2025 15:21:25 +0000 Message-ID: <20251208152133.269316-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> References: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3E SoC has 2 GPT's. Add GPT nodes to RZ/G3E ("R9A09G047") SoC DTSI. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v3->v4: * Added Rb tag from Geert. v2->v3: * No change. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 184 +++++++++++++++++++++ 1 file changed, 184 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g047.dtsi index d1bf16c6ff6b..d05abafe4b5e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -591,6 +591,190 @@ channel5 { }; }; =20 + gpt0: pwm@13010000 { + compatible =3D "renesas,r9a09g047-gpt"; + reg =3D <0 0x13010000 0 0x10000>; + #pwm-cells =3D <3>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "gtcia0", "gtcib0", "gtcic0", "gtcid0", + "gtcie0", "gtcif0", "gtcih0", "gtcil0", + "gtcia1", "gtcib1", "gtcic1", "gtcid1", + "gtcie1", "gtcif1", "gtcih1", "gtcil1", + "gtcia2", "gtcib2", "gtcic2", "gtcid2", + "gtcie2", "gtcif2", "gtcih2", "gtcil2", + "gtcia3", "gtcib3", "gtcic3", "gtcid3", + "gtcie3", "gtcif3", "gtcih3", "gtcil3", + "gtcia4", "gtcib4", "gtcic4", "gtcid4", + "gtcie4", "gtcif4", "gtcih4", "gtcil4", + "gtcia5", "gtcib5", "gtcic5", "gtcid5", + "gtcie5", "gtcif5", "gtcih5", "gtcil5", + "gtcia6", "gtcib6", "gtcic6", "gtcid6", + "gtcie6", "gtcif6", "gtcih6", "gtcil6", + "gtcia7", "gtcib7", "gtcic7", "gtcid7", + "gtcie7", "gtcif7", "gtcih7", "gtcil7"; + clocks =3D <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>; + clock-names =3D "core", "bus"; + resets =3D <&cpg 0x59>, <&cpg 0x5a>; + reset-names =3D "rst_p", "rst_s"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + gpt1: pwm@13020000 { + compatible =3D "renesas,r9a09g047-gpt"; + reg =3D <0 0x13020000 0 0x10000>; + #pwm-cells =3D <3>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "gtcia0", "gtcib0", "gtcic0", "gtcid0", + "gtcie0", "gtcif0", "gtcih0", "gtcil0", + "gtcia1", "gtcib1", "gtcic1", "gtcid1", + "gtcie1", "gtcif1", "gtcih1", "gtcil1", + "gtcia2", "gtcib2", "gtcic2", "gtcid2", + "gtcie2", "gtcif2", "gtcih2", "gtcil2", + "gtcia3", "gtcib3", "gtcic3", "gtcid3", + "gtcie3", "gtcif3", "gtcih3", "gtcil3", + "gtcia4", "gtcib4", "gtcic4", "gtcid4", + "gtcie4", "gtcif4", "gtcih4", "gtcil4", + "gtcia5", "gtcib5", "gtcic5", "gtcid5", + "gtcie5", "gtcif5", "gtcih5", "gtcil5", + "gtcia6", "gtcib6", "gtcic6", "gtcid6", + "gtcie6", "gtcif6", "gtcih6", "gtcil6", + "gtcia7", "gtcib7", "gtcic7", "gtcid7", + "gtcie7", "gtcif7", "gtcih7", "gtcil7"; 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[86.162.200.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b412deddsm11547484a12.31.2025.12.08.07.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Dec 2025 07:21:41 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v4 9/9] arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board Date: Mon, 8 Dec 2025 15:21:26 +0000 Message-ID: <20251208152133.269316-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> References: <20251208152133.269316-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The GTIOC4{A,B} IOs are available on the carrier board's PMOD1_6A connector. Enable the GPT on the carrier board by adding the GPT pinmux and device node on the board dts file. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v3->v4: * Added SW_GPIO9_CAN1_STB check to gpt0 node. v2->v3: * No change. v1->v2: * Collected tags. --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a09g047e57-smarc.dts index 0fd90d79b020..e4d2902ca4c8 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -84,6 +84,14 @@ &can_transceiver1 { }; #endif =20 +#if (!SW_LCD_EN) && (!SW_GPIO8_CAN0_STB) && (!SW_GPIO9_CAN1_STB) +&gpt0 { + pinctrl-0 =3D <&gpt0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; +#endif + &i2c0 { pinctrl-0 =3D <&i2c0_pins>; pinctrl-names =3D "default"; @@ -125,6 +133,11 @@ can4_pins: can4 { }; }; =20 + gpt0_pins: gpt0 { + pinmux =3D , /* GTIOC4A */ + ; /* GTIOC4B */ + }; + i2c0_pins: i2c0 { pinmux =3D , /* SCL0 */ ; /* SDA0 */ --=20 2.43.0