From nobody Fri Dec 19 13:29:08 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6186624DFF3 for ; Mon, 8 Dec 2025 03:50:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765165854; cv=none; b=H2wm+7srRV96WcurMdj4xHG8sFMWaBbBxaW0p4FtkOB9+f57LLiHvWcmHTBOUqh9D9ONEKjJ/cSGUo6g6nPKA4lWcDR35eUq+nOymCzZ4zo/K4kzDkcTM6Q6H7QLwEPhW4Gy8T2Pn4p1L06nOSNovVP5H80BGuhdkZlQrBYrZjk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765165854; c=relaxed/simple; bh=s7J1/EJglygUlRcA2CA2RR3zp0EAzyaKlV4J61HRDG8=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=ajsKueCkk7ZQWHeiXzZ7BalQhD879/EMX8SeE4inR6RFe3VM3v/tHscW/+IwSv46dePJ32d+6exEtvajUktx2fT/dTQXcWWdYGKttAru4nG4MBZbXjo4SckfgOgIIXlEvnoNyi69T/GWgnhOnujomPVx9HDG9fUDObeF+1zBf0E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com; spf=pass smtp.mailfrom=bytedance.com; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b=JveqQe+4; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bytedance.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b="JveqQe+4" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-29d7b019e0eso44960435ad.2 for ; Sun, 07 Dec 2025 19:50:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1765165853; x=1765770653; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xFr5RgkhvM6EE5Q/RHn3oG8Xllt/H7Gtrl4Nvhbq1ik=; b=JveqQe+4vnnBF9/JE6TGDJebpcfTVkSFSusxozXzEEzKIXzeB2X78bi0GfmBgnSmOn kBhLioroZZxLg6+rUzN8vLL03Bpmx3qmpTYXrL9C1XgetXZXYwOBY1ohjM++0F/8tR8r 6SCGxW2lUeQF5YeyD0SKVSzUv50/+G8hfz5ZYCHTLlwLckrceok7uKXIZkv0E0yMaNir mcGlY0G86dLqRyD3ufuD0EwW3lkG3JyQ/Tmc/JaDqlr38E1XnZV+jz0CEy5/gTNJsypN XugjFk59HHasR44Zft1w14sI1vkhiwcRYcdBCs8B9zcY5Kcu7FCfJYmuZ36E0Mdl30YD MZFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765165853; x=1765770653; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=xFr5RgkhvM6EE5Q/RHn3oG8Xllt/H7Gtrl4Nvhbq1ik=; b=AmK8eQS3rIQEdTmdOgez7Sp67PfQaaPHZ+ZoMrC9u9d5c3JBRyQXbdKRMPaZLERqpZ ax8CqtrY2zTTV/LFwtvtm+MiRuX0HWekW3gO8cIdQ2PxQvFoHm5uakzeQwhmYjrT1Kpv SXClrSVc6lTLxzcgWWKN3a42pc3aGHLY3dJdXel9LCvjx9pzhGSvI+9kmNh8Bs7pp4iv MzPrx/RUbxG+XYW2UVi0zRDJSzYxelkQlnuUAKEeYHrDut8CccUJX2j+X9PpQVP0O3cg 9gFDCWZnGAQ9siLpOUkWzA1NYUP8tna2BGFVwuTYXieBkWh6D5Tpk37wrcmqNJbt8Hmw NFwQ== X-Forwarded-Encrypted: i=1; AJvYcCXKqwAD3Hw2dhXZaiJlOxNz/3rk2L02kZ2VPhMb7VarzMcYrvUI3jVzUPQxhSZOfxV+Qb2egnP2GOmy7Go=@vger.kernel.org X-Gm-Message-State: AOJu0Ywnt3EEDTB4E4fAsy6Jv3u4byCm55H7w0a1EVKDlE+u62NxSrcu ODL+zyNnIMJSQRKfw6vxykgOC0IKujPstQXb6gSHW+wFmR5cBwgRc721tRbeKCD7FIo= X-Gm-Gg: ASbGncu1yeyXl5+dlUa5UTXmrmigu2hOiMnHZ053IF8JpzKZvImnE8ivLqglplhbPI6 zAwUSgj7ESrojgXXtpqbqomcm1TaZFqj5YmMXRK+gtgyNkd9OfZ2VV4hPygKL3lNodhxmPci2c6 wxlR+RGGIjoUo8VxiJMzMkuZJVS1lAKplYF71g1vUnWFW0AakpYFmoPG+P3BpnSEK+LtQ0Ili/Y qU9XV0n05nOogj5YfAiGckq9j9deglpKdCaiuU7cid1MOFR6Tw2xaYrkTothmmFB3L7vjyz0nw0 BIJjhUPDyEZnwdoG2iX9FYA+J2Uph6XMjPZ2Y9IVd7AFQYTFuDXEJI+LcYDPJ9GGGp21kDf710c ypnprGL57XfxROLo0+jDxu/N33pTBw2H4zbKy4UrC2it04Spqo0t+z4JkoDfGAsFokqN7rlXYEX H8DZmwRHZ7Me91mcW71sOUrhb302Gm1pDWJKIHeXsIdFkm X-Google-Smtp-Source: AGHT+IGvReM+D+IE845FajcK0U2ifqJXm74OcYy9I6WIlw3gQeLkhNJjnOwLKfKhujYanWqb2gK1OA== X-Received: by 2002:a17:903:15ce:b0:299:dea1:e791 with SMTP id d9443c01a7336-29df56772d0mr53566285ad.12.1765165852442; Sun, 07 Dec 2025 19:50:52 -0800 (PST) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.240]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29daeae6d96sm108871275ad.102.2025.12.07.19.50.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 07 Dec 2025 19:50:52 -0800 (PST) From: Yunhui Cui To: aou@eecs.berkeley.edu, alex@ghiti.fr, andii@kernel.org, andybnac@gmail.com, apatel@ventanamicro.com, ast@kernel.org, ben.dooks@codethink.co.uk, bjorn@kernel.org, bpf@vger.kernel.org, charlie@rivosinc.com, cl@gentwo.org, conor.dooley@microchip.com, cuiyunhui@bytedance.com, cyrilbur@tenstorrent.com, daniel@iogearbox.net, debug@rivosinc.com, dennis@kernel.org, eddyz87@gmail.com, haoluo@google.com, john.fastabend@gmail.com, jolsa@kernel.org, kpsingh@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux@rasmusvillemoes.dk, martin.lau@linux.dev, palmer@dabbelt.com, pjw@kernel.org, puranjay@kernel.org, pulehui@huawei.com, ruanjinjie@huawei.com, rkrcmar@ventanamicro.com, samuel.holland@sifive.com, sdf@fomichev.me, song@kernel.org, tglx@linutronix.de, tj@kernel.org, thuth@redhat.com, yonghong.song@linux.dev, yury.norov@gmail.com, zong.li@sifive.com Subject: [PATCH v2 3/3] riscv: store percpu offset into thread_info Date: Mon, 8 Dec 2025 11:49:44 +0800 Message-Id: <20251208034944.73113-4-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251208034944.73113-1-cuiyunhui@bytedance.com> References: <20251208034944.73113-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Originally we planned to add a register for the percpu offset, which would speed up percpu variable R/W and reduce access instructions. After discussion [1], it=E2=80=99s now stored in thread_info. [1] https://lists.riscv.org/g/tech-privileged/topic/risc_v_tech_arch_review= /113437553?page=3D2 Signed-off-by: Yunhui Cui --- arch/riscv/include/asm/asm.h | 6 +----- arch/riscv/include/asm/percpu.h | 4 ++++ arch/riscv/include/asm/switch_to.h | 8 ++++++++ arch/riscv/include/asm/thread_info.h | 5 +++-- arch/riscv/kernel/asm-offsets.c | 1 + arch/riscv/kernel/smpboot.c | 7 +++++++ arch/riscv/net/bpf_jit_comp64.c | 9 +-------- 7 files changed, 25 insertions(+), 15 deletions(-) diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h index e9e8ba83e632f..137a49488325e 100644 --- a/arch/riscv/include/asm/asm.h +++ b/arch/riscv/include/asm/asm.h @@ -91,11 +91,7 @@ =20 #ifdef CONFIG_SMP .macro asm_per_cpu dst sym tmp - lw \tmp, TASK_TI_CPU_NUM(tp) - slli \tmp, \tmp, RISCV_LGPTR - la \dst, __per_cpu_offset - add \dst, \dst, \tmp - REG_L \tmp, 0(\dst) + REG_L \tmp, TASK_TI_PCPU_OFFSET(tp) la \dst, \sym add \dst, \dst, \tmp .endm diff --git a/arch/riscv/include/asm/percpu.h b/arch/riscv/include/asm/percp= u.h index b173729926126..18e282dded626 100644 --- a/arch/riscv/include/asm/percpu.h +++ b/arch/riscv/include/asm/percpu.h @@ -7,7 +7,9 @@ =20 #include #include +#include #include +#include =20 #define PERCPU_RW_OPS(sz) \ static inline unsigned long __percpu_read_##sz(void *ptr) \ @@ -233,6 +235,8 @@ _pcp_protect_return(__percpu_add_return_amo_case_64, pc= p, val) ret__; \ }) =20 +#define __my_cpu_offset (((struct thread_info *)current)->pcpu_offset) + #include =20 #endif /* __ASM_PERCPU_H */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 0e71eb82f920c..733b6cd306e40 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -88,6 +88,13 @@ static inline void __switch_to_envcfg(struct task_struct= *next) :: "r" (next->thread.envcfg) : "memory"); } =20 +static inline void __switch_to_pcpu_offset(struct task_struct *next) +{ +#ifdef CONFIG_SMP + next->thread_info.pcpu_offset =3D __my_cpu_offset; +#endif +} + extern struct task_struct *__switch_to(struct task_struct *, struct task_struct *); =20 @@ -122,6 +129,7 @@ do { \ if (switch_to_should_flush_icache(__next)) \ local_flush_icache_all(); \ __switch_to_envcfg(__next); \ + __switch_to_pcpu_offset(__next); \ ((last) =3D __switch_to(__prev, __next)); \ } while (0) =20 diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/= thread_info.h index 36918c9200c92..8d7d43cc9c405 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -52,7 +52,8 @@ */ struct thread_info { unsigned long flags; /* low level flags */ - int preempt_count; /* 0=3D>preemptible, <0=3D>BUG */ + int preempt_count; /* 0=3D>preemptible, <0=3D>BUG */ + int cpu; /* * These stack pointers are overwritten on every system call or * exception. SP is also saved to the stack it can be recovered when @@ -60,8 +61,8 @@ struct thread_info { */ long kernel_sp; /* Kernel stack pointer */ long user_sp; /* User stack pointer */ - int cpu; unsigned long syscall_work; /* SYSCALL_WORK_ flags */ + unsigned long pcpu_offset; #ifdef CONFIG_SHADOW_CALL_STACK void *scs_base; void *scs_sp; diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offset= s.c index af827448a609e..fbf53b66b0e06 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -38,6 +38,7 @@ void asm_offsets(void) OFFSET(TASK_THREAD_SUM, task_struct, thread.sum); =20 OFFSET(TASK_TI_CPU, task_struct, thread_info.cpu); + OFFSET(TASK_TI_PCPU_OFFSET, task_struct, thread_info.pcpu_offset); OFFSET(TASK_TI_PREEMPT_COUNT, task_struct, thread_info.preempt_count); OFFSET(TASK_TI_KERNEL_SP, task_struct, thread_info.kernel_sp); OFFSET(TASK_TI_USER_SP, task_struct, thread_info.user_sp); diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index d85916a3660c3..9e95c068b966b 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -209,6 +209,11 @@ int __cpu_up(unsigned int cpu, struct task_struct *tid= le) } #endif =20 +void __init smp_prepare_boot_cpu(void) +{ + __my_cpu_offset =3D per_cpu_offset(smp_processor_id()); +} + void __init smp_cpus_done(unsigned int max_cpus) { } @@ -234,6 +239,8 @@ asmlinkage __visible void smp_callin(void) mmgrab(mm); current->active_mm =3D mm; =20 + __my_cpu_offset =3D per_cpu_offset(smp_processor_id()); + #ifdef CONFIG_HOTPLUG_PARALLEL cpuhp_ap_sync_alive(); #endif diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp6= 4.c index 5f9457e910e87..4a492a6a1cc1e 100644 --- a/arch/riscv/net/bpf_jit_comp64.c +++ b/arch/riscv/net/bpf_jit_comp64.c @@ -1345,15 +1345,8 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, s= truct rv_jit_context *ctx, if (rd !=3D rs) emit_mv(rd, rs, ctx); #ifdef CONFIG_SMP - /* Load current CPU number in T1 */ - emit_lw(RV_REG_T1, offsetof(struct thread_info, cpu), + emit_lw(RV_REG_T1, offsetof(struct thread_info, pcpu_offset), RV_REG_TP, ctx); - /* Load address of __per_cpu_offset array in T2 */ - emit_addr(RV_REG_T2, (u64)&__per_cpu_offset, extra_pass, ctx); - /* Get address of __per_cpu_offset[cpu] in T1 */ - emit_sh3add(RV_REG_T1, RV_REG_T1, RV_REG_T2, ctx); - /* Load __per_cpu_offset[cpu] in T1 */ - emit_ld(RV_REG_T1, 0, RV_REG_T1, ctx); /* Add the offset to Rd */ emit_add(rd, rd, RV_REG_T1, ctx); #endif --=20 2.39.5