From nobody Fri Dec 19 13:29:08 2025 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6989231827 for ; Mon, 8 Dec 2025 03:50:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765165839; cv=none; b=Bb0JY+slwo3NOlEWnGuEz/fNQDqwqJlkzqi4mrxg07bhubENounfbsyFW8j/lGufYZQsWpR8VH5TrRgWHhOI7Z/1MlwclAMnaoGuK8ZWtgq17/tWMOvuirIjObpfrHvD/lXeHoq2MsTvRO8qosC/xabAvaWdEgJ5Axr2eN6qsgk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765165839; c=relaxed/simple; bh=2S8VdCVOVRMhLF5pnwGHAuQCvqrTtPFg5LvAxtmaqpI=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uPAOG+oOOGgtuELcjtGze0TzJRX5dOkwQre/bW6S+oNbooz5hhwBHuoceavsjpVEWsuK9GsF3/sL5cl88L4IUoNUCBrxUXWO21n9Am6uOYOIsUaP4YkXIoRtPKyUegDcDHupNLri+caZ7Gu/yDhHA3aAd8p42oB1Us5WTz7LRZc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com; spf=pass smtp.mailfrom=bytedance.com; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b=GP8K/Okx; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bytedance.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b="GP8K/Okx" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-298145fe27eso62188795ad.1 for ; Sun, 07 Dec 2025 19:50:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1765165837; x=1765770637; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TcDdbeyUjaIQvBTZiz9kFlENYKGodkKBU6I+HMWpHSE=; b=GP8K/Okx3N6vWGjppOI88KOBfYqSf1V3UlBtdJyfMuLh6eCaxTpXLaeKksSm9IT+m9 mPATWk1BPUJf2RRQc852zyuDovq70mTuhO8g4yweZrrcJw+ghoUrW39yplewOhObnw9f YQ/6k1/oDauYfGqQoQu5iThvfmOUk2MvBCS83WttHro/v/mF8ZWf6MXZe03q29bP1qbk RuOM5THrG+41098kgwOsAFb21jcyRUOWQao9XhZcmlWaZS2zQ2dPR7coaM7HR/DBl+RQ mbaQThjElI5UfHfexoh3JRVep5N9OMZlYYgv7+6mqysmh9aHrtZV5EUkWrDocBHYGbVK 3RQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765165837; x=1765770637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=TcDdbeyUjaIQvBTZiz9kFlENYKGodkKBU6I+HMWpHSE=; b=mlTIJFroEEsiKPCr65QCyXA9mVzhII8RKDwf1wJiVsrGNbuVYIfk9Zu8BVRDD65sBg J2dtWYsPxeK1La/YDdkem0AmOm8Y7XgeFq9etoHKx3AUhuuLhd7RmZvPPYgr/AoUg1SA h/Ivt0eANQxALTo3FIXpfwuDTYHn8E1bU/E1suid34Vd2XKanbbRqKCUt2TKaQ9Mj1k8 /EOFDtXyCYbKhqlMmMbNadD8mMr05JnCiOifdfBT0ZlW6JyQXi8D5ua3QVIxwZljRdCz XRdCugBH43JHyFcT/FQGlHzE9QS3SLfXyYa9TZbH/5EW0LtYzoYiTl+VpOa5sXwcCOVJ zfxw== X-Forwarded-Encrypted: i=1; AJvYcCVxIKsJZMPuc84dmOXGAFx/ybjqdrYqQug1ALReY1cjHRor+7C84ty8Nnj2NgzWB1AWP0THpFMH3hJRou8=@vger.kernel.org X-Gm-Message-State: AOJu0Yw4Cax5b0OPoV47D7XN/4BFFHzVw3TLKqzUQH9MVeuW4NQIZIYI MHkI9LBwwCjl0/t5QmncLHxGldSvEj9X/sCrlpeJ+C4K0ynCg+MEhbg9O3CXQpvmCw4= X-Gm-Gg: ASbGncuRKIixLVL+c3aCCwlGFDNzmQN53s12R7LAmc98hXX1FKAAkGBcC2XMsy55gqZ 327TicmuH1Gg4cqEK5n9KXpQARM4Brz4QRlnsDt2vDKGTO1hs8jrYJ8N4EKU8cnL7me6WRMAYpa 4dw/oWhJzi62tGBFJOUzo293zu2PoS1qNZ8nSGBBD9WiHNZbJyszzxvmj96+i5q0i0UIyQxt5gX ZYgJgEbb8sbq3+HvwZ1TL9ceunMpxoDrXx53p6fNP1FR8Pl5SgjPZqqtTcSQUAtv9whsveEIGG8 K03Tkpi5sQZIXAgnUU/mtZNzwku9bvb7QSQEUmp8blc+O5h+rnKIQ2cjOIxnw/4Z7KFBayVQv+y 7xzPo+d+3uz4TYPCqMhHIa5fUVeL4B1FzG368uZRH4fj1PlYaAaqBcCLx0ElP4c9Ek5l82Rr7sx BXHZ02kKRAqu+UOmnm0r6asovcBlJlmNFWf7kx/k9IgzTs X-Google-Smtp-Source: AGHT+IEsyS70YjfqcY6uDUzuCw0QsSiDGBq56vWCrB/xumiB1z4Fux5bNgh47wXnVIwNcfKaN47/fA== X-Received: by 2002:a17:902:cf0f:b0:297:c4b0:8d53 with SMTP id d9443c01a7336-29df5e1b2femr51595245ad.54.1765165836888; Sun, 07 Dec 2025 19:50:36 -0800 (PST) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.240]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29daeae6d96sm108871275ad.102.2025.12.07.19.50.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 07 Dec 2025 19:50:36 -0800 (PST) From: Yunhui Cui To: aou@eecs.berkeley.edu, alex@ghiti.fr, andii@kernel.org, andybnac@gmail.com, apatel@ventanamicro.com, ast@kernel.org, ben.dooks@codethink.co.uk, bjorn@kernel.org, bpf@vger.kernel.org, charlie@rivosinc.com, cl@gentwo.org, conor.dooley@microchip.com, cuiyunhui@bytedance.com, cyrilbur@tenstorrent.com, daniel@iogearbox.net, debug@rivosinc.com, dennis@kernel.org, eddyz87@gmail.com, haoluo@google.com, john.fastabend@gmail.com, jolsa@kernel.org, kpsingh@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux@rasmusvillemoes.dk, martin.lau@linux.dev, palmer@dabbelt.com, pjw@kernel.org, puranjay@kernel.org, pulehui@huawei.com, ruanjinjie@huawei.com, rkrcmar@ventanamicro.com, samuel.holland@sifive.com, sdf@fomichev.me, song@kernel.org, tglx@linutronix.de, tj@kernel.org, thuth@redhat.com, yonghong.song@linux.dev, yury.norov@gmail.com, zong.li@sifive.com Subject: [PATCH v2 2/3] riscv: introduce percpu.h into include/asm Date: Mon, 8 Dec 2025 11:49:43 +0800 Message-Id: <20251208034944.73113-3-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251208034944.73113-1-cuiyunhui@bytedance.com> References: <20251208034944.73113-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Current percpu operations rely on generic implementations, where raw_local_irq_save() introduces substantial overhead. Optimization is achieved through atomic operations and preemption disabling. Currently, since RISC-V does not support lr/sc.b/h, when ZABHA is not supported, lr/sc.w needs to be used instead, which requires some additional mask operations. Signed-off-by: Yunhui Cui --- arch/riscv/include/asm/percpu.h | 238 ++++++++++++++++++++++++++++++++ 1 file changed, 238 insertions(+) create mode 100644 arch/riscv/include/asm/percpu.h diff --git a/arch/riscv/include/asm/percpu.h b/arch/riscv/include/asm/percp= u.h new file mode 100644 index 0000000000000..b173729926126 --- /dev/null +++ b/arch/riscv/include/asm/percpu.h @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __ASM_PERCPU_H +#define __ASM_PERCPU_H + +#include + +#include +#include +#include + +#define PERCPU_RW_OPS(sz) \ +static inline unsigned long __percpu_read_##sz(void *ptr) \ +{ \ + return READ_ONCE(*(u##sz *)ptr); \ +} \ + \ +static inline void __percpu_write_##sz(void *ptr, unsigned long val) \ +{ \ + WRITE_ONCE(*(u##sz *)ptr, (u##sz)val); \ +} + +PERCPU_RW_OPS(8) +PERCPU_RW_OPS(16) +PERCPU_RW_OPS(32) +PERCPU_RW_OPS(64) + +#define __PERCPU_AMO_OP_CASE(sfx, name, sz, amo_insn) \ +static inline void \ +__percpu_##name##_amo_case_##sz(void *ptr, unsigned long val) \ +{ \ + asm volatile ( \ + "amo" #amo_insn #sfx " zero, %[val], %[ptr]" \ + : [ptr] "+A" (*(u##sz *)ptr) \ + : [val] "r" ((u##sz)(val)) \ + : "memory"); \ +} + +#define PERCPU_OP(name, amo_insn) \ + __PERCPU_AMO_OP_CASE(.w, name, 32, amo_insn) \ + __PERCPU_AMO_OP_CASE(.d, name, 64, amo_insn) + +PERCPU_OP(add, add) +PERCPU_OP(andnot, and) +PERCPU_OP(or, or) + +/* + * Currently, only this_cpu_add_return_xxx() requires a return value, + * and the PERCPU_RET_OP() does not account for other operations. + */ +#define __PERCPU_AMO_RET_OP_CASE(sfx, name, sz, amo_insn) \ +static inline u##sz \ +__percpu_##name##_return_amo_case_##sz(void *ptr, unsigned long val) \ +{ \ + register u##sz ret; \ + \ + asm volatile ( \ + "amo" #amo_insn #sfx " %[ret], %[val], %[ptr]" \ + : [ptr] "+A" (*(u##sz *)ptr), [ret] "=3Dr" (ret) \ + : [val] "r" ((u##sz)(val)) \ + : "memory"); \ + \ + return ret + val; \ +} + +#define PERCPU_RET_OP(name, amo_insn) \ + __PERCPU_AMO_RET_OP_CASE(.w, name, 32, amo_insn) \ + __PERCPU_AMO_RET_OP_CASE(.d, name, 64, amo_insn) + +PERCPU_RET_OP(add, add) + +#define PERCPU_8_16_GET_SHIFT(ptr) (((unsigned long)(ptr) & 0x3) * BITS_PE= R_BYTE) +#define PERCPU_8_16_GET_MASK(sz) GENMASK((sz)-1, 0) +#define PERCPU_8_16_GET_PTR32(ptr) ((u32 *)((unsigned long)(ptr) & ~0x3)) + +#define PERCPU_8_16_OP(name, amo_insn, sz, sfx, val_type, new_val_expr, as= m_op) \ +static inline void __percpu_##name##_amo_case_##sz(void *ptr, unsigned lon= g val) \ +{ \ + if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA) && \ + riscv_has_extension_unlikely(RISCV_ISA_EXT_ZABHA)) { \ + asm volatile ("amo" #amo_insn #sfx " zero, %[val], %[ptr]" \ + : [ptr] "+A"(*(val_type *)ptr) \ + : [val] "r"((val_type)(new_val_expr)) \ + : "memory"); \ + } else { \ + u32 *ptr32 =3D PERCPU_8_16_GET_PTR32(ptr); \ + const unsigned long shift =3D PERCPU_8_16_GET_SHIFT(ptr); \ + const u32 mask =3D PERCPU_8_16_GET_MASK(sz) << shift; \ + const val_type val_trunc =3D (val_type)(new_val_expr); \ + u32 retx, rc; \ + val_type new_val_type; \ + \ + asm volatile ( \ + "0: lr.w %0, %2\n" \ + "and %3, %0, %4\n" \ + "srl %3, %3, %5\n" \ + #asm_op " %3, %3, %6\n" \ + "sll %3, %3, %5\n" \ + "and %1, %0, %7\n" \ + "or %1, %1, %3\n" \ + "sc.w %1, %1, %2\n" \ + "bnez %1, 0b\n" \ + : "=3D&r"(retx), "=3D&r"(rc), "+A"(*ptr32), "=3D&r"(new_val_type) \ + : "r"(mask), "r"(shift), "r"(val_trunc), "r"(~mask) \ + : "memory"); \ + } \ +} + +#define PERCPU_OP_8_16(op_name, op, expr, final_op) \ + PERCPU_8_16_OP(op_name, op, 8, .b, u8, expr, final_op); \ + PERCPU_8_16_OP(op_name, op, 16, .h, u16, expr, final_op) + +PERCPU_OP_8_16(add, add, val, add) +PERCPU_OP_8_16(andnot, and, ~val, and) +PERCPU_OP_8_16(or, or, val, or) + +#define PERCPU_8_16_RET_OP(name, amo_insn, sz, sfx, val_type, new_val_expr= ) \ +static inline val_type __percpu_##name##_return_amo_case_##sz(void *ptr, u= nsigned long val) \ +{ \ + if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA) && \ + riscv_has_extension_unlikely(RISCV_ISA_EXT_ZABHA)) { \ + register val_type ret; \ + asm volatile ("amo" #amo_insn #sfx " %[ret], %[val], %[ptr]" \ + : [ptr] "+A"(*(val_type *)ptr), [ret] "=3Dr"(ret) \ + : [val] "r"((val_type)(new_val_expr)) \ + : "memory"); \ + return ret + (val_type)(new_val_expr); \ + } else { \ + u32 *ptr32 =3D PERCPU_8_16_GET_PTR32(ptr); \ + const unsigned long shift =3D PERCPU_8_16_GET_SHIFT(ptr); \ + const u32 mask =3D (PERCPU_8_16_GET_MASK(sz) << shift); \ + const u32 inv_mask =3D ~mask; \ + const val_type val_trunc =3D (val_type)(new_val_expr); \ + u32 old, new, tmp; \ + \ + asm volatile ( \ + "0: lr.w %0, %3\n" \ + "and %1, %0, %4\n" \ + "srl %1, %1, %5\n" \ + "add %1, %1, %6\n" \ + "and %1, %1, %7\n" \ + "sll %1, %1, %5\n" \ + "and %2, %0, %8\n" \ + "or %2, %2, %1\n" \ + "sc.w %2, %2, %3\n" \ + "bnez %2, 0b\n" \ + : "=3Dr"(old), "=3Dr"(tmp), "=3D&r"(new), "+A"(*ptr32) \ + : "r"(mask), "r"(shift), "r"(val_trunc), "r"(PERCPU_8_16_GET_MASK(sz)),= \ + "r"(inv_mask) \ + : "memory"); \ + return (val_type)(tmp); \ + } \ +} + +PERCPU_8_16_RET_OP(add, add, 8, .b, u8, val) +PERCPU_8_16_RET_OP(add, add, 16, .h, u16, val) + +#define _pcp_protect(op, pcp, ...) \ +({ \ + preempt_disable_notrace(); \ + op(raw_cpu_ptr(&(pcp)), __VA_ARGS__); \ + preempt_enable_notrace(); \ +}) + +#define _pcp_protect_return(op, pcp, args...) \ +({ \ + typeof(pcp) __retval; \ + preempt_disable_notrace(); \ + __retval =3D (typeof(pcp))op(raw_cpu_ptr(&(pcp)), ##args); \ + preempt_enable_notrace(); \ + __retval; \ +}) + +#define this_cpu_read_1(pcp) _pcp_protect_return(__percpu_read_8, pcp) +#define this_cpu_read_2(pcp) _pcp_protect_return(__percpu_read_16, pcp) +#define this_cpu_read_4(pcp) _pcp_protect_return(__percpu_read_32, pcp) +#define this_cpu_read_8(pcp) _pcp_protect_return(__percpu_read_64, pcp) + +#define this_cpu_write_1(pcp, val) _pcp_protect(__percpu_write_8, pcp, (un= signed long)val) +#define this_cpu_write_2(pcp, val) _pcp_protect(__percpu_write_16, pcp, (u= nsigned long)val) +#define this_cpu_write_4(pcp, val) _pcp_protect(__percpu_write_32, pcp, (u= nsigned long)val) +#define this_cpu_write_8(pcp, val) _pcp_protect(__percpu_write_64, pcp, (u= nsigned long)val) + +#define this_cpu_add_1(pcp, val) _pcp_protect(__percpu_add_amo_case_8, pcp= , val) +#define this_cpu_add_2(pcp, val) _pcp_protect(__percpu_add_amo_case_16, pc= p, val) +#define this_cpu_add_4(pcp, val) _pcp_protect(__percpu_add_amo_case_32, pc= p, val) +#define this_cpu_add_8(pcp, val) _pcp_protect(__percpu_add_amo_case_64, pc= p, val) + +#define this_cpu_add_return_1(pcp, val) \ +_pcp_protect_return(__percpu_add_return_amo_case_8, pcp, val) + +#define this_cpu_add_return_2(pcp, val) \ +_pcp_protect_return(__percpu_add_return_amo_case_16, pcp, val) + +#define this_cpu_add_return_4(pcp, val) \ +_pcp_protect_return(__percpu_add_return_amo_case_32, pcp, val) + +#define this_cpu_add_return_8(pcp, val) \ +_pcp_protect_return(__percpu_add_return_amo_case_64, pcp, val) + +#define this_cpu_and_1(pcp, val) _pcp_protect(__percpu_andnot_amo_case_8, = pcp, ~val) +#define this_cpu_and_2(pcp, val) _pcp_protect(__percpu_andnot_amo_case_16,= pcp, ~val) +#define this_cpu_and_4(pcp, val) _pcp_protect(__percpu_andnot_amo_case_32,= pcp, ~val) +#define this_cpu_and_8(pcp, val) _pcp_protect(__percpu_andnot_amo_case_64,= pcp, ~val) + +#define this_cpu_or_1(pcp, val) _pcp_protect(__percpu_or_amo_case_8, pcp, = val) +#define this_cpu_or_2(pcp, val) _pcp_protect(__percpu_or_amo_case_16, pcp,= val) +#define this_cpu_or_4(pcp, val) _pcp_protect(__percpu_or_amo_case_32, pcp,= val) +#define this_cpu_or_8(pcp, val) _pcp_protect(__percpu_or_amo_case_64, pcp,= val) + +#define this_cpu_xchg_1(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, v= al) +#define this_cpu_xchg_2(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, v= al) +#define this_cpu_xchg_4(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, v= al) +#define this_cpu_xchg_8(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, v= al) + +#define this_cpu_cmpxchg_1(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed,= pcp, o, n) +#define this_cpu_cmpxchg_2(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed,= pcp, o, n) +#define this_cpu_cmpxchg_4(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed,= pcp, o, n) +#define this_cpu_cmpxchg_8(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed,= pcp, o, n) + +#define this_cpu_cmpxchg64(pcp, o, n) this_cpu_cmpxchg_8(pcp, o, n) + +#define this_cpu_cmpxchg128(pcp, o, n) \ +({ \ + u128 old__, new__, ret__; \ + typeof(pcp) *ptr__; \ + old__ =3D o; \ + new__ =3D n; \ + preempt_disable_notrace(); \ + ptr__ =3D raw_cpu_ptr(&(pcp)); \ + ret__ =3D cmpxchg128_local(ptr__, old__, new__); \ + preempt_enable_notrace(); \ + ret__; \ +}) + +#include + +#endif /* __ASM_PERCPU_H */ --=20 2.39.5