From nobody Fri Dec 19 11:14:18 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBCDA2E62A2; Mon, 8 Dec 2025 09:42:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765186946; cv=none; b=MtgvONYbd2o92GOf8sJTWMhvQ0w+/yED2i4NA2QJPmJI9XG2+2nEbMMxLZxUKUmUbrSn7hswZeTuHnJYpOk/4eHXDfrgvG6YO0Da3TIIXOH1itPidRVYwkngWs18KD5YtUdrHtlufDdUz6pNS3cxyEifRNw8aaco1qZyap2V6wM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765186946; c=relaxed/simple; bh=HjJDMUd9VNGNyS2sUGn4tel1CQSAz6Tp6zX5Z6lzkq8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QHVagoTms2nQpDtqC218bdiGvNChyZEQufKymQIN9T+uf+QkOUk6Rfi5AprkTFqehYlOi7YI+uyTA8rEjBSFNxod1pDllIF6L+LSSd4SzWa+77jGxPs40xzIeNGtUH/mVLY+hIsZL7CqmFThoh6+56B/4AHXBYf7VCgGHnXt9dA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TPOzpkq2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TPOzpkq2" Received: by smtp.kernel.org (Postfix) with ESMTPS id 82970C19421; Mon, 8 Dec 2025 09:42:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1765186945; bh=HjJDMUd9VNGNyS2sUGn4tel1CQSAz6Tp6zX5Z6lzkq8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=TPOzpkq2nTI6hKoaT3FSs7xzUbOt1FCByuASCr/x+nqkbmdwACHm9o60JqmVxJ7oC nT9u8ZlaAtgFv+C+tIS8UQndvhVzKPMyQTWpyJ39WtZIsTDUBfSPj+1ouwPk33V4H4 YLvrJQg1OxU7IM+6hlvsU5wlk4SEf9eHnYAyu0lks6Mk3baQebe/abkng8OEQQ4LmE dqGzJzLB1s+LdHQ2xllEryjmZoROeNP+AYKXX/dStyD4rIIGMoFPtgsOjfab8VNBLW ojT6kA8Sciae0Bdny2GAFHVYwfCxAXbM5mhRqpFu0s3qOl97eN7yDP1A8s4iVpG6mh +Dwh/HpMN4ZxA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CDF5D3B7DE; Mon, 8 Dec 2025 09:42:25 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Mon, 08 Dec 2025 10:41:54 +0100 Subject: [PATCH v6 1/8] dt-bindings: arm: qcom: Add Pixel 3 and 3 XL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251208-pixel-3-v6-1-e9e559d6f412@ixit.cz> References: <20251208-pixel-3-v6-0-e9e559d6f412@ixit.cz> In-Reply-To: <20251208-pixel-3-v6-0-e9e559d6f412@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Casey Connolly , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Marijn Suijten , Dmitry Baryshkov , Vinod Koul , Petr Hodina , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Heidelberg , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=765; i=david@ixit.cz; h=from:subject:message-id; bh=Vnt/xXHh7c01EXNWnpunAXvFyH2vLjx4UfYXxFc1+5w=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpNp1/qlP6M4fA/UAI9sFslieZ/vPbVdIWRdnrw sNMRGePcV+JAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaTadfwAKCRBgAj/E00kg csCCD/9pw77H//blcdVh47TCMq5x3u0geMj+edvvECKlk1jqZQkeDoAACyJKOxWFTIesWIihVG9 G8iNdshQeUF2v/ODkPkeCrM8iVbYbMzz/V7wBIxwJreiTM/FOQlcDJzfKC/0oscYQ+Rns+Kc2RL OjZgwCgBMy0JH3e6OVo9fWxyYJ4CjjLOhBIOxdiDgbq6xXXXuhEhL5QuRADK5bsAnlbmk2ere6o Wfpv41N7OPAape7rCm+Klcal8c+tVLH3yHU0sj7wfnssL+GF5vIARAGDN/wmubUf7VOtLpddnAU imeOPaDTfB6ewq4t9N00Me4+KXoWGz6MtabP2sWj/qDi9oj3fpdMJq2D20QgY61qfIEcE3mLZc7 jdaufFk7fz3sVnPBMcioC8umAOmFNvfZJ+VmenataKIMUIxyiICtodu6wIpDUXZ7nHjlYinhhCA GLZ0gQvSdSOUcSc7K+yvhFRQpHbQ7zpkNjuIIHTKIMZWM8sQGKH3ThDmJRSLKyf+2V4f/9gR2Ad C9Bt3mt5jGaBwH3YgDUzxBMFHu/m+uwrx61IE7HduThDRQOGxcFho0h6I/P4WWHPE/63/R3SOs9 5WIh6N3R0XbQQaPZ9AZAKIBRML8H1boVMp7kGShdvXXxAkwMqpSdeatqYVgtavpi4W8S6/Eyr7M QjAetK403TJj8dQ== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Document the bindings for the Pixel 3 and 3 XL. Acked-by: Krzysztof Kozlowski Signed-off-by: David Heidelberg --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index d84bd3bca2010..760b6633b7a55 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -900,6 +900,8 @@ properties: =20 - items: - enum: + - google,blueline + - google,crosshatch - huawei,planck - lenovo,yoga-c630 - lg,judyln --=20 2.51.0 From nobody Fri Dec 19 11:14:18 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBD4A2F618B; Mon, 8 Dec 2025 09:42:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251208-pixel-3-v6-2-e9e559d6f412@ixit.cz> References: <20251208-pixel-3-v6-0-e9e559d6f412@ixit.cz> In-Reply-To: <20251208-pixel-3-v6-0-e9e559d6f412@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Casey Connolly , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Marijn Suijten , Dmitry Baryshkov , Vinod Koul , Petr Hodina , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Heidelberg , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1948; i=david@ixit.cz; h=from:subject:message-id; bh=YFbMU07Wu5FnvTw9LCEYZ4TnpCBRf84TLv0leteBovM=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpNp1/2va/mVnfDJFtJnUzeoVBNshAhSm3Ggl2r 5QA/uM5P6qJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaTadfwAKCRBgAj/E00kg chtGD/9BRz2pbgCA5jVXvzIkQFz5VPZK6MADTaowDuIVc05EFfw847eVJ5l7MmBDfALQXt3fY30 IAHs8oeh/Q8omQjqwVB80tn631ArucHySGNes6wHnn4aky3/eJi4unvT/Hhzx6xJS4Bfd+dNdaD JvRBf03pfWnqLLsPFtnc7MmR4MKVizOS/+cHvsStCfd2THFCosCOVDryvzUlY4/njLkbtGfDDjT ozsLb5x192nR0ggJyAUaF4/qBnth52cFcCSibYWTyxVGx8iOjSl+UY+hBLlhCIfxUYyolJ4J2+u Vm24ODGYN9gk6blxMnjGkd9D/jTr1rNi3tMCUYInLVUAeKUHTm0K7ga01eHhluxR6T66v/SqIl3 NNkDLeMdhkQHCW6l09HohEDXUSoDYjAWBxDkD7HeNrgOl+LxJBZWQ3c649297Gblzlm/C3pP4NS Wo4fwvs7P1l6bQiC1Nv+etV4MfCBOQRFVx6CkOHJrVaBTBbx5WsXKNhns756W+HdXYCqdvDRv1Y YUb/6LcZZjN7JuXdSpkgRoUzxf8oRMxg9xzsZNtO5Crazo4pGjNPzxPMEWNEzmSN6UX9E6iAuzb zj5yMgnssRXlNor1dn/IRZGPaDgrzqDBXm2ZrhSAD5QpOA3GxhHPYMbsyJKjAsie4Mu77DXgJ7p YWgsJB70FH5m5EA== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Add compatible for used LG panel. SW43408 is not panel, but DDIC. The panel itself is the LG LH546WF1-ED01, so introduce combined compatible for it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: David Heidelberg --- .../devicetree/bindings/display/panel/lg,sw43408.yaml | 13 +++++++++= ---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yam= l b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml index 2219d3d4ac43b..f641efaeb8b36 100644 --- a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml +++ b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml @@ -4,14 +4,16 @@ $id: http://devicetree.org/schemas/display/panel/lg,sw43408.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: LG SW43408 1080x2160 DSI panel +title: LG SW43408 AMOLED DDIC =20 maintainers: - Casey Connolly =20 description: - This panel is used on the Pixel 3, it is a 60hz OLED panel which - required DSC (Display Stream Compression) and has rounded corners. + The SW43408 is display driver IC with connected panel. + + LG LH546WF1-ED01 panel is used on the Pixel 3, it is a 60hz OLED panel + which required DSC (Display Stream Compression) and has rounded corners. =20 allOf: - $ref: panel-common.yaml# @@ -19,6 +21,9 @@ allOf: properties: compatible: items: + - enum: + # LG 5.46 inch, 1080x2160 pixels, 18:9 ratio + - lg,sw43408-lh546wf1-ed01 - const: lg,sw43408 =20 reg: @@ -46,7 +51,7 @@ examples: #size-cells =3D <0>; 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Mon, 8 Dec 2025 09:42:25 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Mon, 08 Dec 2025 10:41:56 +0100 Subject: [PATCH v6 3/8] drm/panel: sw43408: Introduce LH546WF1-ED01 panel compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251208-pixel-3-v6-3-e9e559d6f412@ixit.cz> References: <20251208-pixel-3-v6-0-e9e559d6f412@ixit.cz> In-Reply-To: <20251208-pixel-3-v6-0-e9e559d6f412@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Casey Connolly , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Marijn Suijten , Dmitry Baryshkov , Vinod Koul , Petr Hodina , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg The supported panel is LH546WF1-ED01, add compatible and adjust the struct name to reflect that. The standalone compatible lg,sw43408 will continue to work, even thou there are no users yet. Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg --- drivers/gpu/drm/panel/panel-lg-sw43408.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/pan= el/panel-lg-sw43408.c index 46a56ea92ad9f..dcca7873acf8e 100644 --- a/drivers/gpu/drm/panel/panel-lg-sw43408.c +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -149,7 +149,7 @@ static int sw43408_prepare(struct drm_panel *panel) return ret; } =20 -static const struct drm_display_mode sw43408_mode =3D { +static const struct drm_display_mode lh546wf1_ed01_mode =3D { .clock =3D (1080 + 20 + 32 + 20) * (2160 + 20 + 4 + 20) * 60 / 1000, =20 .hdisplay =3D 1080, @@ -171,7 +171,7 @@ static const struct drm_display_mode sw43408_mode =3D { static int sw43408_get_modes(struct drm_panel *panel, struct drm_connector *connector) { - return drm_connector_helper_get_modes_fixed(connector, &sw43408_mode); + return drm_connector_helper_get_modes_fixed(connector, &lh546wf1_ed01_mod= e); } =20 static int sw43408_backlight_update_status(struct backlight_device *bl) @@ -214,7 +214,8 @@ static const struct drm_panel_funcs sw43408_funcs =3D { }; =20 static const struct of_device_id sw43408_of_match[] =3D { - { .compatible =3D "lg,sw43408", }, + { .compatible =3D "lg,sw43408", }, /* legacy */ + { .compatible =3D "lg,sw43408-lh546wf1-ed01", }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sw43408_of_match); --=20 2.51.0 From nobody Fri Dec 19 11:14:18 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EC562F6587; Mon, 8 Dec 2025 09:42:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765186946; cv=none; b=WZdCuD45r/yGIMqHlAPG8PvOBq0wjhuULC5VF4tY8ChEmOGbM6mGOQuDe1H9msP1HijsSOoodde2s1sMTl5bayao5Sf7kJ6rRj4wVPA1hUb/sjmq1dkAs5P6C5u/7V0nTMTtia6+qoD+UeTvHjjDVo/bGUQ648/MafEwd98M5es= ARC-Message-Signature: i=1; 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b=uSbvcs4d9/nd64KlxxSkU7RDL+kxBRCVNeWntrxExxbZl69jc65ykhTGUyGBfeVYn kJXVL4/dwwZuBz4QaPS2F6uFo6St6qd6hL77TXDjp9vcGF679q3TuDUcHvQ/yBeIJ/ 0cjZLiVU2o7IaGfVfSaEiJqa8duLWUKtEjKxoEfwgod7hHiPc3Mh8R49qhYEetfSHZ RAf0kGdi9snVS7eX8LmZtc3gXfpozruulwwQnUiPOxWYZLrmws0gVtSY4G0rpvifUZ F04RaeOQFUTPKF5P4yHdp+Hzfdqqh0/XnoSovlohd+On/2b0CBMMk+kcejppcQfe4J y/2hBWUy9ZC/w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACC39D3B7E8; Mon, 8 Dec 2025 09:42:25 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Mon, 08 Dec 2025 10:41:57 +0100 Subject: [PATCH v6 4/8] drm/panel: sw43408: Add enable/disable and reset functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251208-pixel-3-v6-4-e9e559d6f412@ixit.cz> References: <20251208-pixel-3-v6-0-e9e559d6f412@ixit.cz> In-Reply-To: <20251208-pixel-3-v6-0-e9e559d6f412@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Casey Connolly , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Marijn Suijten , Dmitry Baryshkov , Vinod Koul , Petr Hodina , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4042; i=david@ixit.cz; h=from:subject:message-id; bh=qN5N+wyRlTAEEdBXkU0m8ndfuHhWL8oA++gF/EwODJc=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpNp1/kkA3vvylZ+8cMHHZS2NThYES8yN3zqhuu ZuGxQ1j43iJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaTadfwAKCRBgAj/E00kg cv2cEACcHz4ocz4NqY/iG7yqNqtCuDpD3sIbfDmQeg4v/KR47l1LCftkzCjBo2HRf0Cq007b3rI LMoS1Bt5KQSTOGRJd055fcnU6rQXXNCeUnpwmWCMj07jdYixE51FK+yWJPVrXtw6Vjxc5L4KHd6 U6id8ZVqDV1Bw1gSUQHCxOrsDIHxOdd8nybmJoabW1OQ60COPaXl0oRFINuU329SQgi0YcxFT7b YU3Tk+OgHwDom3A0Y2UY4QoU+E3iEd+fQAWtu3P8fmZYgWxQHI19B9pESXxYfUsKXjazGa/Ickh 7vTh3RBEJlWKUc3LElxj0HElotJNqXJOkJ/KMO5mYexuJ0HDQXO5c1OHsY2/OXnEHvdq1qHgyWW c5E6kdxRt8KWAitNDpCO61Zuw2arVBX+Ry4dKp8pfHVwmZIX/R8J51RQT9o0MZr1pUKsa7HdgGH gF5W4i91xXknicDH7t7PGm2dbZ4uWswCSxxx19ihFSljJuN99VPyuB30bVsvYgQvjLMcjCfWmcW LM2AneVYvPweUGkv7FjUkDPXEiLRdB7EANuxOTNb2O2a7zGfMvLy11d/IxvUvMoG5jJP0PA1Kfj YKI5i6nr3NsB8phXKGgTYkUBIxC0Bc504PGTFIhPMplrrHjokyN+95tIsF/jyTC99dp5yxNN5VO /d73rhnGet2Wdlw== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Introduce enable(), disable() and reset() functions. The enable() and disable() callbacks keep the symmetry in the commands sent to the panel and also make a clearer distinction between panel initialization and configuration. Splitting reset() from prepare() follows clean coding practices and lets us potentially make reset optional in the future for flicker-less takeover from a bootloader or framebuffer driver where the panel is already configured. Signed-off-by: David Heidelberg --- drivers/gpu/drm/panel/panel-lg-sw43408.c | 47 ++++++++++++++++++++++++----= ---- 1 file changed, 35 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/pan= el/panel-lg-sw43408.c index dcca7873acf8e..dad6b967b92c2 100644 --- a/drivers/gpu/drm/panel/panel-lg-sw43408.c +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -38,11 +38,10 @@ static inline struct sw43408_panel *to_panel_info(struc= t drm_panel *panel) return container_of(panel, struct sw43408_panel, base); } =20 -static int sw43408_unprepare(struct drm_panel *panel) +static int sw43408_disable(struct drm_panel *panel) { struct sw43408_panel *sw43408 =3D to_panel_info(panel); struct mipi_dsi_multi_context ctx =3D { .dsi =3D sw43408->link }; - int ret; =20 mipi_dsi_dcs_set_display_off_multi(&ctx); =20 @@ -50,18 +49,25 @@ static int sw43408_unprepare(struct drm_panel *panel) =20 mipi_dsi_msleep(&ctx, 100); =20 + return ctx.accum_err; +} + +static int sw43408_unprepare(struct drm_panel *panel) +{ + struct sw43408_panel *sw43408 =3D to_panel_info(panel); + int ret; + gpiod_set_value(sw43408->reset_gpio, 1); =20 ret =3D regulator_bulk_disable(ARRAY_SIZE(sw43408->supplies), sw43408->su= pplies); =20 - return ret ? : ctx.accum_err; + return ret; } =20 static int sw43408_program(struct drm_panel *panel) { struct sw43408_panel *sw43408 =3D to_panel_info(panel); struct mipi_dsi_multi_context ctx =3D { .dsi =3D sw43408->link }; - struct drm_dsc_picture_parameter_set pps; =20 mipi_dsi_dcs_write_seq_multi(&ctx, MIPI_DCS_SET_GAMMA_CURVE, 0x02); =20 @@ -97,6 +103,15 @@ static int sw43408_program(struct drm_panel *panel) mipi_dsi_dcs_write_seq_multi(&ctx, 0x55, 0x04, 0x61, 0xdb, 0x04, 0x70, 0x= db); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0xca); =20 + return ctx.accum_err; +} + +static int sw43408_enable(struct drm_panel *panel) +{ + struct sw43408_panel *sw43408 =3D to_panel_info(panel); + struct mipi_dsi_multi_context ctx =3D { .dsi =3D sw43408->link }; + struct drm_dsc_picture_parameter_set pps; + mipi_dsi_dcs_set_display_on_multi(&ctx); =20 mipi_dsi_msleep(&ctx, 50); @@ -116,18 +131,12 @@ static int sw43408_program(struct drm_panel *panel) */ mipi_dsi_compression_mode_ext_multi(&ctx, true, MIPI_DSI_COMPRESSION_DSC, 1); + return ctx.accum_err; } =20 -static int sw43408_prepare(struct drm_panel *panel) +static void sw43408_reset(struct sw43408_panel *ctx) { - struct sw43408_panel *ctx =3D to_panel_info(panel); - int ret; - - ret =3D regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); - if (ret < 0) - return ret; - usleep_range(5000, 6000); =20 gpiod_set_value(ctx->reset_gpio, 0); @@ -136,6 +145,18 @@ static int sw43408_prepare(struct drm_panel *panel) usleep_range(1000, 2000); gpiod_set_value(ctx->reset_gpio, 0); usleep_range(9000, 10000); +} + +static int sw43408_prepare(struct drm_panel *panel) +{ + struct sw43408_panel *ctx =3D to_panel_info(panel); + int ret; + + ret =3D regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (ret < 0) + return ret; + + sw43408_reset(ctx); =20 ret =3D sw43408_program(panel); if (ret) @@ -208,6 +229,8 @@ static int sw43408_backlight_init(struct sw43408_panel = *ctx) } =20 static const struct drm_panel_funcs sw43408_funcs =3D { + .disable =3D sw43408_disable, + .enable =3D sw43408_enable, .unprepare =3D sw43408_unprepare, .prepare =3D sw43408_prepare, .get_modes =3D sw43408_get_modes, --=20 2.51.0 From nobody Fri Dec 19 11:14:18 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61B34314D3B; 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a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg The drm_panel_remove should take care of disable/unprepare. Remove the manual call from the sw43408_remove function. Fixes: 069a6c0e94f9 ("drm: panel: Add LG sw43408 panel driver") Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg --- drivers/gpu/drm/panel/panel-lg-sw43408.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/pan= el/panel-lg-sw43408.c index dad6b967b92c2..06b9c5e650edf 100644 --- a/drivers/gpu/drm/panel/panel-lg-sw43408.c +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -318,10 +318,6 @@ static void sw43408_remove(struct mipi_dsi_device *dsi) struct sw43408_panel *ctx =3D mipi_dsi_get_drvdata(dsi); int ret; =20 - ret =3D sw43408_unprepare(&ctx->base); - if (ret < 0) - dev_err(&dsi->dev, "failed to unprepare panel: %d\n", ret); - ret =3D mipi_dsi_detach(dsi); if (ret < 0) dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret); --=20 2.51.0 From nobody Fri Dec 19 11:14:18 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61BFB315760; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251208-pixel-3-v6-6-e9e559d6f412@ixit.cz> References: <20251208-pixel-3-v6-0-e9e559d6f412@ixit.cz> In-Reply-To: <20251208-pixel-3-v6-0-e9e559d6f412@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Casey Connolly , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Marijn Suijten , Dmitry Baryshkov , Vinod Koul , Petr Hodina , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2779; i=david@ixit.cz; h=from:subject:message-id; bh=FslEhjXGojUkauhq/OFIjdrErLG55tF+5ngAsfmKcWA=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpNp1/QW4GScA8cEz+uhXAJUtAgwmVHwHY4iRM2 vwuelghuCaJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaTadfwAKCRBgAj/E00kg ck25EAC5uhi1m435DMsot5KN86ZhoHWasdgQfpWrEK+Tj7zj1W0cK/zJ0q0LC+4FUBNAcOP6mK4 DZCEhQHHj+rFtaAltEjRouVGlGLYO069Obqfiv7d2E0vIh7OjJCTrMBYftLKdoq965x1k8eK8qH h1DQCuYQyu7cXOAScceqj7rDGjAGAR78pRDuvnL2QCm34Khech3T8DTnV0duei1BtbYsXu1k1Jp BsgCK5+8tg8jDISWphqbzAbPUyfKif0w3yxzrPGaVsq1UZzpH0qoAxZC+VaxGpTW7M40b0a9iHc Vw6W1zSaefzSZgG4daNAZhzbyubcCpLfSNtqCyIfIh/0UKcbEBL6VQpFyqVIdp/drsGIynOSHLc ZsFURGFONcXWNh0TZG8SJA67u1eLFbzPwjFx4HYPRPEJK9tqIysqrqTzh8K/TBBMEVKoGN8lVIc kAkzCYVDsc81FBcHqrSJsk2ay+jdZ3WyeS/Hr7sFdQrp7oHSpnnIrfwmfqanXyyaSPd3o86xqtp Uc+xE0ankiWf9py7PoGOZ+aROYPotxmAp7oVE/fCP0KFamGmm/9oTluAaqlu4lH0kkMqFJr7tHr yfqK7HYKxJfg4ouEZHr9woOuY83NKVFVcB+hjqk7BLLUButPUT0xDFW8QNEE5qfEnbF0Rvp0Nq0 9Nk/cXsAD9kqPqQ== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Switch to devm_regulator_bulk_get_const() to stop setting the supplies list in probe(), and move the regulator_bulk_data struct in static const. Cosmetic: adjust comment for regulator from 1.88V to 1.8 V. Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg --- drivers/gpu/drm/panel/panel-lg-sw43408.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/pan= el/panel-lg-sw43408.c index 06b9c5e650edf..e8a970b53d873 100644 --- a/drivers/gpu/drm/panel/panel-lg-sw43408.c +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -20,13 +20,18 @@ #include #include =20 -#define NUM_SUPPLIES 2 +static const struct regulator_bulk_data sw43408_supplies[] =3D { + { .supply =3D "vddi", /* 1.8 V */ + .init_load_uA =3D 62000 }, + { .supply =3D "vpnl", /* 3.0 V */ + .init_load_uA =3D 857000 }, +}; =20 struct sw43408_panel { struct drm_panel base; struct mipi_dsi_device *link; =20 - struct regulator_bulk_data supplies[NUM_SUPPLIES]; + struct regulator_bulk_data *supplies; =20 struct gpio_desc *reset_gpio; =20 @@ -59,7 +64,7 @@ static int sw43408_unprepare(struct drm_panel *panel) =20 gpiod_set_value(sw43408->reset_gpio, 1); =20 - ret =3D regulator_bulk_disable(ARRAY_SIZE(sw43408->supplies), sw43408->su= pplies); + ret =3D regulator_bulk_disable(ARRAY_SIZE(sw43408_supplies), sw43408->sup= plies); =20 return ret; } @@ -152,7 +157,7 @@ static int sw43408_prepare(struct drm_panel *panel) struct sw43408_panel *ctx =3D to_panel_info(panel); int ret; =20 - ret =3D regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + ret =3D regulator_bulk_enable(ARRAY_SIZE(sw43408_supplies), ctx->supplies= ); if (ret < 0) return ret; =20 @@ -166,7 +171,7 @@ static int sw43408_prepare(struct drm_panel *panel) =20 poweroff: gpiod_set_value(ctx->reset_gpio, 1); - regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + regulator_bulk_disable(ARRAY_SIZE(sw43408_supplies), ctx->supplies); return ret; } =20 @@ -248,13 +253,10 @@ static int sw43408_add(struct sw43408_panel *ctx) struct device *dev =3D &ctx->link->dev; int ret; =20 - ctx->supplies[0].supply =3D "vddi"; /* 1.88 V */ - ctx->supplies[0].init_load_uA =3D 62000; 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a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Choose better wording. Cosmetic: also inline PTR_ERR. Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg --- drivers/gpu/drm/panel/panel-lg-sw43408.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/pan= el/panel-lg-sw43408.c index e8a970b53d873..edc7749d98d71 100644 --- a/drivers/gpu/drm/panel/panel-lg-sw43408.c +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -262,8 +262,8 @@ static int sw43408_add(struct sw43408_panel *ctx) =20 ctx->reset_gpio =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(ctx->reset_gpio)) { - ret =3D PTR_ERR(ctx->reset_gpio); - return dev_err_probe(dev, ret, "cannot get reset gpio\n"); + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "Failed to get reset-gpios\n"); } =20 ret =3D sw43408_backlight_init(ctx); --=20 2.51.0 From nobody Fri Dec 19 11:14:18 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9429C3161A8; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251208-pixel-3-v6-8-e9e559d6f412@ixit.cz> References: <20251208-pixel-3-v6-0-e9e559d6f412@ixit.cz> In-Reply-To: <20251208-pixel-3-v6-0-e9e559d6f412@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sumit Semwal , Casey Connolly , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Marijn Suijten , Dmitry Baryshkov , Vinod Koul , Petr Hodina , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Heidelberg , Amit Pundir , Casey Connolly , Joel Selvaraj , Konrad Dybcio , Bjorn Andersson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=17793; i=david@ixit.cz; h=from:subject:message-id; bh=V19W2ftZf1FS3O1JmsGWEcuKVDBgilB9pehSL6TR4VM=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpNp1/HCAGH0aChSbcIMAbfp1ssFjcF2cdRvCc5 VUqx2G8cQaJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaTadfwAKCRBgAj/E00kg ciQUEACH89btpUG1vR0eNn/0A2rteXJ/CYumoYdnEkOY8AYJFD+BmM9x8i4FHSx6JtHJXTHlRKd fLCh/EPIWTNKyz8Ct2uiSGWodDuZYFY3DhhZrjh+6wvYrobUWl7I95e9PLW++NQDkBVNgX4eON3 FHv4AVoDDkVJCLJiJQTEYrQjFBeLOWWf9EnYwSUCv2qi4GRBdn0LOzuIcP2yeIpT0fWhi9tMwE2 FRgEFmXVrxP+FPYSGOqxZFOQnf8mNnxWPe8jFANCyCZ4qnrnzaWZzTyQpTr2PvCzq+K9c0NDB/9 U7Bue0Cn+4iAZlt3pYOqqs3JZsuXcnEi+Eqv7wjAuFwSajKtQk/oK6+Cely8KSadoWGHx41n6RO VQphfWY5xpevJX0gPhfxsp24Nx9I4/edpNUuaRTgCwxSWF4IW2si57SAC1KEbhwV1jgSNFOnYIm ALUGOWwwntrdMINhg0NQUh7hixzKIpHX7lhxKLswYM4mF6ePIEPcR6hrJjaTHih5RKNCJWtCL/A BRlyQhDtOeFoT7vhIDeVF9IV6aiOHVChFxLMeeVcbttiJRaWRvXtgnIdSU81uxchR8Ru2oBDaNg 1YkmIoDn32fSaqdjX4dF99gIytIv4M8k+37iZm4YAAFgACAAlQ2lZ7IUiJ3BJZ6uFZUqzeo8Dcw 0Uurk/LfPgC3L7Q== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg This adds initial device tree support for the following phones: - Google Pixel 3 (blueline) - Google Pixel 3 XL (crosshatch) Both phone boards use the same identifiers and differ only slightly in their connected peripherals. Supported functionality includes: - Debug UART - UFS - USB-C (peripheral mode) - Framebuffer (both u-boot and Linux) - Display (Pixel 3 only, and the driver needs work) - GPU - Bluetooth - Wi-Fi The rmtfs region is allocated using UIO, making it technically "dynamic." Its address and size can be read from sysfs: $ cat /sys/class/uio/uio0/name /sys/class/uio/uio0/maps/map0/addr 0x00000000f2701000 $ cat /sys/class/uio/uio0/maps/map0/size 0x0000000000200000 Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either side of the rmtfs region to work around an XPU bug that would otherwise cause erroneous violations when accessing the rmtfs_mem region. Co-developed-by: Amit Pundir Signed-off-by: Amit Pundir Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Co-developed-by: Casey Connolly Signed-off-by: Casey Connolly Co-developed-by: Joel Selvaraj Signed-off-by: Joel Selvaraj Co-developed-by: Sumit Semwal Signed-off-by: Sumit Semwal Co-developed-by: Vinod Koul Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: David Heidelberg --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 85 ++++ arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 524 +++++++++++++++++= ++++ .../boot/dts/qcom/sdm845-google-crosshatch.dts | 33 ++ 4 files changed, 644 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 6f34d5ed331c4..c853b28b3b198 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -250,6 +250,8 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine-dtbs :=3D sdm845-db845c.dtb sdm845-db84= 5c-navigation-mezzanine.dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-db845c-navigation-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-google-crosshatch.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-google-blueline.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-lg-judyln.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-lg-judyp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm= 64/boot/dts/qcom/sdm845-google-blueline.dts new file mode 100644 index 0000000000000..cb9716ed3da33 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sdm845-google-common.dtsi" + +/ { + model =3D "Google Pixel 3"; + compatible =3D "google,blueline", "qcom,sdm845"; +}; + +&battery { + charge-full-design-microamp-hours =3D <2970000>; + voltage-min-design-microvolt =3D <3600000>; + voltage-max-design-microvolt =3D <4400000>; +}; + +&framebuffer0 { + width =3D <1080>; + height =3D <2160>; + stride =3D <(1080 * 4)>; +}; + +&i2c2 { + clock-frequency =3D <1000000>; + + status =3D "okay"; + + /* ST,FTS @ 49 */ +}; + +&mdss_dsi0 { + vdda-supply =3D <&vdda_mipi_dsi0_1p2>; + + status =3D "okay"; + + panel@0 { + compatible =3D "lg,sw43408-lh546wf1-ed01", "lg,sw43408"; + reg =3D <0>; + + vddi-supply =3D <&vreg_l14a_1p8>; + vpnl-supply =3D <&vreg_l28a_3p0>; + + reset-gpios =3D <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&panel_default>; + pinctrl-names =3D "default"; + + port { + panel_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&panel_in>; + qcom,te-source =3D "mdp_vsync_e"; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vdda_mipi_dsi0_pll>; + + status =3D "okay"; +}; + +&tlmm { + panel_default: panel-default-state { + reset-pins { + pins =3D "gpio6"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + te-pins { + pins =3D "gpio12"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm6= 4/boot/dts/qcom/sdm845-google-common.dtsi new file mode 100644 index 0000000000000..00b653c40be85 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -0,0 +1,524 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &rmtfs_mem; + +/ { + chassis-type =3D "handset"; + qcom,board-id =3D <0x00021505 0>; + qcom,msm-id =3D ; + + aliases { + serial0 =3D &uart9; + serial1 =3D &uart6; + }; + + battery: battery { + compatible =3D "simple-battery"; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "serial0:115200n8"; + + /* Use display framebuffer as setup by bootloader */ + framebuffer0: framebuffer-0 { + compatible =3D "simple-framebuffer"; + memory-region =3D <&cont_splash_mem>; + + format =3D "a8r8g8b8"; + }; + }; + + reserved-memory { + cont_splash_mem: splash@9d400000 { + reg =3D <0 0x9d400000 0 0x02400000>; + no-map; + }; + + mpss_region: memory@8e000000 { + reg =3D <0 0x8e000000 0 0x9800000>; + no-map; + }; + + venus_mem: venus@97800000 { + reg =3D <0 0x97800000 0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp-mem@97D00000 { + reg =3D <0 0x97D00000 0 0x800000>; + no-map; + }; + + mba_region: mba@98500000 { + reg =3D <0 0x98500000 0 0x200000>; + no-map; + }; + + slpi_mem: slpi@98700000 { + reg =3D <0 0x98700000 0 0x1400000>; + no-map; + }; + + spss_mem: spss@99B00000 { + reg =3D <0 0x99B00000 0 0x100000>; + no-map; + }; + + rmtfs_mem: rmtfs-region@f2700000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0 0xf2700000 0 0x202000>; + qcom,use-guard-pages; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D ; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + label =3D "Volume keys"; + autorepeat; + + pinctrl-0 =3D <&volume_up_gpio>; + pinctrl-names =3D "default"; + + key-vol-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + }; + + vreg_s4a_1p8: regulator-vreg-s4a-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_s4a_1p8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vph_pwr>; + }; +}; + +&adsp_pas { + firmware-name =3D "qcom/sdm845/Google/blueline/adsp.mbn"; + + status =3D "okay"; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + vdd-s7-supply =3D <&vph_pwr>; + vdd-s8-supply =3D <&vph_pwr>; + vdd-s9-supply =3D <&vph_pwr>; + vdd-s10-supply =3D <&vph_pwr>; + vdd-s11-supply =3D <&vph_pwr>; + vdd-s12-supply =3D <&vph_pwr>; + vdd-s13-supply =3D <&vph_pwr>; + vdd-l1-l27-supply =3D <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply =3D <&vreg_s3a_1p35>; + vdd-l3-l11-supply =3D <&vreg_s7a_1p025>; + vdd-l4-l5-supply =3D <&vreg_s7a_1p025>; + vdd-l6-supply =3D <&vph_pwr>; + vdd-l7-l12-l14-l15-supply =3D <&vreg_s5a_2p04>; + vdd-l9-supply =3D <&vreg_bob>; + vdd-l10-l23-l25-supply =3D <&vreg_bob>; + vdd-l13-l19-l21-supply =3D <&vreg_bob>; + vdd-l16-l28-supply =3D <&vreg_bob>; + vdd-l18-l22-supply =3D <&vreg_bob>; + vdd-l20-l24-supply =3D <&vreg_bob>; + vdd-l26-supply =3D <&vreg_s3a_1p35>; + vin-lvs-1-2-supply =3D <&vreg_s4a_1p8>; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt =3D <1352000>; + regulator-max-microvolt =3D <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt =3D <1904000>; + regulator-max-microvolt =3D <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1028000>; + }; + + vdda_mipi_dsi0_pll: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-boot-on; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-initial-mode =3D ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt =3D <1304000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l19a_3p3: ldo19 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + /* + * The touchscreen needs this to be 3.3v, which is apparently + * quite close to the hardware limit for this LDO (3.312v) + * It must be kept in high power mode to prevent TS brownouts + */ + regulator-allowed-modes =3D ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2968000>; + regulator-initial-mode =3D ; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2968000>; + regulator-initial-mode =3D ; + }; + + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt =3D <3088000>; + regulator-max-microvolt =3D <3088000>; + regulator-initial-mode =3D ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + }; + + vdda_mipi_dsi0_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-boot-on; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt =3D <2856000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-bob-supply =3D <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt =3D <3312000>; + regulator-max-microvolt =3D <3600000>; + regulator-initial-mode =3D ; + regulator-allow-bypass; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <600000>; + }; + }; +}; + +&cdsp_pas { + firmware-name =3D "qcom/sdm845/Google/blueline/cdsp.mbn"; + + status =3D "okay"; +}; + +&gcc { + protected-clocks =3D , + , + ; +}; + +&gpi_dma0 { + status =3D "okay"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/sdm845/Google/blueline/a630_zap.mbn"; +}; + +&i2c12 { + /* Bottom spkr (right) CS35L36 @ 40 */ + + /* Top spkr (left) CS35L36 @ 41 */ +}; + +&ipa { + firmware-name =3D "qcom/sdm845/Google/blueline/ipa_fws.mbn"; + memory-region =3D <&ipa_fw_mem>; + + status =3D "okay"; +}; + +&mdss { + status =3D "okay"; +}; + +&mss_pil { + firmware-name =3D "qcom/sdm845/Google/blueline/mba.mbn", + "qcom/sdm845/Google/blueline/modem.mbn"; + + status =3D "okay"; +}; + +&pm8998_gpios { + volume_up_gpio: vol-up-active-state { + pins =3D "gpio6"; + function =3D "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength =3D <0>; + }; +}; + +&pm8998_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&pmi8998_charger { + monitored-battery =3D <&battery>; + + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&qup_uart9_rx { + drive-strength =3D <2>; + bias-pull-up; +}; + +&qup_uart9_tx { + drive-strength =3D <2>; + bias-disable; +}; + +&tlmm { + gpio-reserved-ranges =3D < 0 4>, /* SPI (Intel MNH Pixel Visual Core) */ + <81 4>; /* SPI (most likely Fingerprint Cards FPC1075) */ + + touchscreen_reset: ts-reset-state { + pins =3D "gpio99"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + }; + + touchscreen_pins: ts-pins-gpio-state { + pins =3D "gpio125"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + touchscreen_i2c_pins: qup-i2c2-gpio-state { + pins =3D "gpio27", "gpio28"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; + +&uart6 { + pinctrl-0 =3D <&qup_uart6_4pin>; + + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn3990-bt"; + + vddio-supply =3D <&vreg_s4a_1p8>; + vddxo-supply =3D <&vreg_l7a_1p8>; + vddrf-supply =3D <&vreg_l17a_1p3>; + vddch0-supply =3D <&vreg_l25a_3p3>; + max-speed =3D <3200000>; + }; +}; + +&uart9 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l20a_2p95>; + vcc-max-microamp =3D <800000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1a_0p875>; + vdda-pll-supply =3D <&vreg_l26a_1p2>; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l1a_0p875>; + vdda-pll-supply =3D <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply =3D <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value =3D <8>; + qcom,hstx-trim-value =3D ; + qcom,preemphasis-level =3D ; + qcom,preemphasis-width =3D ; + + status =3D "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply =3D <&vreg_l26a_1p2>; + vdda-pll-supply =3D <&vreg_l1a_0p875>; + + status =3D "okay"; +}; + +&venus { + firmware-name =3D "qcom/sdm845/Google/blueline/venus.mbn"; + + status =3D "okay"; +}; + +&wifi { + vdd-0.8-cx-mx-supply =3D <&vreg_l5a_0p8>; + vdd-1.8-xo-supply =3D <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply =3D <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply =3D <&vreg_l25a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; + + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/a= rm64/boot/dts/qcom/sdm845-google-crosshatch.dts new file mode 100644 index 0000000000000..5aa02be1c864e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sdm845-google-common.dtsi" + +/ { + model =3D "Google Pixel 3 XL"; + compatible =3D "google,crosshatch", "qcom,sdm845"; +}; + +&battery { + charge-full-design-microamp-hours =3D <3480000>; + voltage-min-design-microvolt =3D <3600000>; + voltage-max-design-microvolt =3D <4400000>; +}; + +&dispcc { + /* Disable for now so simple-framebuffer continues working */ + status =3D "disabled"; +}; + +&framebuffer0 { + width =3D <1440>; + height =3D <2960>; + stride =3D <(1440 * 4)>; +}; + +&mdss { + /* Disable for now so simple-framebuffer continues working */ + status =3D "disabled"; +}; + --=20 2.51.0